1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Unisoc UMS512 SoC DTS file
5 * Copyright (C) 2021, Unisoc Inc.
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
51 compatible = "arm,cortex-a55";
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD>;
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD>;
67 compatible = "arm,cortex-a55";
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD>;
75 compatible = "arm,cortex-a55";
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD>;
83 compatible = "arm,cortex-a55";
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD>;
91 compatible = "arm,cortex-a55";
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD>;
99 compatible = "arm,cortex-a55";
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD>;
107 compatible = "arm,cortex-a55";
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD>;
115 entry-method = "psci";
117 compatible = "arm,idle-state";
118 entry-latency-us = <4000>;
119 exit-latency-us = <4000>;
120 min-residency-us = <10000>;
122 arm,psci-suspend-param = <0x00010000>;
127 compatible = "arm,psci-0.2";
132 compatible = "arm,armv8-timer";
133 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
134 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
135 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
136 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
140 compatible = "arm,armv8-pmuv3";
141 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
152 compatible = "simple-bus";
153 #address-cells = <2>;
157 gic: interrupt-controller@12000000 {
158 compatible = "arm,gic-v3";
159 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
160 <0x0 0x12040000 0 0x100000>; /* GICR */
161 #interrupt-cells = <3>;
162 #address-cells = <2>;
165 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
166 #redistributor-regions = <1>;
167 interrupt-controller;
168 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
171 ap_ahb_regs: syscon@20100000 {
172 compatible = "sprd,ums512-glbregs", "syscon",
174 reg = <0 0x20100000 0 0x4000>;
175 #address-cells = <1>;
177 ranges = <0 0 0x20100000 0x4000>;
179 apahb_gate: clock-controller@0 {
180 compatible = "sprd,ums512-apahb-gate";
183 clock-names = "ext-26m";
188 pub_apb_regs: syscon@31050000 {
189 compatible = "sprd,ums512-glbregs", "syscon",
191 reg = <0 0x31050000 0 0x9000>;
194 top_dvfs_apb_regs: syscon@322a0000 {
195 compatible = "sprd,ums512-glbregs", "syscon",
197 reg = <0 0x322a0000 0 0x8000>;
200 ap_intc0_regs: syscon@32310000 {
201 compatible = "sprd,ums512-glbregs", "syscon",
203 reg = <0 0x32310000 0 0x1000>;
206 ap_intc1_regs: syscon@32320000 {
207 compatible = "sprd,ums512-glbregs", "syscon",
209 reg = <0 0x32320000 0 0x1000>;
212 ap_intc2_regs: syscon@32330000 {
213 compatible = "sprd,ums512-glbregs", "syscon",
215 reg = <0 0x32330000 0 0x1000>;
218 ap_intc3_regs: syscon@32340000 {
219 compatible = "sprd,ums512-glbregs", "syscon",
221 reg = <0 0x32340000 0 0x1000>;
224 ap_intc4_regs: syscon@32350000 {
225 compatible = "sprd,ums512-glbregs", "syscon",
227 reg = <0 0x32350000 0 0x1000>;
230 ap_intc5_regs: syscon@32360000 {
231 compatible = "sprd,ums512-glbregs", "syscon",
233 reg = <0 0x32360000 0 0x1000>;
236 anlg_phy_g0_regs: syscon@32390000 {
237 compatible = "sprd,ums512-glbregs", "syscon",
239 reg = <0 0x32390000 0 0x3000>;
240 #address-cells = <1>;
242 ranges = <0 0 0x32390000 0x3000>;
244 dpll0: clock-controller@0 {
245 compatible = "sprd,ums512-g0-pll";
251 anlg_phy_g2_regs: syscon@323b0000 {
252 compatible = "sprd,ums512-glbregs", "syscon",
254 reg = <0 0x323b0000 0 0x3000>;
255 #address-cells = <1>;
257 ranges = <0 0 0x323b0000 0x3000>;
259 mpll1: clock-controller@0 {
260 compatible = "sprd,ums512-g2-pll";
266 anlg_phy_g3_regs: syscon@323c0000 {
267 compatible = "sprd,ums512-glbregs", "syscon",
269 reg = <0 0x323c0000 0 0x3000>;
270 #address-cells = <1>;
272 ranges = <0 0 0x323c0000 0x3000>;
274 pll1: clock-controller@0 {
275 compatible = "sprd,ums512-g3-pll";
278 clock-names = "ext-26m";
283 anlg_phy_gc_regs: syscon@323e0000 {
284 compatible = "sprd,ums512-glbregs", "syscon",
286 reg = <0 0x323e0000 0 0x3000>;
287 #address-cells = <1>;
289 ranges = <0 0 0x323e0000 0x3000>;
291 pll2: clock-controller@0 {
292 compatible = "sprd,ums512-gc-pll";
294 clock-names = "ext-26m";
299 anlg_phy_g10_regs: syscon@323f0000 {
300 compatible = "sprd,ums512-glbregs", "syscon",
302 reg = <0 0x323f0000 0 0x3000>;
305 aon_apb_regs: syscon@327d0000 {
306 compatible = "sprd,ums512-glbregs", "syscon",
308 reg = <0 0x327d0000 0 0x3000>;
309 #address-cells = <1>;
311 ranges = <0 0 0x327d0000 0x3000>;
313 aonapb_gate: clock-controller@0 {
314 compatible = "sprd,ums512-aon-gate";
317 clock-names = "ext-26m";
322 pmu_apb_regs: syscon@327e0000 {
323 compatible = "sprd,ums512-glbregs", "syscon",
325 reg = <0 0x327e0000 0 0x3000>;
326 #address-cells = <1>;
328 ranges = <0 0 0x327e0000 0x3000>;
330 pmu_gate: clock-controller@0 {
331 compatible = "sprd,ums512-pmu-gate";
334 clock-names = "ext-26m";
339 audcp_apb_regs: syscon@3350d000 {
340 compatible = "sprd,ums512-glbregs", "syscon",
342 reg = <0 0x3350d000 0 0x1000>;
343 #address-cells = <1>;
345 ranges = <0 0 0x3350d000 0x1000>;
347 audcpapb_gate: clock-controller@0 {
348 compatible = "sprd,ums512-audcpapb-gate";
354 audcp_ahb_regs: syscon@335e0000 {
355 compatible = "sprd,ums512-glbregs", "syscon",
357 reg = <0 0x335e0000 0 0x1000>;
358 #address-cells = <1>;
360 ranges = <0 0 0x335e0000 0x1000>;
362 audcpahb_gate: clock-controller@0 {
363 compatible = "sprd,ums512-audcpahb-gate";
369 gpu_apb_regs: syscon@60100000 {
370 compatible = "sprd,ums512-glbregs", "syscon",
372 reg = <0 0x60100000 0 0x3000>;
373 #address-cells = <1>;
375 ranges = <0 0 0x60100000 0x3000>;
377 gpu_clk: clock-controller@0 {
378 compatible = "sprd,ums512-gpu-clk";
380 clock-names = "ext-26m";
386 gpu_dvfs_apb_regs: syscon@60110000 {
387 compatible = "sprd,ums512-glbregs", "syscon",
389 reg = <0 0x60110000 0 0x3000>;
392 mm_ahb_regs: syscon@62200000 {
393 compatible = "sprd,ums512-glbregs", "syscon",
395 reg = <0 0x62200000 0 0x3000>;
396 #address-cells = <1>;
398 ranges = <0 0 0x62200000 0x3000>;
400 mm_gate: clock-controller@0 {
401 compatible = "sprd,ums512-mm-gate-clk";
407 ap_apb_regs: syscon@71000000 {
408 compatible = "sprd,ums512-glbregs", "syscon",
410 reg = <0 0x71000000 0 0x3000>;
411 #address-cells = <1>;
413 ranges = <0 0 0x71000000 0x3000>;
415 apapb_gate: clock-controller@0 {
416 compatible = "sprd,ums512-apapb-gate";
422 ap_clk: clock-controller@20200000 {
423 compatible = "sprd,ums512-ap-clk";
424 reg = <0 0x20200000 0 0x1000>;
426 clock-names = "ext-26m";
430 aon_clk: clock-controller@32080000 {
431 compatible = "sprd,ums512-aonapb-clk";
432 reg = <0 0x32080000 0 0x1000>;
433 clocks = <&ext_26m>, <&ext_32k>,
434 <&ext_4m>, <&rco_100m>;
435 clock-names = "ext-26m", "ext-32k",
436 "ext-4m", "rco-100m";
440 mm_clk: clock-controller@62100000 {
441 compatible = "sprd,ums512-mm-clk";
442 reg = <0 0x62100000 0 0x1000>;
444 clock-names = "ext-26m";
450 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
451 reg = <0 0x3c002000 0 0x1000>;
453 clock-names = "apb_pclk";
457 funnel_soc_out_port: endpoint {
458 remote-endpoint = <&etb_in>;
464 #address-cells = <1>;
469 funnel_soc_in_port: endpoint {
471 <&funnel_corinth_out_port>;
478 soc_etb: etb@3c003000 {
479 compatible = "arm,coresight-tmc", "arm,primecell";
480 reg = <0 0x3c003000 0 0x1000>;
482 clock-names = "apb_pclk";
488 <&funnel_soc_out_port>;
494 /* AP-CPU Funnel for core3/4/5/7 */
496 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
497 reg = <0 0x3e001000 0 0x1000>;
499 clock-names = "apb_pclk";
503 funnel_corinth_lit_out_port: endpoint {
505 <&corinth_etf_lit_in>;
511 #address-cells = <1>;
516 funnel_core_in_port3: endpoint {
517 remote-endpoint = <&etm3_out>;
523 funnel_core_in_port4: endpoint {
524 remote-endpoint = <&etm4_out>;
530 funnel_core_in_port5: endpoint {
531 remote-endpoint = <&etm5_out>;
537 funnel_core_in_port7: endpoint {
538 remote-endpoint = <&etm7_out>;
544 /* AP-CPU ETF for little cores */
546 compatible = "arm,coresight-tmc", "arm,primecell";
547 reg = <0 0x3e002000 0 0x1000>;
549 clock-names = "apb_pclk";
553 corinth_etf_lit_out: endpoint {
555 <&funnel_corinth_from_lit_in_port>;
562 corinth_etf_lit_in: endpoint {
564 <&funnel_corinth_lit_out_port>;
570 /* AP-CPU ETF for big cores */
572 compatible = "arm,coresight-tmc", "arm,primecell";
573 reg = <0 0x3e003000 0 0x1000>;
575 clock-names = "apb_pclk";
579 corinth_etf_big_out: endpoint {
581 <&funnel_corinth_from_big_in_port>;
588 corinth_etf_big_in: endpoint {
590 <&funnel_corinth_big_out_port>;
598 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
599 reg = <0 0x3e004000 0 0x1000>;
601 clock-names = "apb_pclk";
605 funnel_corinth_out_port: endpoint {
607 <&funnel_soc_in_port>;
613 #address-cells = <1>;
618 funnel_corinth_from_lit_in_port: endpoint {
619 remote-endpoint = <&corinth_etf_lit_out>;
625 funnel_corinth_from_big_in_port: endpoint {
626 remote-endpoint = <&corinth_etf_big_out>;
632 /* AP-CPU Funnel for core0/1/2/6 */
634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
635 reg = <0 0x3e005000 0 0x1000>;
637 clock-names = "apb_pclk";
641 funnel_corinth_big_out_port: endpoint {
642 remote-endpoint = <&corinth_etf_big_in>;
648 #address-cells = <1>;
653 funnel_core_in_port0: endpoint {
654 remote-endpoint = <&etm0_out>;
660 funnel_core_in_port1: endpoint {
661 remote-endpoint = <&etm1_out>;
667 funnel_core_in_port2: endpoint {
668 remote-endpoint = <&etm2_out>;
674 funnel_core_in_port6: endpoint {
675 remote-endpoint = <&etm6_out>;
682 compatible = "arm,coresight-etm4x", "arm,primecell";
683 reg = <0 0x3f040000 0 0x1000>;
685 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
686 clock-names = "apb_pclk", "clk_cs", "cs_src";
692 <&funnel_core_in_port0>;
699 compatible = "arm,coresight-etm4x", "arm,primecell";
700 reg = <0 0x3f140000 0 0x1000>;
702 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
703 clock-names = "apb_pclk", "clk_cs", "cs_src";
709 <&funnel_core_in_port1>;
716 compatible = "arm,coresight-etm4x", "arm,primecell";
717 reg = <0 0x3f240000 0 0x1000>;
719 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
720 clock-names = "apb_pclk", "clk_cs", "cs_src";
726 <&funnel_core_in_port2>;
733 compatible = "arm,coresight-etm4x", "arm,primecell";
734 reg = <0 0x3f340000 0 0x1000>;
736 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
737 clock-names = "apb_pclk", "clk_cs", "cs_src";
743 <&funnel_core_in_port3>;
750 compatible = "arm,coresight-etm4x", "arm,primecell";
751 reg = <0 0x3f440000 0 0x1000>;
753 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
754 clock-names = "apb_pclk", "clk_cs", "cs_src";
760 <&funnel_core_in_port4>;
767 compatible = "arm,coresight-etm4x", "arm,primecell";
768 reg = <0 0x3f540000 0 0x1000>;
770 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
771 clock-names = "apb_pclk", "clk_cs", "cs_src";
777 <&funnel_core_in_port5>;
784 compatible = "arm,coresight-etm4x", "arm,primecell";
785 reg = <0 0x3f640000 0 0x1000>;
787 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
788 clock-names = "apb_pclk", "clk_cs", "cs_src";
794 <&funnel_core_in_port6>;
801 compatible = "arm,coresight-etm4x", "arm,primecell";
802 reg = <0 0x3f740000 0 0x1000>;
804 clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
805 clock-names = "apb_pclk", "clk_cs", "cs_src";
811 <&funnel_core_in_port7>;
818 compatible = "simple-bus";
819 #address-cells = <1>;
821 ranges = <0 0x0 0x70000000 0x10000000>;
824 compatible = "sprd,ums512-uart",
827 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
832 uart1: serial@100000 {
833 compatible = "sprd,ums512-uart",
835 reg = <0x100000 0x100>;
836 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
842 compatible = "sprd,sdhci-r11";
843 reg = <0x1100000 0x1000>;
844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "sdio", "enable";
846 clocks = <&ap_clk CLK_SDIO0_2X>,
847 <&apapb_gate CLK_SDIO0_EB>;
848 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
849 assigned-clock-parents = <&pll1 CLK_RPLL>;
854 compatible = "sprd,sdhci-r11";
855 reg = <0x1400000 0x1000>;
856 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
857 clock-names = "sdio", "enable";
858 clocks = <&ap_clk CLK_EMMC_2X>,
859 <&apapb_gate CLK_EMMC_EB>;
860 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
861 assigned-clock-parents = <&pll1 CLK_RPLL>;
867 compatible = "simple-bus";
868 #address-cells = <1>;
870 ranges = <0 0x0 0x32000000 0x1000000>;
872 adi_bus: spi@100000 {
873 compatible = "sprd,ums512-adi";
874 reg = <0x100000 0x100000>;
875 #address-cells = <1>;
877 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
878 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
879 <35 0x19b8>, <39 0x19ac>;
885 compatible = "fixed-clock";
887 clock-frequency = <26000000>;
888 clock-output-names = "ext-26m";
892 compatible = "fixed-clock";
894 clock-frequency = <32768>;
895 clock-output-names = "ext-32k";
899 compatible = "fixed-clock";
901 clock-frequency = <4000000>;
902 clock-output-names = "ext-4m";
906 compatible = "fixed-clock";
908 clock-frequency = <100000000>;
909 clock-output-names = "rco-100m";