1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
5 // Copyright (C) 2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-pxs3";
17 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 clocks = <&sys_clk 33>;
45 enable-method = "psci";
46 operating-points-v2 = <&cluster0_opp>;
51 compatible = "arm,cortex-a53", "arm,armv8";
53 clocks = <&sys_clk 33>;
54 enable-method = "psci";
55 operating-points-v2 = <&cluster0_opp>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 clocks = <&sys_clk 33>;
63 enable-method = "psci";
64 operating-points-v2 = <&cluster0_opp>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 clocks = <&sys_clk 33>;
72 enable-method = "psci";
73 operating-points-v2 = <&cluster0_opp>;
77 cluster0_opp: opp-table {
78 compatible = "operating-points-v2";
82 opp-hz = /bits/ 64 <250000000>;
83 clock-latency-ns = <300>;
86 opp-hz = /bits/ 64 <325000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <500000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <650000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <666667000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <866667000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <1000000000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <1300000000>;
111 clock-latency-ns = <300>;
116 compatible = "arm,psci-1.0";
122 compatible = "fixed-clock";
124 clock-frequency = <25000000>;
128 emmc_pwrseq: emmc-pwrseq {
129 compatible = "mmc-pwrseq-emmc";
130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
134 compatible = "arm,armv8-timer";
135 interrupts = <1 13 4>,
142 compatible = "simple-bus";
143 #address-cells = <1>;
145 ranges = <0 0 0 0xffffffff>;
147 serial0: serial@54006800 {
148 compatible = "socionext,uniphier-uart";
150 reg = <0x54006800 0x40>;
151 interrupts = <0 33 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_uart0>;
154 clocks = <&peri_clk 0>;
155 resets = <&peri_rst 0>;
158 serial1: serial@54006900 {
159 compatible = "socionext,uniphier-uart";
161 reg = <0x54006900 0x40>;
162 interrupts = <0 35 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_uart1>;
165 clocks = <&peri_clk 1>;
166 resets = <&peri_rst 1>;
169 serial2: serial@54006a00 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006a00 0x40>;
173 interrupts = <0 37 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart2>;
176 clocks = <&peri_clk 2>;
177 resets = <&peri_rst 2>;
180 serial3: serial@54006b00 {
181 compatible = "socionext,uniphier-uart";
183 reg = <0x54006b00 0x40>;
184 interrupts = <0 177 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart3>;
187 clocks = <&peri_clk 3>;
188 resets = <&peri_rst 3>;
191 gpio: gpio@55000000 {
192 compatible = "socionext,uniphier-gpio";
193 reg = <0x55000000 0x200>;
194 interrupt-parent = <&aidet>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
199 gpio-ranges = <&pinctrl 0 0 0>,
202 gpio-ranges-group-names = "gpio_range0",
206 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
211 compatible = "socionext,uniphier-fi2c";
213 reg = <0x58780000 0x80>;
214 #address-cells = <1>;
216 interrupts = <0 41 4>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_i2c0>;
219 clocks = <&peri_clk 4>;
220 resets = <&peri_rst 4>;
221 clock-frequency = <100000>;
225 compatible = "socionext,uniphier-fi2c";
227 reg = <0x58781000 0x80>;
228 #address-cells = <1>;
230 interrupts = <0 42 4>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c1>;
233 clocks = <&peri_clk 5>;
234 resets = <&peri_rst 5>;
235 clock-frequency = <100000>;
239 compatible = "socionext,uniphier-fi2c";
241 reg = <0x58782000 0x80>;
242 #address-cells = <1>;
244 interrupts = <0 43 4>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c2>;
247 clocks = <&peri_clk 6>;
248 resets = <&peri_rst 6>;
249 clock-frequency = <100000>;
253 compatible = "socionext,uniphier-fi2c";
255 reg = <0x58783000 0x80>;
256 #address-cells = <1>;
258 interrupts = <0 44 4>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_i2c3>;
261 clocks = <&peri_clk 7>;
262 resets = <&peri_rst 7>;
263 clock-frequency = <100000>;
266 /* chip-internal connection for HDMI */
268 compatible = "socionext,uniphier-fi2c";
269 reg = <0x58786000 0x80>;
270 #address-cells = <1>;
272 interrupts = <0 26 4>;
273 clocks = <&peri_clk 10>;
274 resets = <&peri_rst 10>;
275 clock-frequency = <400000>;
278 system_bus: system-bus@58c00000 {
279 compatible = "socionext,uniphier-system-bus";
281 reg = <0x58c00000 0x400>;
282 #address-cells = <2>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_system_bus>;
289 compatible = "socionext,uniphier-smpctrl";
290 reg = <0x59801000 0x400>;
294 compatible = "socionext,uniphier-pxs3-sdctrl",
295 "simple-mfd", "syscon";
296 reg = <0x59810000 0x400>;
299 compatible = "socionext,uniphier-pxs3-sd-clock";
304 compatible = "socionext,uniphier-pxs3-sd-reset";
310 compatible = "socionext,uniphier-pxs3-perictrl",
311 "simple-mfd", "syscon";
312 reg = <0x59820000 0x200>;
315 compatible = "socionext,uniphier-pxs3-peri-clock";
320 compatible = "socionext,uniphier-pxs3-peri-reset";
325 emmc: sdhc@5a000000 {
326 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
327 reg = <0x5a000000 0x400>;
328 interrupts = <0 78 4>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_emmc>;
331 clocks = <&sys_clk 4>;
332 resets = <&sys_rst 4>;
336 mmc-pwrseq = <&emmc_pwrseq>;
337 cdns,phy-input-delay-legacy = <9>;
338 cdns,phy-input-delay-mmc-highspeed = <2>;
339 cdns,phy-input-delay-mmc-ddr = <3>;
340 cdns,phy-dll-delay-sdclk = <21>;
341 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
344 soc_glue: soc-glue@5f800000 {
345 compatible = "socionext,uniphier-pxs3-soc-glue",
346 "simple-mfd", "syscon";
347 reg = <0x5f800000 0x2000>;
350 compatible = "socionext,uniphier-pxs3-pinctrl";
355 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
357 #address-cells = <1>;
359 ranges = <0 0x5f900000 0x2000>;
362 compatible = "socionext,uniphier-efuse";
367 compatible = "socionext,uniphier-efuse";
372 aidet: aidet@5fc20000 {
373 compatible = "socionext,uniphier-pxs3-aidet";
374 reg = <0x5fc20000 0x200>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 gic: interrupt-controller@5fe00000 {
380 compatible = "arm,gic-v3";
381 reg = <0x5fe00000 0x10000>, /* GICD */
382 <0x5fe80000 0x80000>; /* GICR */
383 interrupt-controller;
384 #interrupt-cells = <3>;
385 interrupts = <1 9 4>;
389 compatible = "socionext,uniphier-pxs3-sysctrl",
390 "simple-mfd", "syscon";
391 reg = <0x61840000 0x10000>;
394 compatible = "socionext,uniphier-pxs3-clock";
399 compatible = "socionext,uniphier-pxs3-reset";
404 compatible = "socionext,uniphier-wdt";
408 eth0: ethernet@65000000 {
409 compatible = "socionext,uniphier-pxs3-ave4";
411 reg = <0x65000000 0x8500>;
412 interrupts = <0 66 4>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_ether_rgmii>;
415 clock-names = "ether";
416 clocks = <&sys_clk 6>;
417 reset-names = "ether";
418 resets = <&sys_rst 6>;
419 phy-mode = "rgmii-id";
420 local-mac-address = [00 00 00 00 00 00];
421 socionext,syscon-phy-mode = <&soc_glue 0>;
424 #address-cells = <1>;
429 eth1: ethernet@65200000 {
430 compatible = "socionext,uniphier-pxs3-ave4";
432 reg = <0x65200000 0x8500>;
433 interrupts = <0 67 4>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_ether1_rgmii>;
436 clock-names = "ether";
437 clocks = <&sys_clk 7>;
438 reset-names = "ether";
439 resets = <&sys_rst 7>;
440 phy-mode = "rgmii-id";
441 local-mac-address = [00 00 00 00 00 00];
442 socionext,syscon-phy-mode = <&soc_glue 1>;
445 #address-cells = <1>;
450 nand: nand@68000000 {
451 compatible = "socionext,uniphier-denali-nand-v5b";
453 reg-names = "nand_data", "denali_reg";
454 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
455 interrupts = <0 65 4>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_nand>;
458 clocks = <&sys_clk 2>;
459 resets = <&sys_rst 2>;
464 #include "uniphier-pinctrl.dtsi"