1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
5 // Copyright (C) 2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
17 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53";
44 clocks = <&sys_clk 33>;
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a53";
55 clocks = <&sys_clk 33>;
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cluster0_opp>;
64 compatible = "arm,cortex-a53";
66 clocks = <&sys_clk 33>;
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 operating-points-v2 = <&cluster0_opp>;
75 compatible = "arm,cortex-a53";
77 clocks = <&sys_clk 33>;
78 enable-method = "psci";
79 next-level-cache = <&l2>;
80 operating-points-v2 = <&cluster0_opp>;
91 cluster0_opp: opp-table {
92 compatible = "operating-points-v2";
96 opp-hz = /bits/ 64 <250000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <325000000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <500000000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <650000000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <666667000>;
113 clock-latency-ns = <300>;
116 opp-hz = /bits/ 64 <866667000>;
117 clock-latency-ns = <300>;
120 opp-hz = /bits/ 64 <1000000000>;
121 clock-latency-ns = <300>;
124 opp-hz = /bits/ 64 <1300000000>;
125 clock-latency-ns = <300>;
130 compatible = "arm,psci-1.0";
136 compatible = "fixed-clock";
138 clock-frequency = <25000000>;
142 emmc_pwrseq: emmc-pwrseq {
143 compatible = "mmc-pwrseq-emmc";
144 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
148 compatible = "arm,armv8-timer";
149 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
157 polling-delay-passive = <250>; /* 250ms */
158 polling-delay = <1000>; /* 1000ms */
159 thermal-sensors = <&pvtctl>;
163 temperature = <110000>; /* 110C */
167 cpu_alert: cpu-alert {
168 temperature = <100000>; /* 100C */
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
187 #address-cells = <2>;
191 secure-memory@81000000 {
192 reg = <0x0 0x81000000 0x0 0x01000000>;
198 compatible = "simple-bus";
199 #address-cells = <1>;
201 ranges = <0 0 0 0xffffffff>;
204 compatible = "socionext,uniphier-scssi";
206 reg = <0x54006000 0x100>;
207 #address-cells = <1>;
209 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_spi0>;
212 clocks = <&peri_clk 11>;
213 resets = <&peri_rst 11>;
217 compatible = "socionext,uniphier-scssi";
219 reg = <0x54006100 0x100>;
220 #address-cells = <1>;
222 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_spi1>;
225 clocks = <&peri_clk 12>;
226 resets = <&peri_rst 12>;
229 serial0: serial@54006800 {
230 compatible = "socionext,uniphier-uart";
232 reg = <0x54006800 0x40>;
233 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart0>;
236 clocks = <&peri_clk 0>;
237 resets = <&peri_rst 0>;
240 serial1: serial@54006900 {
241 compatible = "socionext,uniphier-uart";
243 reg = <0x54006900 0x40>;
244 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart1>;
247 clocks = <&peri_clk 1>;
248 resets = <&peri_rst 1>;
251 serial2: serial@54006a00 {
252 compatible = "socionext,uniphier-uart";
254 reg = <0x54006a00 0x40>;
255 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart2>;
258 clocks = <&peri_clk 2>;
259 resets = <&peri_rst 2>;
262 serial3: serial@54006b00 {
263 compatible = "socionext,uniphier-uart";
265 reg = <0x54006b00 0x40>;
266 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart3>;
269 clocks = <&peri_clk 3>;
270 resets = <&peri_rst 3>;
273 gpio: gpio@55000000 {
274 compatible = "socionext,uniphier-gpio";
275 reg = <0x55000000 0x200>;
276 interrupt-parent = <&aidet>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
281 gpio-ranges = <&pinctrl 0 0 0>,
284 gpio-ranges-group-names = "gpio_range0",
288 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
293 compatible = "socionext,uniphier-fi2c";
295 reg = <0x58780000 0x80>;
296 #address-cells = <1>;
298 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c0>;
301 clocks = <&peri_clk 4>;
302 resets = <&peri_rst 4>;
303 clock-frequency = <100000>;
307 compatible = "socionext,uniphier-fi2c";
309 reg = <0x58781000 0x80>;
310 #address-cells = <1>;
312 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c1>;
315 clocks = <&peri_clk 5>;
316 resets = <&peri_rst 5>;
317 clock-frequency = <100000>;
321 compatible = "socionext,uniphier-fi2c";
323 reg = <0x58782000 0x80>;
324 #address-cells = <1>;
326 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_i2c2>;
329 clocks = <&peri_clk 6>;
330 resets = <&peri_rst 6>;
331 clock-frequency = <100000>;
335 compatible = "socionext,uniphier-fi2c";
337 reg = <0x58783000 0x80>;
338 #address-cells = <1>;
340 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_i2c3>;
343 clocks = <&peri_clk 7>;
344 resets = <&peri_rst 7>;
345 clock-frequency = <100000>;
348 /* chip-internal connection for HDMI */
350 compatible = "socionext,uniphier-fi2c";
351 reg = <0x58786000 0x80>;
352 #address-cells = <1>;
354 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&peri_clk 10>;
356 resets = <&peri_rst 10>;
357 clock-frequency = <400000>;
360 system_bus: system-bus@58c00000 {
361 compatible = "socionext,uniphier-system-bus";
363 reg = <0x58c00000 0x400>;
364 #address-cells = <2>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_system_bus>;
371 compatible = "socionext,uniphier-smpctrl";
372 reg = <0x59801000 0x400>;
375 sdctrl: syscon@59810000 {
376 compatible = "socionext,uniphier-pxs3-sdctrl",
377 "simple-mfd", "syscon";
378 reg = <0x59810000 0x400>;
380 sd_clk: clock-controller {
381 compatible = "socionext,uniphier-pxs3-sd-clock";
385 sd_rst: reset-controller {
386 compatible = "socionext,uniphier-pxs3-sd-reset";
392 compatible = "socionext,uniphier-pxs3-perictrl",
393 "simple-mfd", "syscon";
394 reg = <0x59820000 0x200>;
396 peri_clk: clock-controller {
397 compatible = "socionext,uniphier-pxs3-peri-clock";
401 peri_rst: reset-controller {
402 compatible = "socionext,uniphier-pxs3-peri-reset";
408 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
409 reg = <0x5a000000 0x400>;
410 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_emmc>;
413 clocks = <&sys_clk 4>;
414 resets = <&sys_rst 4>;
418 mmc-pwrseq = <&emmc_pwrseq>;
419 cdns,phy-input-delay-legacy = <9>;
420 cdns,phy-input-delay-mmc-highspeed = <2>;
421 cdns,phy-input-delay-mmc-ddr = <3>;
422 cdns,phy-dll-delay-sdclk = <21>;
423 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
427 compatible = "socionext,uniphier-sd-v3.1.1";
429 reg = <0x5a400000 0x800>;
430 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
431 pinctrl-names = "default", "uhs";
432 pinctrl-0 = <&pinctrl_sd>;
433 pinctrl-1 = <&pinctrl_sd_uhs>;
434 clocks = <&sd_clk 0>;
435 reset-names = "host";
436 resets = <&sd_rst 0>;
442 socionext,syscon-uhs-mode = <&sdctrl 0>;
445 soc_glue: syscon@5f800000 {
446 compatible = "socionext,uniphier-pxs3-soc-glue",
447 "simple-mfd", "syscon";
448 reg = <0x5f800000 0x2000>;
451 compatible = "socionext,uniphier-pxs3-pinctrl";
456 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
457 "simple-mfd", "syscon";
458 reg = <0x5f900000 0x2000>;
459 #address-cells = <1>;
461 ranges = <0 0x5f900000 0x2000>;
464 compatible = "socionext,uniphier-efuse";
469 compatible = "socionext,uniphier-efuse";
471 #address-cells = <1>;
475 usb_rterm0: trim@54,4 {
479 usb_rterm1: trim@55,4 {
483 usb_rterm2: trim@58,4 {
487 usb_rterm3: trim@59,4 {
491 usb_sel_t0: trim@54,0 {
495 usb_sel_t1: trim@55,0 {
499 usb_sel_t2: trim@58,0 {
503 usb_sel_t3: trim@59,0 {
507 usb_hs_i0: trim@56,0 {
511 usb_hs_i2: trim@5a,0 {
518 xdmac: dma-controller@5fc10000 {
519 compatible = "socionext,uniphier-xdmac";
520 reg = <0x5fc10000 0x5300>;
521 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
526 aidet: interrupt-controller@5fc20000 {
527 compatible = "socionext,uniphier-pxs3-aidet";
528 reg = <0x5fc20000 0x200>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
533 gic: interrupt-controller@5fe00000 {
534 compatible = "arm,gic-v3";
535 reg = <0x5fe00000 0x10000>, /* GICD */
536 <0x5fe80000 0x80000>; /* GICR */
537 interrupt-controller;
538 #interrupt-cells = <3>;
539 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
543 compatible = "socionext,uniphier-pxs3-sysctrl",
544 "simple-mfd", "syscon";
545 reg = <0x61840000 0x10000>;
547 sys_clk: clock-controller {
548 compatible = "socionext,uniphier-pxs3-clock";
552 sys_rst: reset-controller {
553 compatible = "socionext,uniphier-pxs3-reset";
558 compatible = "socionext,uniphier-wdt";
561 pvtctl: thermal-sensor {
562 compatible = "socionext,uniphier-pxs3-thermal";
563 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
564 #thermal-sensor-cells = <0>;
565 socionext,tmod-calibration = <0x0f22 0x68ee>;
569 eth0: ethernet@65000000 {
570 compatible = "socionext,uniphier-pxs3-ave4";
572 reg = <0x65000000 0x8500>;
573 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_ether_rgmii>;
576 clock-names = "ether";
577 clocks = <&sys_clk 6>;
578 reset-names = "ether";
579 resets = <&sys_rst 6>;
580 phy-mode = "rgmii-id";
581 local-mac-address = [00 00 00 00 00 00];
582 socionext,syscon-phy-mode = <&soc_glue 0>;
585 #address-cells = <1>;
590 eth1: ethernet@65200000 {
591 compatible = "socionext,uniphier-pxs3-ave4";
593 reg = <0x65200000 0x8500>;
594 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_ether1_rgmii>;
597 clock-names = "ether";
598 clocks = <&sys_clk 7>;
599 reset-names = "ether";
600 resets = <&sys_rst 7>;
601 phy-mode = "rgmii-id";
602 local-mac-address = [00 00 00 00 00 00];
603 socionext,syscon-phy-mode = <&soc_glue 1>;
606 #address-cells = <1>;
611 ahci0: sata@65600000 {
612 compatible = "socionext,uniphier-pxs3-ahci",
615 reg = <0x65600000 0x10000>;
616 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&sys_clk 28>;
618 resets = <&sys_rst 28>, <&ahci0_rst 0>;
619 ports-implemented = <1>;
623 sata-controller@65700000 {
624 compatible = "socionext,uniphier-pxs3-ahci-glue",
626 reg = <0x65700000 0x100>;
627 #address-cells = <1>;
629 ranges = <0 0x65700000 0x100>;
631 ahci0_rst: reset-controller@0 {
632 compatible = "socionext,uniphier-pxs3-ahci-reset";
634 clock-names = "link";
635 clocks = <&sys_clk 28>;
636 reset-names = "link";
637 resets = <&sys_rst 28>;
641 ahci0_phy: sata-phy@10 {
642 compatible = "socionext,uniphier-pxs3-ahci-phy";
644 clock-names = "link", "phy";
645 clocks = <&sys_clk 28>, <&sys_clk 30>;
646 reset-names = "link", "phy";
647 resets = <&sys_rst 28>, <&sys_rst 30>;
652 ahci1: sata@65800000 {
653 compatible = "socionext,uniphier-pxs3-ahci",
656 reg = <0x65800000 0x10000>;
657 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&sys_clk 29>;
659 resets = <&sys_rst 29>, <&ahci1_rst 0>;
660 ports-implemented = <1>;
664 sata-controller@65900000 {
665 compatible = "socionext,uniphier-pxs3-ahci-glue",
667 reg = <0x65900000 0x100>;
668 #address-cells = <1>;
670 ranges = <0 0x65900000 0x100>;
672 ahci1_rst: reset-controller@0 {
673 compatible = "socionext,uniphier-pxs3-ahci-reset";
675 clock-names = "link";
676 clocks = <&sys_clk 29>;
677 reset-names = "link";
678 resets = <&sys_rst 29>;
682 ahci1_phy: sata-phy@10 {
683 compatible = "socionext,uniphier-pxs3-ahci-phy";
685 clock-names = "link", "phy";
686 clocks = <&sys_clk 29>, <&sys_clk 30>;
687 reset-names = "link", "phy";
688 resets = <&sys_rst 29>, <&sys_rst 30>;
694 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
696 reg = <0x65a00000 0xcd00>;
697 interrupt-names = "dwc_usb3";
698 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
701 clock-names = "ref", "bus_early", "suspend";
702 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
703 resets = <&usb0_rst 15>;
704 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
705 <&usb0_ssphy0>, <&usb0_ssphy1>;
709 usb-controller@65b00000 {
710 compatible = "socionext,uniphier-pxs3-dwc3-glue",
712 reg = <0x65b00000 0x400>;
713 #address-cells = <1>;
715 ranges = <0 0x65b00000 0x400>;
717 usb0_rst: reset-controller@0 {
718 compatible = "socionext,uniphier-pxs3-usb3-reset";
721 clock-names = "link";
722 clocks = <&sys_clk 12>;
723 reset-names = "link";
724 resets = <&sys_rst 12>;
727 usb0_vbus0: regulator@100 {
728 compatible = "socionext,uniphier-pxs3-usb3-regulator";
730 clock-names = "link";
731 clocks = <&sys_clk 12>;
732 reset-names = "link";
733 resets = <&sys_rst 12>;
736 usb0_vbus1: regulator@110 {
737 compatible = "socionext,uniphier-pxs3-usb3-regulator";
739 clock-names = "link";
740 clocks = <&sys_clk 12>;
741 reset-names = "link";
742 resets = <&sys_rst 12>;
745 usb0_hsphy0: phy@200 {
746 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
749 clock-names = "link", "phy";
750 clocks = <&sys_clk 12>, <&sys_clk 16>;
751 reset-names = "link", "phy";
752 resets = <&sys_rst 12>, <&sys_rst 16>;
753 vbus-supply = <&usb0_vbus0>;
754 nvmem-cell-names = "rterm", "sel_t", "hs_i";
755 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
759 usb0_hsphy1: phy@210 {
760 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
763 clock-names = "link", "phy";
764 clocks = <&sys_clk 12>, <&sys_clk 16>;
765 reset-names = "link", "phy";
766 resets = <&sys_rst 12>, <&sys_rst 16>;
767 vbus-supply = <&usb0_vbus1>;
768 nvmem-cell-names = "rterm", "sel_t", "hs_i";
769 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
773 usb0_ssphy0: phy@300 {
774 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
777 clock-names = "link", "phy";
778 clocks = <&sys_clk 12>, <&sys_clk 17>;
779 reset-names = "link", "phy";
780 resets = <&sys_rst 12>, <&sys_rst 17>;
781 vbus-supply = <&usb0_vbus0>;
784 usb0_ssphy1: phy@310 {
785 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
788 clock-names = "link", "phy";
789 clocks = <&sys_clk 12>, <&sys_clk 18>;
790 reset-names = "link", "phy";
791 resets = <&sys_rst 12>, <&sys_rst 18>;
792 vbus-supply = <&usb0_vbus1>;
797 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
799 reg = <0x65c00000 0xcd00>;
800 interrupt-names = "dwc_usb3";
801 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
804 clock-names = "ref", "bus_early", "suspend";
805 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
806 resets = <&usb1_rst 15>;
807 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
812 usb-controller@65d00000 {
813 compatible = "socionext,uniphier-pxs3-dwc3-glue",
815 reg = <0x65d00000 0x400>;
816 #address-cells = <1>;
818 ranges = <0 0x65d00000 0x400>;
820 usb1_rst: reset-controller@0 {
821 compatible = "socionext,uniphier-pxs3-usb3-reset";
824 clock-names = "link";
825 clocks = <&sys_clk 13>;
826 reset-names = "link";
827 resets = <&sys_rst 13>;
830 usb1_vbus0: regulator@100 {
831 compatible = "socionext,uniphier-pxs3-usb3-regulator";
833 clock-names = "link";
834 clocks = <&sys_clk 13>;
835 reset-names = "link";
836 resets = <&sys_rst 13>;
839 usb1_vbus1: regulator@110 {
840 compatible = "socionext,uniphier-pxs3-usb3-regulator";
842 clock-names = "link";
843 clocks = <&sys_clk 13>;
844 reset-names = "link";
845 resets = <&sys_rst 13>;
848 usb1_hsphy0: phy@200 {
849 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
852 clock-names = "link", "phy", "phy-ext";
853 clocks = <&sys_clk 13>, <&sys_clk 20>,
855 reset-names = "link", "phy";
856 resets = <&sys_rst 13>, <&sys_rst 20>;
857 vbus-supply = <&usb1_vbus0>;
858 nvmem-cell-names = "rterm", "sel_t", "hs_i";
859 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
863 usb1_hsphy1: phy@210 {
864 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
867 clock-names = "link", "phy", "phy-ext";
868 clocks = <&sys_clk 13>, <&sys_clk 20>,
870 reset-names = "link", "phy";
871 resets = <&sys_rst 13>, <&sys_rst 20>;
872 vbus-supply = <&usb1_vbus1>;
873 nvmem-cell-names = "rterm", "sel_t", "hs_i";
874 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
878 usb1_ssphy0: phy@300 {
879 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
882 clock-names = "link", "phy", "phy-ext";
883 clocks = <&sys_clk 13>, <&sys_clk 21>,
885 reset-names = "link", "phy";
886 resets = <&sys_rst 13>, <&sys_rst 21>;
887 vbus-supply = <&usb1_vbus0>;
891 pcie: pcie@66000000 {
892 compatible = "socionext,uniphier-pcie";
894 reg-names = "dbi", "link", "config";
895 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
896 <0x2fff0000 0x10000>;
897 #address-cells = <3>;
899 clocks = <&sys_clk 24>;
900 resets = <&sys_rst 24>;
903 bus-range = <0x0 0xff>;
907 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
908 /* non-prefetchable memory */
909 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
910 #interrupt-cells = <1>;
911 interrupt-names = "dma", "msi";
912 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
914 interrupt-map-mask = <0 0 0 7>;
915 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
916 <0 0 0 2 &pcie_intc 1>, /* INTB */
917 <0 0 0 3 &pcie_intc 2>, /* INTC */
918 <0 0 0 4 &pcie_intc 3>; /* INTD */
919 phy-names = "pcie-phy";
922 pcie_intc: legacy-interrupt-controller {
923 interrupt-controller;
924 #interrupt-cells = <1>;
925 interrupt-parent = <&gic>;
926 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
930 pcie_phy: phy@66038000 {
931 compatible = "socionext,uniphier-pxs3-pcie-phy";
932 reg = <0x66038000 0x4000>;
934 clock-names = "link";
935 clocks = <&sys_clk 24>;
936 reset-names = "link";
937 resets = <&sys_rst 24>;
938 socionext,syscon = <&soc_glue>;
941 nand: nand-controller@68000000 {
942 compatible = "socionext,uniphier-denali-nand-v5b";
944 reg-names = "nand_data", "denali_reg";
945 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
946 #address-cells = <1>;
948 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&pinctrl_nand>;
951 clock-names = "nand", "nand_x", "ecc";
952 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
953 reset-names = "nand", "reg";
954 resets = <&sys_rst 2>, <&sys_rst 2>;
959 #include "uniphier-pinctrl.dtsi"