arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier PXs3 SoC
   4 //
   5 // Copyright (C) 2017 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "socionext,uniphier-pxs3";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                                 core2 {
  32                                         cpu = <&cpu2>;
  33                                 };
  34                                 core3 {
  35                                         cpu = <&cpu3>;
  36                                 };
  37                         };
  38                 };
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         reg = <0 0x000>;
  44                         clocks = <&sys_clk 33>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cluster0_opp>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0 0x001>;
  55                         clocks = <&sys_clk 33>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&l2>;
  58                         operating-points-v2 = <&cluster0_opp>;
  59                         #cooling-cells = <2>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         reg = <0 0x002>;
  66                         clocks = <&sys_clk 33>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&l2>;
  69                         operating-points-v2 = <&cluster0_opp>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu3: cpu@3 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0 0x003>;
  77                         clocks = <&sys_clk 33>;
  78                         enable-method = "psci";
  79                         next-level-cache = <&l2>;
  80                         operating-points-v2 = <&cluster0_opp>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 l2: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <2>;
  87                         cache-unified;
  88                 };
  89         };
  90
  91         cluster0_opp: opp-table {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-250000000 {
  96                         opp-hz = /bits/ 64 <250000000>;
  97                         clock-latency-ns = <300>;
  98                 };
  99                 opp-325000000 {
 100                         opp-hz = /bits/ 64 <325000000>;
 101                         clock-latency-ns = <300>;
 102                 };
 103                 opp-500000000 {
 104                         opp-hz = /bits/ 64 <500000000>;
 105                         clock-latency-ns = <300>;
 106                 };
 107                 opp-650000000 {
 108                         opp-hz = /bits/ 64 <650000000>;
 109                         clock-latency-ns = <300>;
 110                 };
 111                 opp-666667000 {
 112                         opp-hz = /bits/ 64 <666667000>;
 113                         clock-latency-ns = <300>;
 114                 };
 115                 opp-866667000 {
 116                         opp-hz = /bits/ 64 <866667000>;
 117                         clock-latency-ns = <300>;
 118                 };
 119                 opp-1000000000 {
 120                         opp-hz = /bits/ 64 <1000000000>;
 121                         clock-latency-ns = <300>;
 122                 };
 123                 opp-1300000000 {
 124                         opp-hz = /bits/ 64 <1300000000>;
 125                         clock-latency-ns = <300>;
 126                 };
 127         };
 128
 129         psci {
 130                 compatible = "arm,psci-1.0";
 131                 method = "smc";
 132         };
 133
 134         clocks {
 135                 refclk: ref {
 136                         compatible = "fixed-clock";
 137                         #clock-cells = <0>;
 138                         clock-frequency = <25000000>;
 139                 };
 140         };
 141
 142         emmc_pwrseq: emmc-pwrseq {
 143                 compatible = "mmc-pwrseq-emmc";
 144                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
 145         };
 146
 147         timer {
 148                 compatible = "arm,armv8-timer";
 149                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 153         };
 154
 155         thermal-zones {
 156                 cpu-thermal {
 157                         polling-delay-passive = <250>;  /* 250ms */
 158                         polling-delay = <1000>;         /* 1000ms */
 159                         thermal-sensors = <&pvtctl>;
 160
 161                         trips {
 162                                 cpu_crit: cpu-crit {
 163                                         temperature = <110000>; /* 110C */
 164                                         hysteresis = <2000>;
 165                                         type = "critical";
 166                                 };
 167                                 cpu_alert: cpu-alert {
 168                                         temperature = <100000>; /* 100C */
 169                                         hysteresis = <2000>;
 170                                         type = "passive";
 171                                 };
 172                         };
 173
 174                         cooling-maps {
 175                                 map0 {
 176                                         trip = <&cpu_alert>;
 177                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 179                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182                         };
 183                 };
 184         };
 185
 186         reserved-memory {
 187                 #address-cells = <2>;
 188                 #size-cells = <2>;
 189                 ranges;
 190
 191                 secure-memory@81000000 {
 192                         reg = <0x0 0x81000000 0x0 0x01000000>;
 193                         no-map;
 194                 };
 195         };
 196
 197         soc@0 {
 198                 compatible = "simple-bus";
 199                 #address-cells = <1>;
 200                 #size-cells = <1>;
 201                 ranges = <0 0 0 0xffffffff>;
 202
 203                 spi0: spi@54006000 {
 204                         compatible = "socionext,uniphier-scssi";
 205                         status = "disabled";
 206                         reg = <0x54006000 0x100>;
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 210                         pinctrl-names = "default";
 211                         pinctrl-0 = <&pinctrl_spi0>;
 212                         clocks = <&peri_clk 11>;
 213                         resets = <&peri_rst 11>;
 214                 };
 215
 216                 spi1: spi@54006100 {
 217                         compatible = "socionext,uniphier-scssi";
 218                         status = "disabled";
 219                         reg = <0x54006100 0x100>;
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 223                         pinctrl-names = "default";
 224                         pinctrl-0 = <&pinctrl_spi1>;
 225                         clocks = <&peri_clk 12>;
 226                         resets = <&peri_rst 12>;
 227                 };
 228
 229                 serial0: serial@54006800 {
 230                         compatible = "socionext,uniphier-uart";
 231                         status = "disabled";
 232                         reg = <0x54006800 0x40>;
 233                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_uart0>;
 236                         clocks = <&peri_clk 0>;
 237                         resets = <&peri_rst 0>;
 238                 };
 239
 240                 serial1: serial@54006900 {
 241                         compatible = "socionext,uniphier-uart";
 242                         status = "disabled";
 243                         reg = <0x54006900 0x40>;
 244                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 245                         pinctrl-names = "default";
 246                         pinctrl-0 = <&pinctrl_uart1>;
 247                         clocks = <&peri_clk 1>;
 248                         resets = <&peri_rst 1>;
 249                 };
 250
 251                 serial2: serial@54006a00 {
 252                         compatible = "socionext,uniphier-uart";
 253                         status = "disabled";
 254                         reg = <0x54006a00 0x40>;
 255                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 256                         pinctrl-names = "default";
 257                         pinctrl-0 = <&pinctrl_uart2>;
 258                         clocks = <&peri_clk 2>;
 259                         resets = <&peri_rst 2>;
 260                 };
 261
 262                 serial3: serial@54006b00 {
 263                         compatible = "socionext,uniphier-uart";
 264                         status = "disabled";
 265                         reg = <0x54006b00 0x40>;
 266                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 267                         pinctrl-names = "default";
 268                         pinctrl-0 = <&pinctrl_uart3>;
 269                         clocks = <&peri_clk 3>;
 270                         resets = <&peri_rst 3>;
 271                 };
 272
 273                 gpio: gpio@55000000 {
 274                         compatible = "socionext,uniphier-gpio";
 275                         reg = <0x55000000 0x200>;
 276                         interrupt-parent = <&aidet>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         gpio-ranges = <&pinctrl 0 0 0>,
 282                                       <&pinctrl 104 0 0>,
 283                                       <&pinctrl 168 0 0>;
 284                         gpio-ranges-group-names = "gpio_range0",
 285                                                   "gpio_range1",
 286                                                   "gpio_range2";
 287                         ngpios = <286>;
 288                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 289                                                      <21 217 3>;
 290                 };
 291
 292                 i2c0: i2c@58780000 {
 293                         compatible = "socionext,uniphier-fi2c";
 294                         status = "disabled";
 295                         reg = <0x58780000 0x80>;
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 299                         pinctrl-names = "default";
 300                         pinctrl-0 = <&pinctrl_i2c0>;
 301                         clocks = <&peri_clk 4>;
 302                         resets = <&peri_rst 4>;
 303                         clock-frequency = <100000>;
 304                 };
 305
 306                 i2c1: i2c@58781000 {
 307                         compatible = "socionext,uniphier-fi2c";
 308                         status = "disabled";
 309                         reg = <0x58781000 0x80>;
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 313                         pinctrl-names = "default";
 314                         pinctrl-0 = <&pinctrl_i2c1>;
 315                         clocks = <&peri_clk 5>;
 316                         resets = <&peri_rst 5>;
 317                         clock-frequency = <100000>;
 318                 };
 319
 320                 i2c2: i2c@58782000 {
 321                         compatible = "socionext,uniphier-fi2c";
 322                         status = "disabled";
 323                         reg = <0x58782000 0x80>;
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 327                         pinctrl-names = "default";
 328                         pinctrl-0 = <&pinctrl_i2c2>;
 329                         clocks = <&peri_clk 6>;
 330                         resets = <&peri_rst 6>;
 331                         clock-frequency = <100000>;
 332                 };
 333
 334                 i2c3: i2c@58783000 {
 335                         compatible = "socionext,uniphier-fi2c";
 336                         status = "disabled";
 337                         reg = <0x58783000 0x80>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 341                         pinctrl-names = "default";
 342                         pinctrl-0 = <&pinctrl_i2c3>;
 343                         clocks = <&peri_clk 7>;
 344                         resets = <&peri_rst 7>;
 345                         clock-frequency = <100000>;
 346                 };
 347
 348                 /* chip-internal connection for HDMI */
 349                 i2c6: i2c@58786000 {
 350                         compatible = "socionext,uniphier-fi2c";
 351                         reg = <0x58786000 0x80>;
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&peri_clk 10>;
 356                         resets = <&peri_rst 10>;
 357                         clock-frequency = <400000>;
 358                 };
 359
 360                 system_bus: system-bus@58c00000 {
 361                         compatible = "socionext,uniphier-system-bus";
 362                         status = "disabled";
 363                         reg = <0x58c00000 0x400>;
 364                         #address-cells = <2>;
 365                         #size-cells = <1>;
 366                         pinctrl-names = "default";
 367                         pinctrl-0 = <&pinctrl_system_bus>;
 368                 };
 369
 370                 smpctrl@59801000 {
 371                         compatible = "socionext,uniphier-smpctrl";
 372                         reg = <0x59801000 0x400>;
 373                 };
 374
 375                 sdctrl: syscon@59810000 {
 376                         compatible = "socionext,uniphier-pxs3-sdctrl",
 377                                      "simple-mfd", "syscon";
 378                         reg = <0x59810000 0x400>;
 379
 380                         sd_clk: clock-controller {
 381                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 382                                 #clock-cells = <1>;
 383                         };
 384
 385                         sd_rst: reset-controller {
 386                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 387                                 #reset-cells = <1>;
 388                         };
 389                 };
 390
 391                 syscon@59820000 {
 392                         compatible = "socionext,uniphier-pxs3-perictrl",
 393                                      "simple-mfd", "syscon";
 394                         reg = <0x59820000 0x200>;
 395
 396                         peri_clk: clock-controller {
 397                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 398                                 #clock-cells = <1>;
 399                         };
 400
 401                         peri_rst: reset-controller {
 402                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 403                                 #reset-cells = <1>;
 404                         };
 405                 };
 406
 407                 emmc: mmc@5a000000 {
 408                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 409                         reg = <0x5a000000 0x400>;
 410                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 411                         pinctrl-names = "default";
 412                         pinctrl-0 = <&pinctrl_emmc>;
 413                         clocks = <&sys_clk 4>;
 414                         resets = <&sys_rst 4>;
 415                         bus-width = <8>;
 416                         mmc-ddr-1_8v;
 417                         mmc-hs200-1_8v;
 418                         mmc-pwrseq = <&emmc_pwrseq>;
 419                         cdns,phy-input-delay-legacy = <9>;
 420                         cdns,phy-input-delay-mmc-highspeed = <2>;
 421                         cdns,phy-input-delay-mmc-ddr = <3>;
 422                         cdns,phy-dll-delay-sdclk = <21>;
 423                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 424                 };
 425
 426                 sd: mmc@5a400000 {
 427                         compatible = "socionext,uniphier-sd-v3.1.1";
 428                         status = "disabled";
 429                         reg = <0x5a400000 0x800>;
 430                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 431                         pinctrl-names = "default", "uhs";
 432                         pinctrl-0 = <&pinctrl_sd>;
 433                         pinctrl-1 = <&pinctrl_sd_uhs>;
 434                         clocks = <&sd_clk 0>;
 435                         reset-names = "host";
 436                         resets = <&sd_rst 0>;
 437                         bus-width = <4>;
 438                         cap-sd-highspeed;
 439                         sd-uhs-sdr12;
 440                         sd-uhs-sdr25;
 441                         sd-uhs-sdr50;
 442                         socionext,syscon-uhs-mode = <&sdctrl 0>;
 443                 };
 444
 445                 soc_glue: syscon@5f800000 {
 446                         compatible = "socionext,uniphier-pxs3-soc-glue",
 447                                      "simple-mfd", "syscon";
 448                         reg = <0x5f800000 0x2000>;
 449
 450                         pinctrl: pinctrl {
 451                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 452                         };
 453                 };
 454
 455                 syscon@5f900000 {
 456                         compatible = "socionext,uniphier-pxs3-soc-glue-debug",
 457                                      "simple-mfd", "syscon";
 458                         reg = <0x5f900000 0x2000>;
 459                         #address-cells = <1>;
 460                         #size-cells = <1>;
 461                         ranges = <0 0x5f900000 0x2000>;
 462
 463                         efuse@100 {
 464                                 compatible = "socionext,uniphier-efuse";
 465                                 reg = <0x100 0x28>;
 466                         };
 467
 468                         efuse@200 {
 469                                 compatible = "socionext,uniphier-efuse";
 470                                 reg = <0x200 0x68>;
 471                                 #address-cells = <1>;
 472                                 #size-cells = <1>;
 473
 474                                 /* USB cells */
 475                                 usb_rterm0: trim@54,4 {
 476                                         reg = <0x54 1>;
 477                                         bits = <4 2>;
 478                                 };
 479                                 usb_rterm1: trim@55,4 {
 480                                         reg = <0x55 1>;
 481                                         bits = <4 2>;
 482                                 };
 483                                 usb_rterm2: trim@58,4 {
 484                                         reg = <0x58 1>;
 485                                         bits = <4 2>;
 486                                 };
 487                                 usb_rterm3: trim@59,4 {
 488                                         reg = <0x59 1>;
 489                                         bits = <4 2>;
 490                                 };
 491                                 usb_sel_t0: trim@54,0 {
 492                                         reg = <0x54 1>;
 493                                         bits = <0 4>;
 494                                 };
 495                                 usb_sel_t1: trim@55,0 {
 496                                         reg = <0x55 1>;
 497                                         bits = <0 4>;
 498                                 };
 499                                 usb_sel_t2: trim@58,0 {
 500                                         reg = <0x58 1>;
 501                                         bits = <0 4>;
 502                                 };
 503                                 usb_sel_t3: trim@59,0 {
 504                                         reg = <0x59 1>;
 505                                         bits = <0 4>;
 506                                 };
 507                                 usb_hs_i0: trim@56,0 {
 508                                         reg = <0x56 1>;
 509                                         bits = <0 4>;
 510                                 };
 511                                 usb_hs_i2: trim@5a,0 {
 512                                         reg = <0x5a 1>;
 513                                         bits = <0 4>;
 514                                 };
 515                         };
 516                 };
 517
 518                 xdmac: dma-controller@5fc10000 {
 519                         compatible = "socionext,uniphier-xdmac";
 520                         reg = <0x5fc10000 0x5300>;
 521                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 522                         dma-channels = <16>;
 523                         #dma-cells = <2>;
 524                 };
 525
 526                 aidet: interrupt-controller@5fc20000 {
 527                         compatible = "socionext,uniphier-pxs3-aidet";
 528                         reg = <0x5fc20000 0x200>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 gic: interrupt-controller@5fe00000 {
 534                         compatible = "arm,gic-v3";
 535                         reg = <0x5fe00000 0x10000>,     /* GICD */
 536                               <0x5fe80000 0x80000>;     /* GICR */
 537                         interrupt-controller;
 538                         #interrupt-cells = <3>;
 539                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 540                 };
 541
 542                 syscon@61840000 {
 543                         compatible = "socionext,uniphier-pxs3-sysctrl",
 544                                      "simple-mfd", "syscon";
 545                         reg = <0x61840000 0x10000>;
 546
 547                         sys_clk: clock-controller {
 548                                 compatible = "socionext,uniphier-pxs3-clock";
 549                                 #clock-cells = <1>;
 550                         };
 551
 552                         sys_rst: reset-controller {
 553                                 compatible = "socionext,uniphier-pxs3-reset";
 554                                 #reset-cells = <1>;
 555                         };
 556
 557                         watchdog {
 558                                 compatible = "socionext,uniphier-wdt";
 559                         };
 560
 561                         pvtctl: thermal-sensor {
 562                                 compatible = "socionext,uniphier-pxs3-thermal";
 563                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 564                                 #thermal-sensor-cells = <0>;
 565                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 566                         };
 567                 };
 568
 569                 eth0: ethernet@65000000 {
 570                         compatible = "socionext,uniphier-pxs3-ave4";
 571                         status = "disabled";
 572                         reg = <0x65000000 0x8500>;
 573                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 574                         pinctrl-names = "default";
 575                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 576                         clock-names = "ether";
 577                         clocks = <&sys_clk 6>;
 578                         reset-names = "ether";
 579                         resets = <&sys_rst 6>;
 580                         phy-mode = "rgmii-id";
 581                         local-mac-address = [00 00 00 00 00 00];
 582                         socionext,syscon-phy-mode = <&soc_glue 0>;
 583
 584                         mdio0: mdio {
 585                                 #address-cells = <1>;
 586                                 #size-cells = <0>;
 587                         };
 588                 };
 589
 590                 eth1: ethernet@65200000 {
 591                         compatible = "socionext,uniphier-pxs3-ave4";
 592                         status = "disabled";
 593                         reg = <0x65200000 0x8500>;
 594                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 595                         pinctrl-names = "default";
 596                         pinctrl-0 = <&pinctrl_ether1_rgmii>;
 597                         clock-names = "ether";
 598                         clocks = <&sys_clk 7>;
 599                         reset-names = "ether";
 600                         resets = <&sys_rst 7>;
 601                         phy-mode = "rgmii-id";
 602                         local-mac-address = [00 00 00 00 00 00];
 603                         socionext,syscon-phy-mode = <&soc_glue 1>;
 604
 605                         mdio1: mdio {
 606                                 #address-cells = <1>;
 607                                 #size-cells = <0>;
 608                         };
 609                 };
 610
 611                 ahci0: sata@65600000 {
 612                         compatible = "socionext,uniphier-pxs3-ahci",
 613                                      "generic-ahci";
 614                         status = "disabled";
 615                         reg = <0x65600000 0x10000>;
 616                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&sys_clk 28>;
 618                         resets = <&sys_rst 28>, <&ahci0_rst 0>;
 619                         ports-implemented = <1>;
 620                         phys = <&ahci0_phy>;
 621                 };
 622
 623                 sata-controller@65700000 {
 624                         compatible = "socionext,uniphier-pxs3-ahci-glue",
 625                                      "simple-mfd";
 626                         reg = <0x65700000 0x100>;
 627                         #address-cells = <1>;
 628                         #size-cells = <1>;
 629                         ranges = <0 0x65700000 0x100>;
 630
 631                         ahci0_rst: reset-controller@0 {
 632                                 compatible = "socionext,uniphier-pxs3-ahci-reset";
 633                                 reg = <0x0 0x4>;
 634                                 clock-names = "link";
 635                                 clocks = <&sys_clk 28>;
 636                                 reset-names = "link";
 637                                 resets = <&sys_rst 28>;
 638                                 #reset-cells = <1>;
 639                         };
 640
 641                         ahci0_phy: sata-phy@10 {
 642                                 compatible = "socionext,uniphier-pxs3-ahci-phy";
 643                                 reg = <0x10 0x10>;
 644                                 clock-names = "link", "phy";
 645                                 clocks = <&sys_clk 28>, <&sys_clk 30>;
 646                                 reset-names = "link", "phy";
 647                                 resets = <&sys_rst 28>, <&sys_rst 30>;
 648                                 #phy-cells = <0>;
 649                         };
 650                 };
 651
 652                 ahci1: sata@65800000 {
 653                         compatible = "socionext,uniphier-pxs3-ahci",
 654                                      "generic-ahci";
 655                         status = "disabled";
 656                         reg = <0x65800000 0x10000>;
 657                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 658                         clocks = <&sys_clk 29>;
 659                         resets = <&sys_rst 29>, <&ahci1_rst 0>;
 660                         ports-implemented = <1>;
 661                         phys = <&ahci1_phy>;
 662                 };
 663
 664                 sata-controller@65900000 {
 665                         compatible = "socionext,uniphier-pxs3-ahci-glue",
 666                                      "simple-mfd";
 667                         reg = <0x65900000 0x100>;
 668                         #address-cells = <1>;
 669                         #size-cells = <1>;
 670                         ranges = <0 0x65900000 0x100>;
 671
 672                         ahci1_rst: reset-controller@0 {
 673                                 compatible = "socionext,uniphier-pxs3-ahci-reset";
 674                                 reg = <0x0 0x4>;
 675                                 clock-names = "link";
 676                                 clocks = <&sys_clk 29>;
 677                                 reset-names = "link";
 678                                 resets = <&sys_rst 29>;
 679                                 #reset-cells = <1>;
 680                         };
 681
 682                         ahci1_phy: sata-phy@10 {
 683                                 compatible = "socionext,uniphier-pxs3-ahci-phy";
 684                                 reg = <0x10 0x10>;
 685                                 clock-names = "link", "phy";
 686                                 clocks = <&sys_clk 29>, <&sys_clk 30>;
 687                                 reset-names = "link", "phy";
 688                                 resets = <&sys_rst 29>, <&sys_rst 30>;
 689                                 #phy-cells = <0>;
 690                         };
 691                 };
 692
 693                 usb0: usb@65a00000 {
 694                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 695                         status = "disabled";
 696                         reg = <0x65a00000 0xcd00>;
 697                         interrupt-names = "dwc_usb3";
 698                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 699                         pinctrl-names = "default";
 700                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 701                         clock-names = "ref", "bus_early", "suspend";
 702                         clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
 703                         resets = <&usb0_rst 15>;
 704                         phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
 705                                <&usb0_ssphy0>, <&usb0_ssphy1>;
 706                         dr_mode = "host";
 707                 };
 708
 709                 usb-controller@65b00000 {
 710                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 711                                      "simple-mfd";
 712                         reg = <0x65b00000 0x400>;
 713                         #address-cells = <1>;
 714                         #size-cells = <1>;
 715                         ranges = <0 0x65b00000 0x400>;
 716
 717                         usb0_rst: reset-controller@0 {
 718                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 719                                 reg = <0x0 0x4>;
 720                                 #reset-cells = <1>;
 721                                 clock-names = "link";
 722                                 clocks = <&sys_clk 12>;
 723                                 reset-names = "link";
 724                                 resets = <&sys_rst 12>;
 725                         };
 726
 727                         usb0_vbus0: regulator@100 {
 728                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 729                                 reg = <0x100 0x10>;
 730                                 clock-names = "link";
 731                                 clocks = <&sys_clk 12>;
 732                                 reset-names = "link";
 733                                 resets = <&sys_rst 12>;
 734                         };
 735
 736                         usb0_vbus1: regulator@110 {
 737                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 738                                 reg = <0x110 0x10>;
 739                                 clock-names = "link";
 740                                 clocks = <&sys_clk 12>;
 741                                 reset-names = "link";
 742                                 resets = <&sys_rst 12>;
 743                         };
 744
 745                         usb0_hsphy0: phy@200 {
 746                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 747                                 reg = <0x200 0x10>;
 748                                 #phy-cells = <0>;
 749                                 clock-names = "link", "phy";
 750                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 751                                 reset-names = "link", "phy";
 752                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 753                                 vbus-supply = <&usb0_vbus0>;
 754                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 755                                 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
 756                                               <&usb_hs_i0>;
 757                         };
 758
 759                         usb0_hsphy1: phy@210 {
 760                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 761                                 reg = <0x210 0x10>;
 762                                 #phy-cells = <0>;
 763                                 clock-names = "link", "phy";
 764                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 765                                 reset-names = "link", "phy";
 766                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 767                                 vbus-supply = <&usb0_vbus1>;
 768                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 769                                 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
 770                                               <&usb_hs_i0>;
 771                         };
 772
 773                         usb0_ssphy0: phy@300 {
 774                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 775                                 reg = <0x300 0x10>;
 776                                 #phy-cells = <0>;
 777                                 clock-names = "link", "phy";
 778                                 clocks = <&sys_clk 12>, <&sys_clk 17>;
 779                                 reset-names = "link", "phy";
 780                                 resets = <&sys_rst 12>, <&sys_rst 17>;
 781                                 vbus-supply = <&usb0_vbus0>;
 782                         };
 783
 784                         usb0_ssphy1: phy@310 {
 785                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 786                                 reg = <0x310 0x10>;
 787                                 #phy-cells = <0>;
 788                                 clock-names = "link", "phy";
 789                                 clocks = <&sys_clk 12>, <&sys_clk 18>;
 790                                 reset-names = "link", "phy";
 791                                 resets = <&sys_rst 12>, <&sys_rst 18>;
 792                                 vbus-supply = <&usb0_vbus1>;
 793                         };
 794                 };
 795
 796                 usb1: usb@65c00000 {
 797                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 798                         status = "disabled";
 799                         reg = <0x65c00000 0xcd00>;
 800                         interrupt-names = "dwc_usb3";
 801                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 802                         pinctrl-names = "default";
 803                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 804                         clock-names = "ref", "bus_early", "suspend";
 805                         clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
 806                         resets = <&usb1_rst 15>;
 807                         phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
 808                                <&usb1_ssphy0>;
 809                         dr_mode = "host";
 810                 };
 811
 812                 usb-controller@65d00000 {
 813                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 814                                      "simple-mfd";
 815                         reg = <0x65d00000 0x400>;
 816                         #address-cells = <1>;
 817                         #size-cells = <1>;
 818                         ranges = <0 0x65d00000 0x400>;
 819
 820                         usb1_rst: reset-controller@0 {
 821                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 822                                 reg = <0x0 0x4>;
 823                                 #reset-cells = <1>;
 824                                 clock-names = "link";
 825                                 clocks = <&sys_clk 13>;
 826                                 reset-names = "link";
 827                                 resets = <&sys_rst 13>;
 828                         };
 829
 830                         usb1_vbus0: regulator@100 {
 831                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 832                                 reg = <0x100 0x10>;
 833                                 clock-names = "link";
 834                                 clocks = <&sys_clk 13>;
 835                                 reset-names = "link";
 836                                 resets = <&sys_rst 13>;
 837                         };
 838
 839                         usb1_vbus1: regulator@110 {
 840                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 841                                 reg = <0x110 0x10>;
 842                                 clock-names = "link";
 843                                 clocks = <&sys_clk 13>;
 844                                 reset-names = "link";
 845                                 resets = <&sys_rst 13>;
 846                         };
 847
 848                         usb1_hsphy0: phy@200 {
 849                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 850                                 reg = <0x200 0x10>;
 851                                 #phy-cells = <0>;
 852                                 clock-names = "link", "phy", "phy-ext";
 853                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 854                                          <&sys_clk 14>;
 855                                 reset-names = "link", "phy";
 856                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 857                                 vbus-supply = <&usb1_vbus0>;
 858                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 859                                 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
 860                                               <&usb_hs_i2>;
 861                         };
 862
 863                         usb1_hsphy1: phy@210 {
 864                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 865                                 reg = <0x210 0x10>;
 866                                 #phy-cells = <0>;
 867                                 clock-names = "link", "phy", "phy-ext";
 868                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 869                                          <&sys_clk 14>;
 870                                 reset-names = "link", "phy";
 871                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 872                                 vbus-supply = <&usb1_vbus1>;
 873                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 874                                 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
 875                                               <&usb_hs_i2>;
 876                         };
 877
 878                         usb1_ssphy0: phy@300 {
 879                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 880                                 reg = <0x300 0x10>;
 881                                 #phy-cells = <0>;
 882                                 clock-names = "link", "phy", "phy-ext";
 883                                 clocks = <&sys_clk 13>, <&sys_clk 21>,
 884                                          <&sys_clk 14>;
 885                                 reset-names = "link", "phy";
 886                                 resets = <&sys_rst 13>, <&sys_rst 21>;
 887                                 vbus-supply = <&usb1_vbus0>;
 888                         };
 889                 };
 890
 891                 pcie: pcie@66000000 {
 892                         compatible = "socionext,uniphier-pcie";
 893                         status = "disabled";
 894                         reg-names = "dbi", "link", "config";
 895                         reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
 896                               <0x2fff0000 0x10000>;
 897                         #address-cells = <3>;
 898                         #size-cells = <2>;
 899                         clocks = <&sys_clk 24>;
 900                         resets = <&sys_rst 24>;
 901                         num-lanes = <1>;
 902                         num-viewport = <1>;
 903                         bus-range = <0x0 0xff>;
 904                         device_type = "pci";
 905                         ranges =
 906                         /* downstream I/O */
 907                                 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
 908                         /* non-prefetchable memory */
 909                                 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
 910                         #interrupt-cells = <1>;
 911                         interrupt-names = "dma", "msi";
 912                         interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 914                         interrupt-map-mask = <0 0 0 7>;
 915                         interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
 916                                         <0 0 0 2 &pcie_intc 1>, /* INTB */
 917                                         <0 0 0 3 &pcie_intc 2>, /* INTC */
 918                                         <0 0 0 4 &pcie_intc 3>; /* INTD */
 919                         phy-names = "pcie-phy";
 920                         phys = <&pcie_phy>;
 921
 922                         pcie_intc: legacy-interrupt-controller {
 923                                 interrupt-controller;
 924                                 #interrupt-cells = <1>;
 925                                 interrupt-parent = <&gic>;
 926                                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 927                         };
 928                 };
 929
 930                 pcie_phy: phy@66038000 {
 931                         compatible = "socionext,uniphier-pxs3-pcie-phy";
 932                         reg = <0x66038000 0x4000>;
 933                         #phy-cells = <0>;
 934                         clock-names = "link";
 935                         clocks = <&sys_clk 24>;
 936                         reset-names = "link";
 937                         resets = <&sys_rst 24>;
 938                         socionext,syscon = <&soc_glue>;
 939                 };
 940
 941                 nand: nand-controller@68000000 {
 942                         compatible = "socionext,uniphier-denali-nand-v5b";
 943                         status = "disabled";
 944                         reg-names = "nand_data", "denali_reg";
 945                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 946                         #address-cells = <1>;
 947                         #size-cells = <0>;
 948                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 949                         pinctrl-names = "default";
 950                         pinctrl-0 = <&pinctrl_nand>;
 951                         clock-names = "nand", "nand_x", "ecc";
 952                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 953                         reset-names = "nand", "reg";
 954                         resets = <&sys_rst 2>, <&sys_rst 2>;
 955                 };
 956         };
 957 };
 958
 959 #include "uniphier-pinctrl.dtsi"