2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld20";
16 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a72", "arm,armv8";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a72", "arm,armv8";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 operating-points-v2 = <&cluster0_opp>;
63 compatible = "arm,cortex-a53", "arm,armv8";
65 clocks = <&sys_clk 33>;
66 enable-method = "psci";
67 operating-points-v2 = <&cluster1_opp>;
72 compatible = "arm,cortex-a53", "arm,armv8";
74 clocks = <&sys_clk 33>;
75 enable-method = "psci";
76 operating-points-v2 = <&cluster1_opp>;
81 cluster0_opp: opp_table0 {
82 compatible = "operating-points-v2";
86 opp-hz = /bits/ 64 <250000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <275000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <500000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <550000000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <666667000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <733334000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <1000000000>;
111 clock-latency-ns = <300>;
114 opp-hz = /bits/ 64 <1100000000>;
115 clock-latency-ns = <300>;
119 cluster1_opp: opp_table1 {
120 compatible = "operating-points-v2";
124 opp-hz = /bits/ 64 <250000000>;
125 clock-latency-ns = <300>;
128 opp-hz = /bits/ 64 <275000000>;
129 clock-latency-ns = <300>;
132 opp-hz = /bits/ 64 <500000000>;
133 clock-latency-ns = <300>;
136 opp-hz = /bits/ 64 <550000000>;
137 clock-latency-ns = <300>;
140 opp-hz = /bits/ 64 <666667000>;
141 clock-latency-ns = <300>;
144 opp-hz = /bits/ 64 <733334000>;
145 clock-latency-ns = <300>;
148 opp-hz = /bits/ 64 <1000000000>;
149 clock-latency-ns = <300>;
152 opp-hz = /bits/ 64 <1100000000>;
153 clock-latency-ns = <300>;
158 compatible = "arm,psci-1.0";
164 compatible = "fixed-clock";
166 clock-frequency = <25000000>;
171 compatible = "arm,armv8-timer";
172 interrupts = <1 13 4>,
179 compatible = "simple-bus";
180 #address-cells = <1>;
182 ranges = <0 0 0 0xffffffff>;
184 serial0: serial@54006800 {
185 compatible = "socionext,uniphier-uart";
187 reg = <0x54006800 0x40>;
188 interrupts = <0 33 4>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart0>;
191 clocks = <&peri_clk 0>;
194 serial1: serial@54006900 {
195 compatible = "socionext,uniphier-uart";
197 reg = <0x54006900 0x40>;
198 interrupts = <0 35 4>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_uart1>;
201 clocks = <&peri_clk 1>;
204 serial2: serial@54006a00 {
205 compatible = "socionext,uniphier-uart";
207 reg = <0x54006a00 0x40>;
208 interrupts = <0 37 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart2>;
211 clocks = <&peri_clk 2>;
214 serial3: serial@54006b00 {
215 compatible = "socionext,uniphier-uart";
217 reg = <0x54006b00 0x40>;
218 interrupts = <0 177 4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart3>;
221 clocks = <&peri_clk 3>;
225 compatible = "socionext,uniphier-ld20-adamv",
226 "simple-mfd", "syscon";
227 reg = <0x57920000 0x1000>;
230 compatible = "socionext,uniphier-ld20-adamv-reset";
236 compatible = "socionext,uniphier-fi2c";
238 reg = <0x58780000 0x80>;
239 #address-cells = <1>;
241 interrupts = <0 41 4>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c0>;
244 clocks = <&peri_clk 4>;
245 clock-frequency = <100000>;
249 compatible = "socionext,uniphier-fi2c";
251 reg = <0x58781000 0x80>;
252 #address-cells = <1>;
254 interrupts = <0 42 4>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_i2c1>;
257 clocks = <&peri_clk 5>;
258 clock-frequency = <100000>;
262 compatible = "socionext,uniphier-fi2c";
263 reg = <0x58782000 0x80>;
264 #address-cells = <1>;
266 interrupts = <0 43 4>;
267 clocks = <&peri_clk 6>;
268 clock-frequency = <400000>;
272 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58783000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 44 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c3>;
280 clocks = <&peri_clk 7>;
281 clock-frequency = <100000>;
285 compatible = "socionext,uniphier-fi2c";
287 reg = <0x58784000 0x80>;
288 #address-cells = <1>;
290 interrupts = <0 45 4>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_i2c4>;
293 clocks = <&peri_clk 8>;
294 clock-frequency = <100000>;
298 compatible = "socionext,uniphier-fi2c";
299 reg = <0x58785000 0x80>;
300 #address-cells = <1>;
302 interrupts = <0 25 4>;
303 clocks = <&peri_clk 9>;
304 clock-frequency = <400000>;
307 system_bus: system-bus@58c00000 {
308 compatible = "socionext,uniphier-system-bus";
310 reg = <0x58c00000 0x400>;
311 #address-cells = <2>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_system_bus>;
318 compatible = "socionext,uniphier-smpctrl";
319 reg = <0x59801000 0x400>;
323 compatible = "socionext,uniphier-ld20-sdctrl",
324 "simple-mfd", "syscon";
325 reg = <0x59810000 0x400>;
328 compatible = "socionext,uniphier-ld20-sd-clock";
333 compatible = "socionext,uniphier-ld20-sd-reset";
339 compatible = "socionext,uniphier-ld20-perictrl",
340 "simple-mfd", "syscon";
341 reg = <0x59820000 0x200>;
344 compatible = "socionext,uniphier-ld20-peri-clock";
349 compatible = "socionext,uniphier-ld20-peri-reset";
354 emmc: sdhc@5a000000 {
355 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
356 reg = <0x5a000000 0x400>;
357 interrupts = <0 78 4>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_emmc>;
360 clocks = <&sys_clk 4>;
364 cdns,phy-input-delay-legacy = <4>;
365 cdns,phy-input-delay-mmc-highspeed = <2>;
366 cdns,phy-input-delay-mmc-ddr = <3>;
367 cdns,phy-dll-delay-sdclk = <21>;
368 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
372 compatible = "socionext,uniphier-ld20-soc-glue",
373 "simple-mfd", "syscon";
374 reg = <0x5f800000 0x2000>;
377 compatible = "socionext,uniphier-ld20-pinctrl";
381 aidet: aidet@5fc20000 {
382 compatible = "socionext,uniphier-ld20-aidet";
383 reg = <0x5fc20000 0x200>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
388 gic: interrupt-controller@5fe00000 {
389 compatible = "arm,gic-v3";
390 reg = <0x5fe00000 0x10000>, /* GICD */
391 <0x5fe80000 0x80000>; /* GICR */
392 interrupt-controller;
393 #interrupt-cells = <3>;
394 interrupts = <1 9 4>;
398 compatible = "socionext,uniphier-ld20-sysctrl",
399 "simple-mfd", "syscon";
400 reg = <0x61840000 0x10000>;
403 compatible = "socionext,uniphier-ld20-clock";
408 compatible = "socionext,uniphier-ld20-reset";
413 compatible = "socionext,uniphier-wdt";
417 nand: nand@68000000 {
418 compatible = "socionext,uniphier-denali-nand-v5b";
420 reg-names = "nand_data", "denali_reg";
421 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
422 interrupts = <0 65 4>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_nand>;
425 clocks = <&sys_clk 2>;
430 #include "uniphier-pinctrl.dtsi"