1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
17 interrupt-parent = <&gic>;
45 compatible = "arm,cortex-a72";
47 clocks = <&sys_clk 32>;
48 enable-method = "psci";
49 next-level-cache = <&a72_l2>;
50 operating-points-v2 = <&cluster0_opp>;
56 compatible = "arm,cortex-a72";
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 next-level-cache = <&a72_l2>;
61 operating-points-v2 = <&cluster0_opp>;
67 compatible = "arm,cortex-a53";
69 clocks = <&sys_clk 33>;
70 enable-method = "psci";
71 next-level-cache = <&a53_l2>;
72 operating-points-v2 = <&cluster1_opp>;
78 compatible = "arm,cortex-a53";
80 clocks = <&sys_clk 33>;
81 enable-method = "psci";
82 next-level-cache = <&a53_l2>;
83 operating-points-v2 = <&cluster1_opp>;
96 cluster0_opp: opp-table-0 {
97 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <250000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <275000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <500000000>;
110 clock-latency-ns = <300>;
113 opp-hz = /bits/ 64 <550000000>;
114 clock-latency-ns = <300>;
117 opp-hz = /bits/ 64 <666667000>;
118 clock-latency-ns = <300>;
121 opp-hz = /bits/ 64 <733334000>;
122 clock-latency-ns = <300>;
125 opp-hz = /bits/ 64 <1000000000>;
126 clock-latency-ns = <300>;
129 opp-hz = /bits/ 64 <1100000000>;
130 clock-latency-ns = <300>;
134 cluster1_opp: opp-table-1 {
135 compatible = "operating-points-v2";
139 opp-hz = /bits/ 64 <250000000>;
140 clock-latency-ns = <300>;
143 opp-hz = /bits/ 64 <275000000>;
144 clock-latency-ns = <300>;
147 opp-hz = /bits/ 64 <500000000>;
148 clock-latency-ns = <300>;
151 opp-hz = /bits/ 64 <550000000>;
152 clock-latency-ns = <300>;
155 opp-hz = /bits/ 64 <666667000>;
156 clock-latency-ns = <300>;
159 opp-hz = /bits/ 64 <733334000>;
160 clock-latency-ns = <300>;
163 opp-hz = /bits/ 64 <1000000000>;
164 clock-latency-ns = <300>;
167 opp-hz = /bits/ 64 <1100000000>;
168 clock-latency-ns = <300>;
173 compatible = "arm,psci-1.0";
179 compatible = "fixed-clock";
181 clock-frequency = <25000000>;
185 emmc_pwrseq: emmc-pwrseq {
186 compatible = "mmc-pwrseq-emmc";
187 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
191 compatible = "arm,armv8-timer";
192 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
200 polling-delay-passive = <250>; /* 250ms */
201 polling-delay = <1000>; /* 1000ms */
202 thermal-sensors = <&pvtctl>;
206 temperature = <110000>; /* 110C */
210 cpu_alert: cpu-alert {
211 temperature = <100000>; /* 100C */
220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
221 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
222 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
223 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
230 #address-cells = <2>;
234 secure-memory@81000000 {
235 reg = <0x0 0x81000000 0x0 0x01000000>;
241 compatible = "simple-bus";
242 #address-cells = <1>;
244 ranges = <0 0 0 0xffffffff>;
247 compatible = "socionext,uniphier-scssi";
249 reg = <0x54006000 0x100>;
250 #address-cells = <1>;
252 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_spi0>;
255 clocks = <&peri_clk 11>;
256 resets = <&peri_rst 11>;
260 compatible = "socionext,uniphier-scssi";
262 reg = <0x54006100 0x100>;
263 #address-cells = <1>;
265 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_spi1>;
268 clocks = <&peri_clk 12>;
269 resets = <&peri_rst 12>;
273 compatible = "socionext,uniphier-scssi";
275 reg = <0x54006200 0x100>;
276 #address-cells = <1>;
278 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_spi2>;
281 clocks = <&peri_clk 13>;
282 resets = <&peri_rst 13>;
286 compatible = "socionext,uniphier-scssi";
288 reg = <0x54006300 0x100>;
289 #address-cells = <1>;
291 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_spi3>;
294 clocks = <&peri_clk 14>;
295 resets = <&peri_rst 14>;
298 serial0: serial@54006800 {
299 compatible = "socionext,uniphier-uart";
301 reg = <0x54006800 0x40>;
302 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_uart0>;
305 clocks = <&peri_clk 0>;
306 resets = <&peri_rst 0>;
309 serial1: serial@54006900 {
310 compatible = "socionext,uniphier-uart";
312 reg = <0x54006900 0x40>;
313 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart1>;
316 clocks = <&peri_clk 1>;
317 resets = <&peri_rst 1>;
320 serial2: serial@54006a00 {
321 compatible = "socionext,uniphier-uart";
323 reg = <0x54006a00 0x40>;
324 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_uart2>;
327 clocks = <&peri_clk 2>;
328 resets = <&peri_rst 2>;
331 serial3: serial@54006b00 {
332 compatible = "socionext,uniphier-uart";
334 reg = <0x54006b00 0x40>;
335 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_uart3>;
338 clocks = <&peri_clk 3>;
339 resets = <&peri_rst 3>;
342 gpio: gpio@55000000 {
343 compatible = "socionext,uniphier-gpio";
344 reg = <0x55000000 0x200>;
345 interrupt-parent = <&aidet>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
350 gpio-ranges = <&pinctrl 0 0 0>,
353 gpio-ranges-group-names = "gpio_range0",
357 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
362 compatible = "socionext,uniphier-ld20-aio";
363 reg = <0x56000000 0x80000>;
364 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_aout1>,
369 clocks = <&sys_clk 40>;
371 resets = <&sys_rst 40>;
372 #sound-dai-cells = <1>;
373 socionext,syscon = <&soc_glue>;
381 i2s_pcmin2: endpoint {
388 remote-endpoint = <&evea_line>;
393 i2s_hpcmout1: endpoint {
400 remote-endpoint = <&evea_hp>;
404 spdif_port0: port@5 {
405 spdif_hiecout1: endpoint {
410 i2s_epcmout2: endpoint {
415 i2s_epcmout3: endpoint {
419 comp_spdif_port0: port@8 {
420 comp_spdif_hiecout1: endpoint {
426 compatible = "socionext,uniphier-evea";
427 reg = <0x57900000 0x1000>;
428 clock-names = "evea", "exiv";
429 clocks = <&sys_clk 41>, <&sys_clk 42>;
430 reset-names = "evea", "exiv", "adamv";
431 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
432 #sound-dai-cells = <1>;
435 evea_line: endpoint {
436 remote-endpoint = <&i2s_line>;
442 remote-endpoint = <&i2s_hp>;
448 compatible = "socionext,uniphier-ld20-adamv",
449 "simple-mfd", "syscon";
450 reg = <0x57920000 0x1000>;
453 compatible = "socionext,uniphier-ld20-adamv-reset";
459 compatible = "socionext,uniphier-fi2c";
461 reg = <0x58780000 0x80>;
462 #address-cells = <1>;
464 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c0>;
467 clocks = <&peri_clk 4>;
468 resets = <&peri_rst 4>;
469 clock-frequency = <100000>;
473 compatible = "socionext,uniphier-fi2c";
475 reg = <0x58781000 0x80>;
476 #address-cells = <1>;
478 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_i2c1>;
481 clocks = <&peri_clk 5>;
482 resets = <&peri_rst 5>;
483 clock-frequency = <100000>;
487 compatible = "socionext,uniphier-fi2c";
488 reg = <0x58782000 0x80>;
489 #address-cells = <1>;
491 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&peri_clk 6>;
493 resets = <&peri_rst 6>;
494 clock-frequency = <400000>;
498 compatible = "socionext,uniphier-fi2c";
500 reg = <0x58783000 0x80>;
501 #address-cells = <1>;
503 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_i2c3>;
506 clocks = <&peri_clk 7>;
507 resets = <&peri_rst 7>;
508 clock-frequency = <100000>;
512 compatible = "socionext,uniphier-fi2c";
514 reg = <0x58784000 0x80>;
515 #address-cells = <1>;
517 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_i2c4>;
520 clocks = <&peri_clk 8>;
521 resets = <&peri_rst 8>;
522 clock-frequency = <100000>;
526 compatible = "socionext,uniphier-fi2c";
527 reg = <0x58785000 0x80>;
528 #address-cells = <1>;
530 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&peri_clk 9>;
532 resets = <&peri_rst 9>;
533 clock-frequency = <400000>;
536 system_bus: system-bus@58c00000 {
537 compatible = "socionext,uniphier-system-bus";
539 reg = <0x58c00000 0x400>;
540 #address-cells = <2>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_system_bus>;
547 compatible = "socionext,uniphier-smpctrl";
548 reg = <0x59801000 0x400>;
552 compatible = "socionext,uniphier-ld20-sdctrl",
553 "simple-mfd", "syscon";
554 reg = <0x59810000 0x400>;
557 compatible = "socionext,uniphier-ld20-sd-clock";
562 compatible = "socionext,uniphier-ld20-sd-reset";
568 compatible = "socionext,uniphier-ld20-perictrl",
569 "simple-mfd", "syscon";
570 reg = <0x59820000 0x200>;
573 compatible = "socionext,uniphier-ld20-peri-clock";
578 compatible = "socionext,uniphier-ld20-peri-reset";
584 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
585 reg = <0x5a000000 0x400>;
586 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&pinctrl_emmc>;
589 clocks = <&sys_clk 4>;
590 resets = <&sys_rst 4>;
594 mmc-pwrseq = <&emmc_pwrseq>;
595 cdns,phy-input-delay-legacy = <9>;
596 cdns,phy-input-delay-mmc-highspeed = <2>;
597 cdns,phy-input-delay-mmc-ddr = <3>;
598 cdns,phy-dll-delay-sdclk = <21>;
599 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
603 compatible = "socionext,uniphier-sd-v3.1.1";
605 reg = <0x5a400000 0x800>;
606 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_sd>;
609 clocks = <&sd_clk 0>;
610 reset-names = "host";
611 resets = <&sd_rst 0>;
616 soc_glue: soc-glue@5f800000 {
617 compatible = "socionext,uniphier-ld20-soc-glue",
618 "simple-mfd", "syscon";
619 reg = <0x5f800000 0x2000>;
622 compatible = "socionext,uniphier-ld20-pinctrl";
627 compatible = "socionext,uniphier-ld20-soc-glue-debug",
629 #address-cells = <1>;
631 ranges = <0 0x5f900000 0x2000>;
634 compatible = "socionext,uniphier-efuse";
639 compatible = "socionext,uniphier-efuse";
641 #address-cells = <1>;
645 usb_rterm0: trim@54,4 {
649 usb_rterm1: trim@55,4 {
653 usb_rterm2: trim@58,4 {
657 usb_rterm3: trim@59,4 {
661 usb_sel_t0: trim@54,0 {
665 usb_sel_t1: trim@55,0 {
669 usb_sel_t2: trim@58,0 {
673 usb_sel_t3: trim@59,0 {
677 usb_hs_i0: trim@56,0 {
681 usb_hs_i2: trim@5a,0 {
688 xdmac: dma-controller@5fc10000 {
689 compatible = "socionext,uniphier-xdmac";
690 reg = <0x5fc10000 0x5300>;
691 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
696 aidet: interrupt-controller@5fc20000 {
697 compatible = "socionext,uniphier-ld20-aidet";
698 reg = <0x5fc20000 0x200>;
699 interrupt-controller;
700 #interrupt-cells = <2>;
703 gic: interrupt-controller@5fe00000 {
704 compatible = "arm,gic-v3";
705 reg = <0x5fe00000 0x10000>, /* GICD */
706 <0x5fe80000 0x80000>; /* GICR */
707 interrupt-controller;
708 #interrupt-cells = <3>;
709 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
713 compatible = "socionext,uniphier-ld20-sysctrl",
714 "simple-mfd", "syscon";
715 reg = <0x61840000 0x10000>;
718 compatible = "socionext,uniphier-ld20-clock";
723 compatible = "socionext,uniphier-ld20-reset";
728 compatible = "socionext,uniphier-wdt";
731 pvtctl: thermal-sensor {
732 compatible = "socionext,uniphier-ld20-thermal";
733 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
734 #thermal-sensor-cells = <0>;
735 socionext,tmod-calibration = <0x0f22 0x68ee>;
739 eth: ethernet@65000000 {
740 compatible = "socionext,uniphier-ld20-ave4";
742 reg = <0x65000000 0x8500>;
743 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&pinctrl_ether_rgmii>;
746 clock-names = "ether";
747 clocks = <&sys_clk 6>;
748 reset-names = "ether";
749 resets = <&sys_rst 6>;
750 phy-mode = "rgmii-id";
751 local-mac-address = [00 00 00 00 00 00];
752 socionext,syscon-phy-mode = <&soc_glue 0>;
755 #address-cells = <1>;
761 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
763 reg = <0x65a00000 0xcd00>;
764 interrupt-names = "host";
765 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
768 <&pinctrl_usb2>, <&pinctrl_usb3>;
769 clock-names = "ref", "bus_early", "suspend";
770 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
771 resets = <&usb_rst 15>;
772 phys = <&usb_hsphy0>, <&usb_hsphy1>,
773 <&usb_hsphy2>, <&usb_hsphy3>,
774 <&usb_ssphy0>, <&usb_ssphy1>;
778 usb-controller@65b00000 {
779 compatible = "socionext,uniphier-ld20-dwc3-glue",
781 #address-cells = <1>;
783 ranges = <0 0x65b00000 0x400>;
786 compatible = "socionext,uniphier-ld20-usb3-reset";
789 clock-names = "link";
790 clocks = <&sys_clk 14>;
791 reset-names = "link";
792 resets = <&sys_rst 14>;
795 usb_vbus0: regulator@100 {
796 compatible = "socionext,uniphier-ld20-usb3-regulator";
798 clock-names = "link";
799 clocks = <&sys_clk 14>;
800 reset-names = "link";
801 resets = <&sys_rst 14>;
804 usb_vbus1: regulator@110 {
805 compatible = "socionext,uniphier-ld20-usb3-regulator";
807 clock-names = "link";
808 clocks = <&sys_clk 14>;
809 reset-names = "link";
810 resets = <&sys_rst 14>;
813 usb_vbus2: regulator@120 {
814 compatible = "socionext,uniphier-ld20-usb3-regulator";
816 clock-names = "link";
817 clocks = <&sys_clk 14>;
818 reset-names = "link";
819 resets = <&sys_rst 14>;
822 usb_vbus3: regulator@130 {
823 compatible = "socionext,uniphier-ld20-usb3-regulator";
825 clock-names = "link";
826 clocks = <&sys_clk 14>;
827 reset-names = "link";
828 resets = <&sys_rst 14>;
831 usb_hsphy0: hs-phy@200 {
832 compatible = "socionext,uniphier-ld20-usb3-hsphy";
835 clock-names = "link", "phy";
836 clocks = <&sys_clk 14>, <&sys_clk 16>;
837 reset-names = "link", "phy";
838 resets = <&sys_rst 14>, <&sys_rst 16>;
839 vbus-supply = <&usb_vbus0>;
840 nvmem-cell-names = "rterm", "sel_t", "hs_i";
841 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
845 usb_hsphy1: hs-phy@210 {
846 compatible = "socionext,uniphier-ld20-usb3-hsphy";
849 clock-names = "link", "phy";
850 clocks = <&sys_clk 14>, <&sys_clk 16>;
851 reset-names = "link", "phy";
852 resets = <&sys_rst 14>, <&sys_rst 16>;
853 vbus-supply = <&usb_vbus1>;
854 nvmem-cell-names = "rterm", "sel_t", "hs_i";
855 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
859 usb_hsphy2: hs-phy@220 {
860 compatible = "socionext,uniphier-ld20-usb3-hsphy";
863 clock-names = "link", "phy";
864 clocks = <&sys_clk 14>, <&sys_clk 17>;
865 reset-names = "link", "phy";
866 resets = <&sys_rst 14>, <&sys_rst 17>;
867 vbus-supply = <&usb_vbus2>;
868 nvmem-cell-names = "rterm", "sel_t", "hs_i";
869 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
873 usb_hsphy3: hs-phy@230 {
874 compatible = "socionext,uniphier-ld20-usb3-hsphy";
877 clock-names = "link", "phy";
878 clocks = <&sys_clk 14>, <&sys_clk 17>;
879 reset-names = "link", "phy";
880 resets = <&sys_rst 14>, <&sys_rst 17>;
881 vbus-supply = <&usb_vbus3>;
882 nvmem-cell-names = "rterm", "sel_t", "hs_i";
883 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
887 usb_ssphy0: ss-phy@300 {
888 compatible = "socionext,uniphier-ld20-usb3-ssphy";
891 clock-names = "link", "phy";
892 clocks = <&sys_clk 14>, <&sys_clk 18>;
893 reset-names = "link", "phy";
894 resets = <&sys_rst 14>, <&sys_rst 18>;
895 vbus-supply = <&usb_vbus0>;
898 usb_ssphy1: ss-phy@310 {
899 compatible = "socionext,uniphier-ld20-usb3-ssphy";
902 clock-names = "link", "phy";
903 clocks = <&sys_clk 14>, <&sys_clk 19>;
904 reset-names = "link", "phy";
905 resets = <&sys_rst 14>, <&sys_rst 19>;
906 vbus-supply = <&usb_vbus1>;
910 pcie: pcie@66000000 {
911 compatible = "socionext,uniphier-pcie";
913 reg-names = "dbi", "link", "config";
914 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
915 <0x2fff0000 0x10000>;
916 #address-cells = <3>;
918 clocks = <&sys_clk 24>;
919 resets = <&sys_rst 24>;
922 bus-range = <0x0 0xff>;
926 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
927 /* non-prefetchable memory */
928 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
929 #interrupt-cells = <1>;
930 interrupt-names = "dma", "msi";
931 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
933 interrupt-map-mask = <0 0 0 7>;
934 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
935 <0 0 0 2 &pcie_intc 1>, /* INTB */
936 <0 0 0 3 &pcie_intc 2>, /* INTC */
937 <0 0 0 4 &pcie_intc 3>; /* INTD */
938 phy-names = "pcie-phy";
941 pcie_intc: legacy-interrupt-controller {
942 interrupt-controller;
943 #interrupt-cells = <1>;
944 interrupt-parent = <&gic>;
945 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
949 pcie_phy: phy@66038000 {
950 compatible = "socionext,uniphier-ld20-pcie-phy";
951 reg = <0x66038000 0x4000>;
953 clock-names = "link";
954 clocks = <&sys_clk 24>;
955 reset-names = "link";
956 resets = <&sys_rst 24>;
957 socionext,syscon = <&soc_glue>;
960 nand: nand-controller@68000000 {
961 compatible = "socionext,uniphier-denali-nand-v5b";
963 reg-names = "nand_data", "denali_reg";
964 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
965 #address-cells = <1>;
967 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&pinctrl_nand>;
970 clock-names = "nand", "nand_x", "ecc";
971 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
972 reset-names = "nand", "reg";
973 resets = <&sys_rst 2>, <&sys_rst 2>;
978 #include "uniphier-pinctrl.dtsi"
981 drive-strength = <4>; /* default: 3.5mA */
985 drive-strength = <5>; /* 5mA */
990 drive-strength = <4>; /* default: 3.5mA */
994 drive-strength = <11>; /* 11mA */