2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
49 compatible = "socionext,uniphier-ld11";
52 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 enable-method = "spin-table";
74 cpu-release-addr = <0 0x80000000>;
79 compatible = "arm,cortex-a53", "arm,armv8";
81 enable-method = "spin-table";
82 cpu-release-addr = <0 0x80000000>;
88 compatible = "fixed-clock";
90 clock-frequency = <25000000>;
95 compatible = "arm,armv8-timer";
96 interrupts = <1 13 4>,
103 compatible = "simple-bus";
104 #address-cells = <1>;
106 ranges = <0 0 0 0xffffffff>;
108 serial0: serial@54006800 {
109 compatible = "socionext,uniphier-uart";
111 reg = <0x54006800 0x40>;
112 interrupts = <0 33 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_uart0>;
115 clocks = <&peri_clk 0>;
118 serial1: serial@54006900 {
119 compatible = "socionext,uniphier-uart";
121 reg = <0x54006900 0x40>;
122 interrupts = <0 35 4>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart1>;
125 clocks = <&peri_clk 1>;
128 serial2: serial@54006a00 {
129 compatible = "socionext,uniphier-uart";
131 reg = <0x54006a00 0x40>;
132 interrupts = <0 37 4>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_uart2>;
135 clocks = <&peri_clk 2>;
138 serial3: serial@54006b00 {
139 compatible = "socionext,uniphier-uart";
141 reg = <0x54006b00 0x40>;
142 interrupts = <0 177 4>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_uart3>;
145 clocks = <&peri_clk 3>;
149 compatible = "socionext,uniphier-fi2c";
151 reg = <0x58780000 0x80>;
152 #address-cells = <1>;
154 interrupts = <0 41 4>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c0>;
157 clocks = <&peri_clk 4>;
158 clock-frequency = <100000>;
162 compatible = "socionext,uniphier-fi2c";
164 reg = <0x58781000 0x80>;
165 #address-cells = <1>;
167 interrupts = <0 42 4>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 clocks = <&peri_clk 5>;
171 clock-frequency = <100000>;
175 compatible = "socionext,uniphier-fi2c";
176 reg = <0x58782000 0x80>;
177 #address-cells = <1>;
179 interrupts = <0 43 4>;
180 clocks = <&peri_clk 6>;
181 clock-frequency = <400000>;
185 compatible = "socionext,uniphier-fi2c";
187 reg = <0x58783000 0x80>;
188 #address-cells = <1>;
190 interrupts = <0 44 4>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c3>;
193 clocks = <&peri_clk 7>;
194 clock-frequency = <100000>;
198 compatible = "socionext,uniphier-fi2c";
200 reg = <0x58784000 0x80>;
201 #address-cells = <1>;
203 interrupts = <0 45 4>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c4>;
206 clocks = <&peri_clk 8>;
207 clock-frequency = <100000>;
211 compatible = "socionext,uniphier-fi2c";
212 reg = <0x58785000 0x80>;
213 #address-cells = <1>;
215 interrupts = <0 25 4>;
216 clocks = <&peri_clk 9>;
217 clock-frequency = <400000>;
220 system_bus: system-bus@58c00000 {
221 compatible = "socionext,uniphier-system-bus";
223 reg = <0x58c00000 0x400>;
224 #address-cells = <2>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_system_bus>;
231 compatible = "socionext,uniphier-smpctrl";
232 reg = <0x59801000 0x400>;
236 compatible = "socionext,uniphier-perictrl",
237 "simple-mfd", "syscon";
238 reg = <0x59820000 0x200>;
241 compatible = "socionext,uniphier-ld11-peri-clock";
246 compatible = "socionext,uniphier-ld11-peri-reset";
252 compatible = "socionext,uniphier-ehci", "generic-ehci";
254 reg = <0x5a800100 0x100>;
255 interrupts = <0 243 4>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_usb0>;
258 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
259 resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
263 compatible = "socionext,uniphier-ehci", "generic-ehci";
265 reg = <0x5a810100 0x100>;
266 interrupts = <0 244 4>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_usb1>;
269 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
270 resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
274 compatible = "socionext,uniphier-ehci", "generic-ehci";
276 reg = <0x5a820100 0x100>;
277 interrupts = <0 245 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usb2>;
280 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
281 resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
285 compatible = "socionext,uniphier-mioctrl",
286 "simple-mfd", "syscon";
287 reg = <0x5b3e0000 0x800>;
290 compatible = "socionext,uniphier-ld11-mio-clock";
295 compatible = "socionext,uniphier-ld11-mio-reset";
297 resets = <&sys_rst 7>;
302 compatible = "socionext,uniphier-soc-glue",
303 "simple-mfd", "syscon";
304 reg = <0x5f800000 0x2000>;
307 compatible = "socionext,uniphier-ld11-pinctrl";
311 gic: interrupt-controller@5fe00000 {
312 compatible = "arm,gic-v3";
313 reg = <0x5fe00000 0x10000>, /* GICD */
314 <0x5fe40000 0x80000>; /* GICR */
315 interrupt-controller;
316 #interrupt-cells = <3>;
317 interrupts = <1 9 4>;
321 compatible = "socionext,uniphier-ld11-sysctrl",
322 "simple-mfd", "syscon";
323 reg = <0x61840000 0x4000>;
326 compatible = "socionext,uniphier-ld11-clock";
331 compatible = "socionext,uniphier-ld11-reset";
338 /include/ "uniphier-pinctrl.dtsi"