1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53";
47 clocks = <&sys_clk 33>;
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cluster0_opp>;
60 cluster0_opp: opp-table {
61 compatible = "operating-points-v2";
65 opp-hz = /bits/ 64 <245000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <250000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <490000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <500000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <653334000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <666667000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <980000000>;
90 clock-latency-ns = <300>;
95 compatible = "arm,psci-1.0";
101 compatible = "fixed-clock";
103 clock-frequency = <25000000>;
107 emmc_pwrseq: emmc-pwrseq {
108 compatible = "mmc-pwrseq-emmc";
109 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
113 compatible = "arm,armv8-timer";
114 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
121 #address-cells = <2>;
125 secure-memory@81000000 {
126 reg = <0x0 0x81000000 0x0 0x01000000>;
132 compatible = "simple-bus";
133 #address-cells = <1>;
135 ranges = <0 0 0 0xffffffff>;
138 compatible = "socionext,uniphier-scssi";
140 reg = <0x54006000 0x100>;
141 #address-cells = <1>;
143 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_spi0>;
146 clocks = <&peri_clk 11>;
147 resets = <&peri_rst 11>;
151 compatible = "socionext,uniphier-scssi";
153 reg = <0x54006100 0x100>;
154 #address-cells = <1>;
156 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_spi1>;
159 clocks = <&peri_clk 12>;
160 resets = <&peri_rst 12>;
163 serial0: serial@54006800 {
164 compatible = "socionext,uniphier-uart";
166 reg = <0x54006800 0x40>;
167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart0>;
170 clocks = <&peri_clk 0>;
171 resets = <&peri_rst 0>;
174 serial1: serial@54006900 {
175 compatible = "socionext,uniphier-uart";
177 reg = <0x54006900 0x40>;
178 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart1>;
181 clocks = <&peri_clk 1>;
182 resets = <&peri_rst 1>;
185 serial2: serial@54006a00 {
186 compatible = "socionext,uniphier-uart";
188 reg = <0x54006a00 0x40>;
189 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart2>;
192 clocks = <&peri_clk 2>;
193 resets = <&peri_rst 2>;
196 serial3: serial@54006b00 {
197 compatible = "socionext,uniphier-uart";
199 reg = <0x54006b00 0x40>;
200 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart3>;
203 clocks = <&peri_clk 3>;
204 resets = <&peri_rst 3>;
207 gpio: gpio@55000000 {
208 compatible = "socionext,uniphier-gpio";
209 reg = <0x55000000 0x200>;
210 interrupt-parent = <&aidet>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
215 gpio-ranges = <&pinctrl 0 0 0>,
221 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-ld11-aio";
234 reg = <0x56000000 0x80000>;
235 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_aout1>,
240 clocks = <&sys_clk 40>;
242 resets = <&sys_rst 40>;
243 #sound-dai-cells = <1>;
244 socionext,syscon = <&soc_glue>;
252 i2s_pcmin2: endpoint {
259 remote-endpoint = <&evea_line>;
264 i2s_hpcmout1: endpoint {
271 remote-endpoint = <&evea_hp>;
275 spdif_port0: port@5 {
276 spdif_hiecout1: endpoint {
281 i2s_epcmout2: endpoint {
286 i2s_epcmout3: endpoint {
290 comp_spdif_port0: port@8 {
291 comp_spdif_hiecout1: endpoint {
297 compatible = "socionext,uniphier-evea";
298 reg = <0x57900000 0x1000>;
299 clock-names = "evea", "exiv";
300 clocks = <&sys_clk 41>, <&sys_clk 42>;
301 reset-names = "evea", "exiv", "adamv";
302 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
303 #sound-dai-cells = <1>;
306 evea_line: endpoint {
307 remote-endpoint = <&i2s_line>;
313 remote-endpoint = <&i2s_hp>;
319 compatible = "socionext,uniphier-ld11-adamv",
320 "simple-mfd", "syscon";
321 reg = <0x57920000 0x1000>;
323 adamv_rst: reset-controller {
324 compatible = "socionext,uniphier-ld11-adamv-reset";
330 compatible = "socionext,uniphier-fi2c";
332 reg = <0x58780000 0x80>;
333 #address-cells = <1>;
335 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c0>;
338 clocks = <&peri_clk 4>;
339 resets = <&peri_rst 4>;
340 clock-frequency = <100000>;
344 compatible = "socionext,uniphier-fi2c";
346 reg = <0x58781000 0x80>;
347 #address-cells = <1>;
349 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_i2c1>;
352 clocks = <&peri_clk 5>;
353 resets = <&peri_rst 5>;
354 clock-frequency = <100000>;
358 compatible = "socionext,uniphier-fi2c";
359 reg = <0x58782000 0x80>;
360 #address-cells = <1>;
362 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&peri_clk 6>;
364 resets = <&peri_rst 6>;
365 clock-frequency = <400000>;
369 compatible = "socionext,uniphier-fi2c";
371 reg = <0x58783000 0x80>;
372 #address-cells = <1>;
374 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c3>;
377 clocks = <&peri_clk 7>;
378 resets = <&peri_rst 7>;
379 clock-frequency = <100000>;
383 compatible = "socionext,uniphier-fi2c";
385 reg = <0x58784000 0x80>;
386 #address-cells = <1>;
388 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_i2c4>;
391 clocks = <&peri_clk 8>;
392 resets = <&peri_rst 8>;
393 clock-frequency = <100000>;
397 compatible = "socionext,uniphier-fi2c";
398 reg = <0x58785000 0x80>;
399 #address-cells = <1>;
401 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&peri_clk 9>;
403 resets = <&peri_rst 9>;
404 clock-frequency = <400000>;
407 system_bus: system-bus@58c00000 {
408 compatible = "socionext,uniphier-system-bus";
410 reg = <0x58c00000 0x400>;
411 #address-cells = <2>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_system_bus>;
418 compatible = "socionext,uniphier-smpctrl";
419 reg = <0x59801000 0x400>;
423 compatible = "socionext,uniphier-ld11-sdctrl",
424 "simple-mfd", "syscon";
425 reg = <0x59810000 0x400>;
427 sd_rst: reset-controller {
428 compatible = "socionext,uniphier-ld11-sd-reset";
434 compatible = "socionext,uniphier-ld11-perictrl",
435 "simple-mfd", "syscon";
436 reg = <0x59820000 0x200>;
438 peri_clk: clock-controller {
439 compatible = "socionext,uniphier-ld11-peri-clock";
443 peri_rst: reset-controller {
444 compatible = "socionext,uniphier-ld11-peri-reset";
450 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
451 reg = <0x5a000000 0x400>;
452 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_emmc>;
455 clocks = <&sys_clk 4>;
456 resets = <&sys_rst 4>;
460 mmc-pwrseq = <&emmc_pwrseq>;
461 cdns,phy-input-delay-legacy = <9>;
462 cdns,phy-input-delay-mmc-highspeed = <2>;
463 cdns,phy-input-delay-mmc-ddr = <3>;
464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
469 compatible = "socionext,uniphier-ehci", "generic-ehci";
471 reg = <0x5a800100 0x100>;
472 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usb0>;
475 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
477 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
481 has-transaction-translator;
485 compatible = "socionext,uniphier-ehci", "generic-ehci";
487 reg = <0x5a810100 0x100>;
488 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_usb1>;
491 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
493 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
497 has-transaction-translator;
501 compatible = "socionext,uniphier-ehci", "generic-ehci";
503 reg = <0x5a820100 0x100>;
504 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_usb2>;
507 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
509 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
513 has-transaction-translator;
517 compatible = "socionext,uniphier-ld11-mioctrl",
518 "simple-mfd", "syscon";
519 reg = <0x5b3e0000 0x800>;
521 mio_clk: clock-controller {
522 compatible = "socionext,uniphier-ld11-mio-clock";
526 mio_rst: reset-controller {
527 compatible = "socionext,uniphier-ld11-mio-reset";
529 resets = <&sys_rst 7>;
533 soc_glue: syscon@5f800000 {
534 compatible = "socionext,uniphier-ld11-soc-glue",
535 "simple-mfd", "syscon";
536 reg = <0x5f800000 0x2000>;
539 compatible = "socionext,uniphier-ld11-pinctrl";
543 compatible = "socionext,uniphier-ld11-usb2-phy";
544 #address-cells = <1>;
565 compatible = "socionext,uniphier-ld11-soc-glue-debug",
566 "simple-mfd", "syscon";
567 reg = <0x5f900000 0x2000>;
568 #address-cells = <1>;
570 ranges = <0 0x5f900000 0x2000>;
573 compatible = "socionext,uniphier-efuse";
578 compatible = "socionext,uniphier-efuse";
583 xdmac: dma-controller@5fc10000 {
584 compatible = "socionext,uniphier-xdmac";
585 reg = <0x5fc10000 0x5300>;
586 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
591 aidet: interrupt-controller@5fc20000 {
592 compatible = "socionext,uniphier-ld11-aidet";
593 reg = <0x5fc20000 0x200>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
598 gic: interrupt-controller@5fe00000 {
599 compatible = "arm,gic-v3";
600 reg = <0x5fe00000 0x10000>, /* GICD */
601 <0x5fe40000 0x80000>; /* GICR */
602 interrupt-controller;
603 #interrupt-cells = <3>;
604 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
608 compatible = "socionext,uniphier-ld11-sysctrl",
609 "simple-mfd", "syscon";
610 reg = <0x61840000 0x10000>;
612 sys_clk: clock-controller {
613 compatible = "socionext,uniphier-ld11-clock";
617 sys_rst: reset-controller {
618 compatible = "socionext,uniphier-ld11-reset";
623 compatible = "socionext,uniphier-wdt";
627 eth: ethernet@65000000 {
628 compatible = "socionext,uniphier-ld11-ave4";
630 reg = <0x65000000 0x8500>;
631 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
632 clock-names = "ether";
633 clocks = <&sys_clk 6>;
634 reset-names = "ether";
635 resets = <&sys_rst 6>;
636 phy-mode = "internal";
637 local-mac-address = [00 00 00 00 00 00];
638 socionext,syscon-phy-mode = <&soc_glue 0>;
641 #address-cells = <1>;
646 nand: nand-controller@68000000 {
647 compatible = "socionext,uniphier-denali-nand-v5b";
649 reg-names = "nand_data", "denali_reg";
650 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
651 #address-cells = <1>;
653 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_nand>;
656 clock-names = "nand", "nand_x", "ecc";
657 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
658 reset-names = "nand", "reg";
659 resets = <&sys_rst 2>, <&sys_rst 2>;
664 #include "uniphier-pinctrl.dtsi"
667 drive-strength = <4>; /* default: 4mA */
671 drive-strength = <8>; /* 8mA */