arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD11 SoC
   4 //
   5 // Copyright (C) 2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "socionext,uniphier-ld11";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&gic>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu-map {
  23                         cluster0 {
  24                                 core0 {
  25                                         cpu = <&cpu0>;
  26                                 };
  27                                 core1 {
  28                                         cpu = <&cpu1>;
  29                                 };
  30                         };
  31                 };
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0 0x000>;
  37                         clocks = <&sys_clk 33>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                         operating-points-v2 = <&cluster0_opp>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         reg = <0 0x001>;
  47                         clocks = <&sys_clk 33>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&l2>;
  50                         operating-points-v2 = <&cluster0_opp>;
  51                 };
  52
  53                 l2: l2-cache {
  54                         compatible = "cache";
  55                 };
  56         };
  57
  58         cluster0_opp: opp-table {
  59                 compatible = "operating-points-v2";
  60                 opp-shared;
  61
  62                 opp-245000000 {
  63                         opp-hz = /bits/ 64 <245000000>;
  64                         clock-latency-ns = <300>;
  65                 };
  66                 opp-250000000 {
  67                         opp-hz = /bits/ 64 <250000000>;
  68                         clock-latency-ns = <300>;
  69                 };
  70                 opp-490000000 {
  71                         opp-hz = /bits/ 64 <490000000>;
  72                         clock-latency-ns = <300>;
  73                 };
  74                 opp-500000000 {
  75                         opp-hz = /bits/ 64 <500000000>;
  76                         clock-latency-ns = <300>;
  77                 };
  78                 opp-653334000 {
  79                         opp-hz = /bits/ 64 <653334000>;
  80                         clock-latency-ns = <300>;
  81                 };
  82                 opp-666667000 {
  83                         opp-hz = /bits/ 64 <666667000>;
  84                         clock-latency-ns = <300>;
  85                 };
  86                 opp-980000000 {
  87                         opp-hz = /bits/ 64 <980000000>;
  88                         clock-latency-ns = <300>;
  89                 };
  90         };
  91
  92         psci {
  93                 compatible = "arm,psci-1.0";
  94                 method = "smc";
  95         };
  96
  97         clocks {
  98                 refclk: ref {
  99                         compatible = "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <25000000>;
 102                 };
 103         };
 104
 105         emmc_pwrseq: emmc-pwrseq {
 106                 compatible = "mmc-pwrseq-emmc";
 107                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv8-timer";
 112                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 114                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 115                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 116         };
 117
 118         reserved-memory {
 119                 #address-cells = <2>;
 120                 #size-cells = <2>;
 121                 ranges;
 122
 123                 secure-memory@81000000 {
 124                         reg = <0x0 0x81000000 0x0 0x01000000>;
 125                         no-map;
 126                 };
 127         };
 128
 129         soc@0 {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges = <0 0 0 0xffffffff>;
 134
 135                 spi0: spi@54006000 {
 136                         compatible = "socionext,uniphier-scssi";
 137                         status = "disabled";
 138                         reg = <0x54006000 0x100>;
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 142                         pinctrl-names = "default";
 143                         pinctrl-0 = <&pinctrl_spi0>;
 144                         clocks = <&peri_clk 11>;
 145                         resets = <&peri_rst 11>;
 146                 };
 147
 148                 spi1: spi@54006100 {
 149                         compatible = "socionext,uniphier-scssi";
 150                         status = "disabled";
 151                         reg = <0x54006100 0x100>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 155                         pinctrl-names = "default";
 156                         pinctrl-0 = <&pinctrl_spi1>;
 157                         clocks = <&peri_clk 12>;
 158                         resets = <&peri_rst 12>;
 159                 };
 160
 161                 serial0: serial@54006800 {
 162                         compatible = "socionext,uniphier-uart";
 163                         status = "disabled";
 164                         reg = <0x54006800 0x40>;
 165                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_uart0>;
 168                         clocks = <&peri_clk 0>;
 169                         resets = <&peri_rst 0>;
 170                 };
 171
 172                 serial1: serial@54006900 {
 173                         compatible = "socionext,uniphier-uart";
 174                         status = "disabled";
 175                         reg = <0x54006900 0x40>;
 176                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 177                         pinctrl-names = "default";
 178                         pinctrl-0 = <&pinctrl_uart1>;
 179                         clocks = <&peri_clk 1>;
 180                         resets = <&peri_rst 1>;
 181                 };
 182
 183                 serial2: serial@54006a00 {
 184                         compatible = "socionext,uniphier-uart";
 185                         status = "disabled";
 186                         reg = <0x54006a00 0x40>;
 187                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&pinctrl_uart2>;
 190                         clocks = <&peri_clk 2>;
 191                         resets = <&peri_rst 2>;
 192                 };
 193
 194                 serial3: serial@54006b00 {
 195                         compatible = "socionext,uniphier-uart";
 196                         status = "disabled";
 197                         reg = <0x54006b00 0x40>;
 198                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 199                         pinctrl-names = "default";
 200                         pinctrl-0 = <&pinctrl_uart3>;
 201                         clocks = <&peri_clk 3>;
 202                         resets = <&peri_rst 3>;
 203                 };
 204
 205                 gpio: gpio@55000000 {
 206                         compatible = "socionext,uniphier-gpio";
 207                         reg = <0x55000000 0x200>;
 208                         interrupt-parent = <&aidet>;
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                         gpio-controller;
 212                         #gpio-cells = <2>;
 213                         gpio-ranges = <&pinctrl 0 0 0>,
 214                                       <&pinctrl 43 0 0>,
 215                                       <&pinctrl 51 0 0>,
 216                                       <&pinctrl 96 0 0>,
 217                                       <&pinctrl 160 0 0>,
 218                                       <&pinctrl 184 0 0>;
 219                         gpio-ranges-group-names = "gpio_range0",
 220                                                   "gpio_range1",
 221                                                   "gpio_range2",
 222                                                   "gpio_range3",
 223                                                   "gpio_range4",
 224                                                   "gpio_range5";
 225                         ngpios = <200>;
 226                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 227                                                      <21 217 3>;
 228                 };
 229
 230                 audio@56000000 {
 231                         compatible = "socionext,uniphier-ld11-aio";
 232                         reg = <0x56000000 0x80000>;
 233                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_aout1>,
 236                                     <&pinctrl_aoutiec1>;
 237                         clock-names = "aio";
 238                         clocks = <&sys_clk 40>;
 239                         reset-names = "aio";
 240                         resets = <&sys_rst 40>;
 241                         #sound-dai-cells = <1>;
 242                         socionext,syscon = <&soc_glue>;
 243
 244                         i2s_port0: port@0 {
 245                                 i2s_hdmi: endpoint {
 246                                 };
 247                         };
 248
 249                         i2s_port1: port@1 {
 250                                 i2s_pcmin2: endpoint {
 251                                 };
 252                         };
 253
 254                         i2s_port2: port@2 {
 255                                 i2s_line: endpoint {
 256                                         dai-format = "i2s";
 257                                         remote-endpoint = <&evea_line>;
 258                                 };
 259                         };
 260
 261                         i2s_port3: port@3 {
 262                                 i2s_hpcmout1: endpoint {
 263                                 };
 264                         };
 265
 266                         i2s_port4: port@4 {
 267                                 i2s_hp: endpoint {
 268                                         dai-format = "i2s";
 269                                         remote-endpoint = <&evea_hp>;
 270                                 };
 271                         };
 272
 273                         spdif_port0: port@5 {
 274                                 spdif_hiecout1: endpoint {
 275                                 };
 276                         };
 277
 278                         src_port0: port@6 {
 279                                 i2s_epcmout2: endpoint {
 280                                 };
 281                         };
 282
 283                         src_port1: port@7 {
 284                                 i2s_epcmout3: endpoint {
 285                                 };
 286                         };
 287
 288                         comp_spdif_port0: port@8 {
 289                                 comp_spdif_hiecout1: endpoint {
 290                                 };
 291                         };
 292                 };
 293
 294                 codec@57900000 {
 295                         compatible = "socionext,uniphier-evea";
 296                         reg = <0x57900000 0x1000>;
 297                         clock-names = "evea", "exiv";
 298                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 299                         reset-names = "evea", "exiv", "adamv";
 300                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 301                         #sound-dai-cells = <1>;
 302
 303                         port@0 {
 304                                 evea_line: endpoint {
 305                                         remote-endpoint = <&i2s_line>;
 306                                 };
 307                         };
 308
 309                         port@1 {
 310                                 evea_hp: endpoint {
 311                                         remote-endpoint = <&i2s_hp>;
 312                                 };
 313                         };
 314                 };
 315
 316                 adamv@57920000 {
 317                         compatible = "socionext,uniphier-ld11-adamv",
 318                                      "simple-mfd", "syscon";
 319                         reg = <0x57920000 0x1000>;
 320
 321                         adamv_rst: reset {
 322                                 compatible = "socionext,uniphier-ld11-adamv-reset";
 323                                 #reset-cells = <1>;
 324                         };
 325                 };
 326
 327                 i2c0: i2c@58780000 {
 328                         compatible = "socionext,uniphier-fi2c";
 329                         status = "disabled";
 330                         reg = <0x58780000 0x80>;
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&pinctrl_i2c0>;
 336                         clocks = <&peri_clk 4>;
 337                         resets = <&peri_rst 4>;
 338                         clock-frequency = <100000>;
 339                 };
 340
 341                 i2c1: i2c@58781000 {
 342                         compatible = "socionext,uniphier-fi2c";
 343                         status = "disabled";
 344                         reg = <0x58781000 0x80>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 348                         pinctrl-names = "default";
 349                         pinctrl-0 = <&pinctrl_i2c1>;
 350                         clocks = <&peri_clk 5>;
 351                         resets = <&peri_rst 5>;
 352                         clock-frequency = <100000>;
 353                 };
 354
 355                 i2c2: i2c@58782000 {
 356                         compatible = "socionext,uniphier-fi2c";
 357                         reg = <0x58782000 0x80>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 361                         clocks = <&peri_clk 6>;
 362                         resets = <&peri_rst 6>;
 363                         clock-frequency = <400000>;
 364                 };
 365
 366                 i2c3: i2c@58783000 {
 367                         compatible = "socionext,uniphier-fi2c";
 368                         status = "disabled";
 369                         reg = <0x58783000 0x80>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 373                         pinctrl-names = "default";
 374                         pinctrl-0 = <&pinctrl_i2c3>;
 375                         clocks = <&peri_clk 7>;
 376                         resets = <&peri_rst 7>;
 377                         clock-frequency = <100000>;
 378                 };
 379
 380                 i2c4: i2c@58784000 {
 381                         compatible = "socionext,uniphier-fi2c";
 382                         status = "disabled";
 383                         reg = <0x58784000 0x80>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 387                         pinctrl-names = "default";
 388                         pinctrl-0 = <&pinctrl_i2c4>;
 389                         clocks = <&peri_clk 8>;
 390                         resets = <&peri_rst 8>;
 391                         clock-frequency = <100000>;
 392                 };
 393
 394                 i2c5: i2c@58785000 {
 395                         compatible = "socionext,uniphier-fi2c";
 396                         reg = <0x58785000 0x80>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&peri_clk 9>;
 401                         resets = <&peri_rst 9>;
 402                         clock-frequency = <400000>;
 403                 };
 404
 405                 system_bus: system-bus@58c00000 {
 406                         compatible = "socionext,uniphier-system-bus";
 407                         status = "disabled";
 408                         reg = <0x58c00000 0x400>;
 409                         #address-cells = <2>;
 410                         #size-cells = <1>;
 411                         pinctrl-names = "default";
 412                         pinctrl-0 = <&pinctrl_system_bus>;
 413                 };
 414
 415                 smpctrl@59801000 {
 416                         compatible = "socionext,uniphier-smpctrl";
 417                         reg = <0x59801000 0x400>;
 418                 };
 419
 420                 sdctrl@59810000 {
 421                         compatible = "socionext,uniphier-ld11-sdctrl",
 422                                      "simple-mfd", "syscon";
 423                         reg = <0x59810000 0x400>;
 424
 425                         sd_rst: reset {
 426                                 compatible = "socionext,uniphier-ld11-sd-reset";
 427                                 #reset-cells = <1>;
 428                         };
 429                 };
 430
 431                 perictrl@59820000 {
 432                         compatible = "socionext,uniphier-ld11-perictrl",
 433                                      "simple-mfd", "syscon";
 434                         reg = <0x59820000 0x200>;
 435
 436                         peri_clk: clock {
 437                                 compatible = "socionext,uniphier-ld11-peri-clock";
 438                                 #clock-cells = <1>;
 439                         };
 440
 441                         peri_rst: reset {
 442                                 compatible = "socionext,uniphier-ld11-peri-reset";
 443                                 #reset-cells = <1>;
 444                         };
 445                 };
 446
 447                 emmc: mmc@5a000000 {
 448                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 449                         reg = <0x5a000000 0x400>;
 450                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&pinctrl_emmc>;
 453                         clocks = <&sys_clk 4>;
 454                         resets = <&sys_rst 4>;
 455                         bus-width = <8>;
 456                         mmc-ddr-1_8v;
 457                         mmc-hs200-1_8v;
 458                         mmc-pwrseq = <&emmc_pwrseq>;
 459                         cdns,phy-input-delay-legacy = <9>;
 460                         cdns,phy-input-delay-mmc-highspeed = <2>;
 461                         cdns,phy-input-delay-mmc-ddr = <3>;
 462                         cdns,phy-dll-delay-sdclk = <21>;
 463                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 464                 };
 465
 466                 usb0: usb@5a800100 {
 467                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 468                         status = "disabled";
 469                         reg = <0x5a800100 0x100>;
 470                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 471                         pinctrl-names = "default";
 472                         pinctrl-0 = <&pinctrl_usb0>;
 473                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 474                                  <&mio_clk 12>;
 475                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 476                                  <&mio_rst 12>;
 477                         phy-names = "usb";
 478                         phys = <&usb_phy0>;
 479                         has-transaction-translator;
 480                 };
 481
 482                 usb1: usb@5a810100 {
 483                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 484                         status = "disabled";
 485                         reg = <0x5a810100 0x100>;
 486                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 487                         pinctrl-names = "default";
 488                         pinctrl-0 = <&pinctrl_usb1>;
 489                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 490                                  <&mio_clk 13>;
 491                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 492                                  <&mio_rst 13>;
 493                         phy-names = "usb";
 494                         phys = <&usb_phy1>;
 495                         has-transaction-translator;
 496                 };
 497
 498                 usb2: usb@5a820100 {
 499                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 500                         status = "disabled";
 501                         reg = <0x5a820100 0x100>;
 502                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
 503                         pinctrl-names = "default";
 504                         pinctrl-0 = <&pinctrl_usb2>;
 505                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 506                                  <&mio_clk 14>;
 507                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 508                                  <&mio_rst 14>;
 509                         phy-names = "usb";
 510                         phys = <&usb_phy2>;
 511                         has-transaction-translator;
 512                 };
 513
 514                 mioctrl@5b3e0000 {
 515                         compatible = "socionext,uniphier-ld11-mioctrl",
 516                                      "simple-mfd", "syscon";
 517                         reg = <0x5b3e0000 0x800>;
 518
 519                         mio_clk: clock {
 520                                 compatible = "socionext,uniphier-ld11-mio-clock";
 521                                 #clock-cells = <1>;
 522                         };
 523
 524                         mio_rst: reset {
 525                                 compatible = "socionext,uniphier-ld11-mio-reset";
 526                                 #reset-cells = <1>;
 527                                 resets = <&sys_rst 7>;
 528                         };
 529                 };
 530
 531                 soc_glue: soc-glue@5f800000 {
 532                         compatible = "socionext,uniphier-ld11-soc-glue",
 533                                      "simple-mfd", "syscon";
 534                         reg = <0x5f800000 0x2000>;
 535
 536                         pinctrl: pinctrl {
 537                                 compatible = "socionext,uniphier-ld11-pinctrl";
 538                         };
 539
 540                         usb-controller {
 541                                 compatible = "socionext,uniphier-ld11-usb2-phy";
 542                                 #address-cells = <1>;
 543                                 #size-cells = <0>;
 544
 545                                 usb_phy0: phy@0 {
 546                                         reg = <0>;
 547                                         #phy-cells = <0>;
 548                                 };
 549
 550                                 usb_phy1: phy@1 {
 551                                         reg = <1>;
 552                                         #phy-cells = <0>;
 553                                 };
 554
 555                                 usb_phy2: phy@2 {
 556                                         reg = <2>;
 557                                         #phy-cells = <0>;
 558                                 };
 559                         };
 560                 };
 561
 562                 soc-glue@5f900000 {
 563                         compatible = "socionext,uniphier-ld11-soc-glue-debug",
 564                                      "simple-mfd";
 565                         #address-cells = <1>;
 566                         #size-cells = <1>;
 567                         ranges = <0 0x5f900000 0x2000>;
 568
 569                         efuse@100 {
 570                                 compatible = "socionext,uniphier-efuse";
 571                                 reg = <0x100 0x28>;
 572                         };
 573
 574                         efuse@200 {
 575                                 compatible = "socionext,uniphier-efuse";
 576                                 reg = <0x200 0x68>;
 577                         };
 578                 };
 579
 580                 xdmac: dma-controller@5fc10000 {
 581                         compatible = "socionext,uniphier-xdmac";
 582                         reg = <0x5fc10000 0x5300>;
 583                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 584                         dma-channels = <16>;
 585                         #dma-cells = <2>;
 586                 };
 587
 588                 aidet: interrupt-controller@5fc20000 {
 589                         compatible = "socionext,uniphier-ld11-aidet";
 590                         reg = <0x5fc20000 0x200>;
 591                         interrupt-controller;
 592                         #interrupt-cells = <2>;
 593                 };
 594
 595                 gic: interrupt-controller@5fe00000 {
 596                         compatible = "arm,gic-v3";
 597                         reg = <0x5fe00000 0x10000>,     /* GICD */
 598                               <0x5fe40000 0x80000>;     /* GICR */
 599                         interrupt-controller;
 600                         #interrupt-cells = <3>;
 601                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 602                 };
 603
 604                 sysctrl@61840000 {
 605                         compatible = "socionext,uniphier-ld11-sysctrl",
 606                                      "simple-mfd", "syscon";
 607                         reg = <0x61840000 0x10000>;
 608
 609                         sys_clk: clock {
 610                                 compatible = "socionext,uniphier-ld11-clock";
 611                                 #clock-cells = <1>;
 612                         };
 613
 614                         sys_rst: reset {
 615                                 compatible = "socionext,uniphier-ld11-reset";
 616                                 #reset-cells = <1>;
 617                         };
 618
 619                         watchdog {
 620                                 compatible = "socionext,uniphier-wdt";
 621                         };
 622                 };
 623
 624                 eth: ethernet@65000000 {
 625                         compatible = "socionext,uniphier-ld11-ave4";
 626                         status = "disabled";
 627                         reg = <0x65000000 0x8500>;
 628                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 629                         clock-names = "ether";
 630                         clocks = <&sys_clk 6>;
 631                         reset-names = "ether";
 632                         resets = <&sys_rst 6>;
 633                         phy-mode = "internal";
 634                         local-mac-address = [00 00 00 00 00 00];
 635                         socionext,syscon-phy-mode = <&soc_glue 0>;
 636
 637                         mdio: mdio {
 638                                 #address-cells = <1>;
 639                                 #size-cells = <0>;
 640                         };
 641                 };
 642
 643                 nand: nand-controller@68000000 {
 644                         compatible = "socionext,uniphier-denali-nand-v5b";
 645                         status = "disabled";
 646                         reg-names = "nand_data", "denali_reg";
 647                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 648                         #address-cells = <1>;
 649                         #size-cells = <0>;
 650                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 651                         pinctrl-names = "default";
 652                         pinctrl-0 = <&pinctrl_nand>;
 653                         clock-names = "nand", "nand_x", "ecc";
 654                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 655                         reset-names = "nand", "reg";
 656                         resets = <&sys_rst 2>, <&sys_rst 2>;
 657                 };
 658         };
 659 };
 660
 661 #include "uniphier-pinctrl.dtsi"
 662
 663 &pinctrl_aoutiec1 {
 664         drive-strength = <4>;   /* default: 4mA */
 665
 666         ao1arc {
 667                 pins = "AO1ARC";
 668                 drive-strength = <8>;   /* 8mA */
 669         };
 670 };