1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
15 compatible = "rockchip,rk3588";
17 interrupt-parent = <&gic>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 capacity-dmips-mhz = <530>;
64 clocks = <&scmi_clk SCMI_CLK_CPUL>;
65 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
66 assigned-clock-rates = <816000000>;
67 cpu-idle-states = <&CPU_SLEEP>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
74 next-level-cache = <&l2_cache_l0>;
75 dynamic-power-coefficient = <228>;
81 compatible = "arm,cortex-a55";
83 enable-method = "psci";
84 capacity-dmips-mhz = <530>;
85 clocks = <&scmi_clk SCMI_CLK_CPUL>;
86 cpu-idle-states = <&CPU_SLEEP>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
93 next-level-cache = <&l2_cache_l1>;
94 dynamic-power-coefficient = <228>;
100 compatible = "arm,cortex-a55";
102 enable-method = "psci";
103 capacity-dmips-mhz = <530>;
104 clocks = <&scmi_clk SCMI_CLK_CPUL>;
105 cpu-idle-states = <&CPU_SLEEP>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_cache_l2>;
113 dynamic-power-coefficient = <228>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a55";
121 enable-method = "psci";
122 capacity-dmips-mhz = <530>;
123 clocks = <&scmi_clk SCMI_CLK_CPUL>;
124 cpu-idle-states = <&CPU_SLEEP>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_cache_l3>;
132 dynamic-power-coefficient = <228>;
133 #cooling-cells = <2>;
138 compatible = "arm,cortex-a76";
140 enable-method = "psci";
141 capacity-dmips-mhz = <1024>;
142 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
143 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
144 assigned-clock-rates = <816000000>;
145 cpu-idle-states = <&CPU_SLEEP>;
146 i-cache-size = <65536>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <65536>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&l2_cache_b0>;
153 dynamic-power-coefficient = <416>;
154 #cooling-cells = <2>;
159 compatible = "arm,cortex-a76";
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
163 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
164 cpu-idle-states = <&CPU_SLEEP>;
165 i-cache-size = <65536>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <65536>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 next-level-cache = <&l2_cache_b1>;
172 dynamic-power-coefficient = <416>;
173 #cooling-cells = <2>;
178 compatible = "arm,cortex-a76";
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
182 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
183 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
184 assigned-clock-rates = <816000000>;
185 cpu-idle-states = <&CPU_SLEEP>;
186 i-cache-size = <65536>;
187 i-cache-line-size = <64>;
188 i-cache-sets = <256>;
189 d-cache-size = <65536>;
190 d-cache-line-size = <64>;
191 d-cache-sets = <256>;
192 next-level-cache = <&l2_cache_b2>;
193 dynamic-power-coefficient = <416>;
194 #cooling-cells = <2>;
199 compatible = "arm,cortex-a76";
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
204 cpu-idle-states = <&CPU_SLEEP>;
205 i-cache-size = <65536>;
206 i-cache-line-size = <64>;
207 i-cache-sets = <256>;
208 d-cache-size = <65536>;
209 d-cache-line-size = <64>;
210 d-cache-sets = <256>;
211 next-level-cache = <&l2_cache_b3>;
212 dynamic-power-coefficient = <416>;
213 #cooling-cells = <2>;
217 entry-method = "psci";
218 CPU_SLEEP: cpu-sleep {
219 compatible = "arm,idle-state";
221 arm,psci-suspend-param = <0x0010000>;
222 entry-latency-us = <100>;
223 exit-latency-us = <120>;
224 min-residency-us = <1000>;
228 l2_cache_l0: l2-cache-l0 {
229 compatible = "cache";
230 cache-size = <131072>;
231 cache-line-size = <64>;
235 next-level-cache = <&l3_cache>;
238 l2_cache_l1: l2-cache-l1 {
239 compatible = "cache";
240 cache-size = <131072>;
241 cache-line-size = <64>;
245 next-level-cache = <&l3_cache>;
248 l2_cache_l2: l2-cache-l2 {
249 compatible = "cache";
250 cache-size = <131072>;
251 cache-line-size = <64>;
255 next-level-cache = <&l3_cache>;
258 l2_cache_l3: l2-cache-l3 {
259 compatible = "cache";
260 cache-size = <131072>;
261 cache-line-size = <64>;
265 next-level-cache = <&l3_cache>;
268 l2_cache_b0: l2-cache-b0 {
269 compatible = "cache";
270 cache-size = <524288>;
271 cache-line-size = <64>;
275 next-level-cache = <&l3_cache>;
278 l2_cache_b1: l2-cache-b1 {
279 compatible = "cache";
280 cache-size = <524288>;
281 cache-line-size = <64>;
285 next-level-cache = <&l3_cache>;
288 l2_cache_b2: l2-cache-b2 {
289 compatible = "cache";
290 cache-size = <524288>;
291 cache-line-size = <64>;
295 next-level-cache = <&l3_cache>;
298 l2_cache_b3: l2-cache-b3 {
299 compatible = "cache";
300 cache-size = <524288>;
301 cache-line-size = <64>;
305 next-level-cache = <&l3_cache>;
309 compatible = "cache";
310 cache-size = <3145728>;
311 cache-line-size = <64>;
320 compatible = "linaro,optee-tz";
325 compatible = "arm,scmi-smc";
326 arm,smc-id = <0x82000010>;
327 shmem = <&scmi_shmem>;
328 #address-cells = <1>;
331 scmi_clk: protocol@14 {
336 scmi_reset: protocol@16 {
344 compatible = "arm,cortex-a55-pmu";
345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
349 compatible = "arm,cortex-a76-pmu";
350 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
354 compatible = "arm,psci-1.0";
359 compatible = "fixed-clock";
360 clock-frequency = <702000000>;
361 clock-output-names = "spll";
366 compatible = "arm,armv8-timer";
367 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
368 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
369 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
370 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
371 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
372 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
376 compatible = "fixed-clock";
377 clock-frequency = <24000000>;
378 clock-output-names = "xin24m";
383 compatible = "fixed-clock";
384 clock-frequency = <32768>;
385 clock-output-names = "xin32k";
389 pmu_sram: sram@10f000 {
390 compatible = "mmio-sram";
391 reg = <0x0 0x0010f000 0x0 0x100>;
392 ranges = <0 0x0 0x0010f000 0x100>;
393 #address-cells = <1>;
397 compatible = "arm,scmi-shmem";
402 usb_host0_ehci: usb@fc800000 {
403 compatible = "rockchip,rk3588-ehci", "generic-ehci";
404 reg = <0x0 0xfc800000 0x0 0x40000>;
405 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
407 phys = <&u2phy2_host>;
409 power-domains = <&power RK3588_PD_USB>;
413 usb_host0_ohci: usb@fc840000 {
414 compatible = "rockchip,rk3588-ohci", "generic-ohci";
415 reg = <0x0 0xfc840000 0x0 0x40000>;
416 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
418 phys = <&u2phy2_host>;
420 power-domains = <&power RK3588_PD_USB>;
424 usb_host1_ehci: usb@fc880000 {
425 compatible = "rockchip,rk3588-ehci", "generic-ehci";
426 reg = <0x0 0xfc880000 0x0 0x40000>;
427 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
429 phys = <&u2phy3_host>;
431 power-domains = <&power RK3588_PD_USB>;
435 usb_host1_ohci: usb@fc8c0000 {
436 compatible = "rockchip,rk3588-ohci", "generic-ohci";
437 reg = <0x0 0xfc8c0000 0x0 0x40000>;
438 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
440 phys = <&u2phy3_host>;
442 power-domains = <&power RK3588_PD_USB>;
446 usb_host2_xhci: usb@fcd00000 {
447 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
448 reg = <0x0 0xfcd00000 0x0 0x400000>;
449 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
450 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
451 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
452 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
453 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
455 phys = <&combphy2_psu PHY_TYPE_USB3>;
456 phy-names = "usb3-phy";
457 phy_type = "utmi_wide";
458 resets = <&cru SRST_A_USB3OTG2>;
459 snps,dis_enblslpm_quirk;
460 snps,dis-u2-freeclk-exists-quirk;
461 snps,dis-del-phy-power-chg-quirk;
462 snps,dis-tx-ipgap-linecheck-quirk;
463 snps,dis_rxdet_inp3_quirk;
467 pmu1grf: syscon@fd58a000 {
468 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
469 reg = <0x0 0xfd58a000 0x0 0x10000>;
472 sys_grf: syscon@fd58c000 {
473 compatible = "rockchip,rk3588-sys-grf", "syscon";
474 reg = <0x0 0xfd58c000 0x0 0x1000>;
477 php_grf: syscon@fd5b0000 {
478 compatible = "rockchip,rk3588-php-grf", "syscon";
479 reg = <0x0 0xfd5b0000 0x0 0x1000>;
482 pipe_phy0_grf: syscon@fd5bc000 {
483 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
484 reg = <0x0 0xfd5bc000 0x0 0x100>;
487 pipe_phy2_grf: syscon@fd5c4000 {
488 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
489 reg = <0x0 0xfd5c4000 0x0 0x100>;
492 usb2phy2_grf: syscon@fd5d8000 {
493 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
494 reg = <0x0 0xfd5d8000 0x0 0x4000>;
495 #address-cells = <1>;
498 u2phy2: usb2-phy@8000 {
499 compatible = "rockchip,rk3588-usb2phy";
501 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
502 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
503 reset-names = "phy", "apb";
504 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
505 clock-names = "phyclk";
506 clock-output-names = "usb480m_phy2";
510 u2phy2_host: host-port {
517 usb2phy3_grf: syscon@fd5dc000 {
518 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
519 reg = <0x0 0xfd5dc000 0x0 0x4000>;
520 #address-cells = <1>;
523 u2phy3: usb2-phy@c000 {
524 compatible = "rockchip,rk3588-usb2phy";
526 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
527 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
528 reset-names = "phy", "apb";
529 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
530 clock-names = "phyclk";
531 clock-output-names = "usb480m_phy3";
535 u2phy3_host: host-port {
542 ioc: syscon@fd5f0000 {
543 compatible = "rockchip,rk3588-ioc", "syscon";
544 reg = <0x0 0xfd5f0000 0x0 0x10000>;
547 system_sram1: sram@fd600000 {
548 compatible = "mmio-sram";
549 reg = <0x0 0xfd600000 0x0 0x100000>;
550 ranges = <0x0 0x0 0xfd600000 0x100000>;
551 #address-cells = <1>;
555 cru: clock-controller@fd7c0000 {
556 compatible = "rockchip,rk3588-cru";
557 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
559 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
560 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
561 <&cru ACLK_CENTER_ROOT>,
562 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
563 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
564 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
565 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
566 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
568 assigned-clock-rates =
569 <1100000000>, <786432000>,
570 <850000000>, <1188000000>,
572 <400000000>, <500000000>,
573 <800000000>, <100000000>,
574 <400000000>, <100000000>,
575 <200000000>, <500000000>,
576 <375000000>, <150000000>,
578 rockchip,grf = <&php_grf>;
584 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
585 reg = <0x0 0xfd880000 0x0 0x1000>;
586 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
587 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
588 clock-names = "i2c", "pclk";
589 pinctrl-0 = <&i2c0m0_xfer>;
590 pinctrl-names = "default";
591 #address-cells = <1>;
596 uart0: serial@fd890000 {
597 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xfd890000 0x0 0x100>;
599 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
600 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
601 clock-names = "baudclk", "apb_pclk";
602 dmas = <&dmac0 6>, <&dmac0 7>;
603 dma-names = "tx", "rx";
604 pinctrl-0 = <&uart0m1_xfer>;
605 pinctrl-names = "default";
612 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
613 reg = <0x0 0xfd8b0000 0x0 0x10>;
614 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
615 clock-names = "pwm", "pclk";
616 pinctrl-0 = <&pwm0m0_pins>;
617 pinctrl-names = "default";
623 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
624 reg = <0x0 0xfd8b0010 0x0 0x10>;
625 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
626 clock-names = "pwm", "pclk";
627 pinctrl-0 = <&pwm1m0_pins>;
628 pinctrl-names = "default";
634 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
635 reg = <0x0 0xfd8b0020 0x0 0x10>;
636 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
637 clock-names = "pwm", "pclk";
638 pinctrl-0 = <&pwm2m0_pins>;
639 pinctrl-names = "default";
645 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
646 reg = <0x0 0xfd8b0030 0x0 0x10>;
647 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
648 clock-names = "pwm", "pclk";
649 pinctrl-0 = <&pwm3m0_pins>;
650 pinctrl-names = "default";
655 pmu: power-management@fd8d8000 {
656 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
657 reg = <0x0 0xfd8d8000 0x0 0x400>;
659 power: power-controller {
660 compatible = "rockchip,rk3588-power-controller";
661 #address-cells = <1>;
662 #power-domain-cells = <1>;
666 /* These power domains are grouped by VD_NPU */
667 power-domain@RK3588_PD_NPU {
668 reg = <RK3588_PD_NPU>;
669 #power-domain-cells = <0>;
670 #address-cells = <1>;
673 power-domain@RK3588_PD_NPUTOP {
674 reg = <RK3588_PD_NPUTOP>;
675 clocks = <&cru HCLK_NPU_ROOT>,
676 <&cru PCLK_NPU_ROOT>,
678 <&cru HCLK_NPU_CM0_ROOT>;
679 pm_qos = <&qos_npu0_mwr>,
682 #power-domain-cells = <0>;
683 #address-cells = <1>;
686 power-domain@RK3588_PD_NPU1 {
687 reg = <RK3588_PD_NPU1>;
688 clocks = <&cru HCLK_NPU_ROOT>,
689 <&cru PCLK_NPU_ROOT>,
691 pm_qos = <&qos_npu1>;
692 #power-domain-cells = <0>;
694 power-domain@RK3588_PD_NPU2 {
695 reg = <RK3588_PD_NPU2>;
696 clocks = <&cru HCLK_NPU_ROOT>,
697 <&cru PCLK_NPU_ROOT>,
699 pm_qos = <&qos_npu2>;
700 #power-domain-cells = <0>;
704 /* These power domains are grouped by VD_GPU */
705 power-domain@RK3588_PD_GPU {
706 reg = <RK3588_PD_GPU>;
707 clocks = <&cru CLK_GPU>,
708 <&cru CLK_GPU_COREGROUP>,
709 <&cru CLK_GPU_STACKS>;
710 pm_qos = <&qos_gpu_m0>,
714 #power-domain-cells = <0>;
716 /* These power domains are grouped by VD_VCODEC */
717 power-domain@RK3588_PD_VCODEC {
718 reg = <RK3588_PD_VCODEC>;
719 #address-cells = <1>;
721 #power-domain-cells = <0>;
723 power-domain@RK3588_PD_RKVDEC0 {
724 reg = <RK3588_PD_RKVDEC0>;
725 clocks = <&cru HCLK_RKVDEC0>,
726 <&cru HCLK_VDPU_ROOT>,
727 <&cru ACLK_VDPU_ROOT>,
729 <&cru ACLK_RKVDEC_CCU>;
730 pm_qos = <&qos_rkvdec0>;
731 #power-domain-cells = <0>;
733 power-domain@RK3588_PD_RKVDEC1 {
734 reg = <RK3588_PD_RKVDEC1>;
735 clocks = <&cru HCLK_RKVDEC1>,
736 <&cru HCLK_VDPU_ROOT>,
737 <&cru ACLK_VDPU_ROOT>,
739 pm_qos = <&qos_rkvdec1>;
740 #power-domain-cells = <0>;
742 power-domain@RK3588_PD_VENC0 {
743 reg = <RK3588_PD_VENC0>;
744 clocks = <&cru HCLK_RKVENC0>,
746 pm_qos = <&qos_rkvenc0_m0ro>,
749 #address-cells = <1>;
751 #power-domain-cells = <0>;
753 power-domain@RK3588_PD_VENC1 {
754 reg = <RK3588_PD_VENC1>;
755 clocks = <&cru HCLK_RKVENC1>,
759 pm_qos = <&qos_rkvenc1_m0ro>,
762 #power-domain-cells = <0>;
766 /* These power domains are grouped by VD_LOGIC */
767 power-domain@RK3588_PD_VDPU {
768 reg = <RK3588_PD_VDPU>;
769 clocks = <&cru HCLK_VDPU_ROOT>,
770 <&cru ACLK_VDPU_LOW_ROOT>,
771 <&cru ACLK_VDPU_ROOT>,
772 <&cru ACLK_JPEG_DECODER_ROOT>,
775 <&cru ACLK_JPEG_ENCODER0>,
776 <&cru HCLK_JPEG_ENCODER0>,
777 <&cru ACLK_JPEG_ENCODER1>,
778 <&cru HCLK_JPEG_ENCODER1>,
779 <&cru ACLK_JPEG_ENCODER2>,
780 <&cru HCLK_JPEG_ENCODER2>,
781 <&cru ACLK_JPEG_ENCODER3>,
782 <&cru HCLK_JPEG_ENCODER3>,
783 <&cru ACLK_JPEG_DECODER>,
784 <&cru HCLK_JPEG_DECODER>,
795 #address-cells = <1>;
797 #power-domain-cells = <0>;
800 power-domain@RK3588_PD_AV1 {
801 reg = <RK3588_PD_AV1>;
802 clocks = <&cru PCLK_AV1>,
804 <&cru HCLK_VDPU_ROOT>;
806 #power-domain-cells = <0>;
808 power-domain@RK3588_PD_RKVDEC0 {
809 reg = <RK3588_PD_RKVDEC0>;
810 clocks = <&cru HCLK_RKVDEC0>,
811 <&cru HCLK_VDPU_ROOT>,
812 <&cru ACLK_VDPU_ROOT>,
814 pm_qos = <&qos_rkvdec0>;
815 #power-domain-cells = <0>;
817 power-domain@RK3588_PD_RKVDEC1 {
818 reg = <RK3588_PD_RKVDEC1>;
819 clocks = <&cru HCLK_RKVDEC1>,
820 <&cru HCLK_VDPU_ROOT>,
821 <&cru ACLK_VDPU_ROOT>;
822 pm_qos = <&qos_rkvdec1>;
823 #power-domain-cells = <0>;
825 power-domain@RK3588_PD_RGA30 {
826 reg = <RK3588_PD_RGA30>;
827 clocks = <&cru ACLK_RGA3_0>,
829 pm_qos = <&qos_rga3_0>;
830 #power-domain-cells = <0>;
833 power-domain@RK3588_PD_VOP {
834 reg = <RK3588_PD_VOP>;
835 clocks = <&cru PCLK_VOP_ROOT>,
836 <&cru HCLK_VOP_ROOT>,
838 pm_qos = <&qos_vop_m0>,
840 #address-cells = <1>;
842 #power-domain-cells = <0>;
844 power-domain@RK3588_PD_VO0 {
845 reg = <RK3588_PD_VO0>;
846 clocks = <&cru PCLK_VO0_ROOT>,
847 <&cru PCLK_VO0_S_ROOT>,
848 <&cru HCLK_VO0_S_ROOT>,
849 <&cru ACLK_VO0_ROOT>,
852 <&cru HCLK_VOP_ROOT>;
853 pm_qos = <&qos_hdcp0>;
854 #power-domain-cells = <0>;
857 power-domain@RK3588_PD_VO1 {
858 reg = <RK3588_PD_VO1>;
859 clocks = <&cru PCLK_VO1_ROOT>,
860 <&cru PCLK_VO1_S_ROOT>,
861 <&cru HCLK_VO1_S_ROOT>,
864 <&cru ACLK_HDMIRX_ROOT>,
865 <&cru HCLK_VO1USB_TOP_ROOT>;
866 pm_qos = <&qos_hdcp1>,
868 #power-domain-cells = <0>;
870 power-domain@RK3588_PD_VI {
871 reg = <RK3588_PD_VI>;
872 clocks = <&cru HCLK_VI_ROOT>,
878 pm_qos = <&qos_isp0_mro>,
882 #address-cells = <1>;
884 #power-domain-cells = <0>;
886 power-domain@RK3588_PD_ISP1 {
887 reg = <RK3588_PD_ISP1>;
888 clocks = <&cru HCLK_ISP1>,
892 pm_qos = <&qos_isp1_mwo>,
894 #power-domain-cells = <0>;
896 power-domain@RK3588_PD_FEC {
897 reg = <RK3588_PD_FEC>;
898 clocks = <&cru HCLK_FISHEYE0>,
899 <&cru ACLK_FISHEYE0>,
900 <&cru HCLK_FISHEYE1>,
901 <&cru ACLK_FISHEYE1>,
903 pm_qos = <&qos_fisheye0>,
905 #power-domain-cells = <0>;
908 power-domain@RK3588_PD_RGA31 {
909 reg = <RK3588_PD_RGA31>;
910 clocks = <&cru HCLK_RGA3_1>,
912 pm_qos = <&qos_rga3_1>;
913 #power-domain-cells = <0>;
915 power-domain@RK3588_PD_USB {
916 reg = <RK3588_PD_USB>;
917 clocks = <&cru PCLK_PHP_ROOT>,
918 <&cru ACLK_USB_ROOT>,
919 <&cru HCLK_USB_ROOT>,
921 <&cru HCLK_HOST_ARB0>,
923 <&cru HCLK_HOST_ARB1>;
924 pm_qos = <&qos_usb3_0>,
928 #power-domain-cells = <0>;
930 power-domain@RK3588_PD_GMAC {
931 reg = <RK3588_PD_GMAC>;
932 clocks = <&cru PCLK_PHP_ROOT>,
933 <&cru ACLK_PCIE_ROOT>,
934 <&cru ACLK_PHP_ROOT>;
935 #power-domain-cells = <0>;
937 power-domain@RK3588_PD_PCIE {
938 reg = <RK3588_PD_PCIE>;
939 clocks = <&cru PCLK_PHP_ROOT>,
940 <&cru ACLK_PCIE_ROOT>,
941 <&cru ACLK_PHP_ROOT>;
942 #power-domain-cells = <0>;
944 power-domain@RK3588_PD_SDIO {
945 reg = <RK3588_PD_SDIO>;
946 clocks = <&cru HCLK_SDIO>,
947 <&cru HCLK_NVM_ROOT>;
948 pm_qos = <&qos_sdio>;
949 #power-domain-cells = <0>;
951 power-domain@RK3588_PD_AUDIO {
952 reg = <RK3588_PD_AUDIO>;
953 clocks = <&cru HCLK_AUDIO_ROOT>,
954 <&cru PCLK_AUDIO_ROOT>;
955 #power-domain-cells = <0>;
957 power-domain@RK3588_PD_SDMMC {
958 reg = <RK3588_PD_SDMMC>;
959 pm_qos = <&qos_sdmmc>;
960 #power-domain-cells = <0>;
965 i2s4_8ch: i2s@fddc0000 {
966 compatible = "rockchip,rk3588-i2s-tdm";
967 reg = <0x0 0xfddc0000 0x0 0x1000>;
968 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
969 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
970 clock-names = "mclk_tx", "mclk_rx", "hclk";
971 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
972 assigned-clock-parents = <&cru PLL_AUPLL>;
975 power-domains = <&power RK3588_PD_VO0>;
976 resets = <&cru SRST_M_I2S4_8CH_TX>;
977 reset-names = "tx-m";
978 #sound-dai-cells = <0>;
982 i2s5_8ch: i2s@fddf0000 {
983 compatible = "rockchip,rk3588-i2s-tdm";
984 reg = <0x0 0xfddf0000 0x0 0x1000>;
985 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
986 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
987 clock-names = "mclk_tx", "mclk_rx", "hclk";
988 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
989 assigned-clock-parents = <&cru PLL_AUPLL>;
992 power-domains = <&power RK3588_PD_VO1>;
993 resets = <&cru SRST_M_I2S5_8CH_TX>;
994 reset-names = "tx-m";
995 #sound-dai-cells = <0>;
999 i2s9_8ch: i2s@fddfc000 {
1000 compatible = "rockchip,rk3588-i2s-tdm";
1001 reg = <0x0 0xfddfc000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1003 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1004 clock-names = "mclk_tx", "mclk_rx", "hclk";
1005 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1006 assigned-clock-parents = <&cru PLL_AUPLL>;
1009 power-domains = <&power RK3588_PD_VO1>;
1010 resets = <&cru SRST_M_I2S9_8CH_RX>;
1011 reset-names = "rx-m";
1012 #sound-dai-cells = <0>;
1013 status = "disabled";
1016 qos_gpu_m0: qos@fdf35000 {
1017 compatible = "rockchip,rk3588-qos", "syscon";
1018 reg = <0x0 0xfdf35000 0x0 0x20>;
1021 qos_gpu_m1: qos@fdf35200 {
1022 compatible = "rockchip,rk3588-qos", "syscon";
1023 reg = <0x0 0xfdf35200 0x0 0x20>;
1026 qos_gpu_m2: qos@fdf35400 {
1027 compatible = "rockchip,rk3588-qos", "syscon";
1028 reg = <0x0 0xfdf35400 0x0 0x20>;
1031 qos_gpu_m3: qos@fdf35600 {
1032 compatible = "rockchip,rk3588-qos", "syscon";
1033 reg = <0x0 0xfdf35600 0x0 0x20>;
1036 qos_rga3_1: qos@fdf36000 {
1037 compatible = "rockchip,rk3588-qos", "syscon";
1038 reg = <0x0 0xfdf36000 0x0 0x20>;
1041 qos_sdio: qos@fdf39000 {
1042 compatible = "rockchip,rk3588-qos", "syscon";
1043 reg = <0x0 0xfdf39000 0x0 0x20>;
1046 qos_sdmmc: qos@fdf3d800 {
1047 compatible = "rockchip,rk3588-qos", "syscon";
1048 reg = <0x0 0xfdf3d800 0x0 0x20>;
1051 qos_usb3_1: qos@fdf3e000 {
1052 compatible = "rockchip,rk3588-qos", "syscon";
1053 reg = <0x0 0xfdf3e000 0x0 0x20>;
1056 qos_usb3_0: qos@fdf3e200 {
1057 compatible = "rockchip,rk3588-qos", "syscon";
1058 reg = <0x0 0xfdf3e200 0x0 0x20>;
1061 qos_usb2host_0: qos@fdf3e400 {
1062 compatible = "rockchip,rk3588-qos", "syscon";
1063 reg = <0x0 0xfdf3e400 0x0 0x20>;
1066 qos_usb2host_1: qos@fdf3e600 {
1067 compatible = "rockchip,rk3588-qos", "syscon";
1068 reg = <0x0 0xfdf3e600 0x0 0x20>;
1071 qos_fisheye0: qos@fdf40000 {
1072 compatible = "rockchip,rk3588-qos", "syscon";
1073 reg = <0x0 0xfdf40000 0x0 0x20>;
1076 qos_fisheye1: qos@fdf40200 {
1077 compatible = "rockchip,rk3588-qos", "syscon";
1078 reg = <0x0 0xfdf40200 0x0 0x20>;
1081 qos_isp0_mro: qos@fdf40400 {
1082 compatible = "rockchip,rk3588-qos", "syscon";
1083 reg = <0x0 0xfdf40400 0x0 0x20>;
1086 qos_isp0_mwo: qos@fdf40500 {
1087 compatible = "rockchip,rk3588-qos", "syscon";
1088 reg = <0x0 0xfdf40500 0x0 0x20>;
1091 qos_vicap_m0: qos@fdf40600 {
1092 compatible = "rockchip,rk3588-qos", "syscon";
1093 reg = <0x0 0xfdf40600 0x0 0x20>;
1096 qos_vicap_m1: qos@fdf40800 {
1097 compatible = "rockchip,rk3588-qos", "syscon";
1098 reg = <0x0 0xfdf40800 0x0 0x20>;
1101 qos_isp1_mwo: qos@fdf41000 {
1102 compatible = "rockchip,rk3588-qos", "syscon";
1103 reg = <0x0 0xfdf41000 0x0 0x20>;
1106 qos_isp1_mro: qos@fdf41100 {
1107 compatible = "rockchip,rk3588-qos", "syscon";
1108 reg = <0x0 0xfdf41100 0x0 0x20>;
1111 qos_rkvenc0_m0ro: qos@fdf60000 {
1112 compatible = "rockchip,rk3588-qos", "syscon";
1113 reg = <0x0 0xfdf60000 0x0 0x20>;
1116 qos_rkvenc0_m1ro: qos@fdf60200 {
1117 compatible = "rockchip,rk3588-qos", "syscon";
1118 reg = <0x0 0xfdf60200 0x0 0x20>;
1121 qos_rkvenc0_m2wo: qos@fdf60400 {
1122 compatible = "rockchip,rk3588-qos", "syscon";
1123 reg = <0x0 0xfdf60400 0x0 0x20>;
1126 qos_rkvenc1_m0ro: qos@fdf61000 {
1127 compatible = "rockchip,rk3588-qos", "syscon";
1128 reg = <0x0 0xfdf61000 0x0 0x20>;
1131 qos_rkvenc1_m1ro: qos@fdf61200 {
1132 compatible = "rockchip,rk3588-qos", "syscon";
1133 reg = <0x0 0xfdf61200 0x0 0x20>;
1136 qos_rkvenc1_m2wo: qos@fdf61400 {
1137 compatible = "rockchip,rk3588-qos", "syscon";
1138 reg = <0x0 0xfdf61400 0x0 0x20>;
1141 qos_rkvdec0: qos@fdf62000 {
1142 compatible = "rockchip,rk3588-qos", "syscon";
1143 reg = <0x0 0xfdf62000 0x0 0x20>;
1146 qos_rkvdec1: qos@fdf63000 {
1147 compatible = "rockchip,rk3588-qos", "syscon";
1148 reg = <0x0 0xfdf63000 0x0 0x20>;
1151 qos_av1: qos@fdf64000 {
1152 compatible = "rockchip,rk3588-qos", "syscon";
1153 reg = <0x0 0xfdf64000 0x0 0x20>;
1156 qos_iep: qos@fdf66000 {
1157 compatible = "rockchip,rk3588-qos", "syscon";
1158 reg = <0x0 0xfdf66000 0x0 0x20>;
1161 qos_jpeg_dec: qos@fdf66200 {
1162 compatible = "rockchip,rk3588-qos", "syscon";
1163 reg = <0x0 0xfdf66200 0x0 0x20>;
1166 qos_jpeg_enc0: qos@fdf66400 {
1167 compatible = "rockchip,rk3588-qos", "syscon";
1168 reg = <0x0 0xfdf66400 0x0 0x20>;
1171 qos_jpeg_enc1: qos@fdf66600 {
1172 compatible = "rockchip,rk3588-qos", "syscon";
1173 reg = <0x0 0xfdf66600 0x0 0x20>;
1176 qos_jpeg_enc2: qos@fdf66800 {
1177 compatible = "rockchip,rk3588-qos", "syscon";
1178 reg = <0x0 0xfdf66800 0x0 0x20>;
1181 qos_jpeg_enc3: qos@fdf66a00 {
1182 compatible = "rockchip,rk3588-qos", "syscon";
1183 reg = <0x0 0xfdf66a00 0x0 0x20>;
1186 qos_rga2_mro: qos@fdf66c00 {
1187 compatible = "rockchip,rk3588-qos", "syscon";
1188 reg = <0x0 0xfdf66c00 0x0 0x20>;
1191 qos_rga2_mwo: qos@fdf66e00 {
1192 compatible = "rockchip,rk3588-qos", "syscon";
1193 reg = <0x0 0xfdf66e00 0x0 0x20>;
1196 qos_rga3_0: qos@fdf67000 {
1197 compatible = "rockchip,rk3588-qos", "syscon";
1198 reg = <0x0 0xfdf67000 0x0 0x20>;
1201 qos_vdpu: qos@fdf67200 {
1202 compatible = "rockchip,rk3588-qos", "syscon";
1203 reg = <0x0 0xfdf67200 0x0 0x20>;
1206 qos_npu1: qos@fdf70000 {
1207 compatible = "rockchip,rk3588-qos", "syscon";
1208 reg = <0x0 0xfdf70000 0x0 0x20>;
1211 qos_npu2: qos@fdf71000 {
1212 compatible = "rockchip,rk3588-qos", "syscon";
1213 reg = <0x0 0xfdf71000 0x0 0x20>;
1216 qos_npu0_mwr: qos@fdf72000 {
1217 compatible = "rockchip,rk3588-qos", "syscon";
1218 reg = <0x0 0xfdf72000 0x0 0x20>;
1221 qos_npu0_mro: qos@fdf72200 {
1222 compatible = "rockchip,rk3588-qos", "syscon";
1223 reg = <0x0 0xfdf72200 0x0 0x20>;
1226 qos_mcu_npu: qos@fdf72400 {
1227 compatible = "rockchip,rk3588-qos", "syscon";
1228 reg = <0x0 0xfdf72400 0x0 0x20>;
1231 qos_hdcp0: qos@fdf80000 {
1232 compatible = "rockchip,rk3588-qos", "syscon";
1233 reg = <0x0 0xfdf80000 0x0 0x20>;
1236 qos_hdcp1: qos@fdf81000 {
1237 compatible = "rockchip,rk3588-qos", "syscon";
1238 reg = <0x0 0xfdf81000 0x0 0x20>;
1241 qos_hdmirx: qos@fdf81200 {
1242 compatible = "rockchip,rk3588-qos", "syscon";
1243 reg = <0x0 0xfdf81200 0x0 0x20>;
1246 qos_vop_m0: qos@fdf82000 {
1247 compatible = "rockchip,rk3588-qos", "syscon";
1248 reg = <0x0 0xfdf82000 0x0 0x20>;
1251 qos_vop_m1: qos@fdf82200 {
1252 compatible = "rockchip,rk3588-qos", "syscon";
1253 reg = <0x0 0xfdf82200 0x0 0x20>;
1256 pcie2x1l1: pcie@fe180000 {
1257 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1258 bus-range = <0x30 0x3f>;
1259 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1260 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1261 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1262 clock-names = "aclk_mst", "aclk_slv",
1265 device_type = "pci";
1266 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1267 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1268 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1269 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1270 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1271 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1272 #interrupt-cells = <1>;
1273 interrupt-map-mask = <0 0 0 7>;
1274 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1275 <0 0 0 2 &pcie2x1l1_intc 1>,
1276 <0 0 0 3 &pcie2x1l1_intc 2>,
1277 <0 0 0 4 &pcie2x1l1_intc 3>;
1278 linux,pci-domain = <3>;
1279 max-link-speed = <2>;
1280 msi-map = <0x3000 &its0 0x3000 0x1000>;
1282 phys = <&combphy2_psu PHY_TYPE_PCIE>;
1283 phy-names = "pcie-phy";
1284 power-domains = <&power RK3588_PD_PCIE>;
1285 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1286 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1287 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1288 reg = <0xa 0x40c00000 0x0 0x00400000>,
1289 <0x0 0xfe180000 0x0 0x00010000>,
1290 <0x0 0xf3000000 0x0 0x00100000>;
1291 reg-names = "dbi", "apb", "config";
1292 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1293 reset-names = "pwr", "pipe";
1294 #address-cells = <3>;
1296 status = "disabled";
1298 pcie2x1l1_intc: legacy-interrupt-controller {
1299 interrupt-controller;
1300 #address-cells = <0>;
1301 #interrupt-cells = <1>;
1302 interrupt-parent = <&gic>;
1303 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1307 pcie2x1l2: pcie@fe190000 {
1308 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1309 bus-range = <0x40 0x4f>;
1310 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1311 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1312 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1313 clock-names = "aclk_mst", "aclk_slv",
1316 device_type = "pci";
1317 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1318 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1319 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1320 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1321 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1322 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1323 #interrupt-cells = <1>;
1324 interrupt-map-mask = <0 0 0 7>;
1325 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1326 <0 0 0 2 &pcie2x1l2_intc 1>,
1327 <0 0 0 3 &pcie2x1l2_intc 2>,
1328 <0 0 0 4 &pcie2x1l2_intc 3>;
1329 linux,pci-domain = <4>;
1330 max-link-speed = <2>;
1331 msi-map = <0x4000 &its0 0x4000 0x1000>;
1333 phys = <&combphy0_ps PHY_TYPE_PCIE>;
1334 phy-names = "pcie-phy";
1335 power-domains = <&power RK3588_PD_PCIE>;
1336 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1337 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1338 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1339 reg = <0xa 0x41000000 0x0 0x00400000>,
1340 <0x0 0xfe190000 0x0 0x00010000>,
1341 <0x0 0xf4000000 0x0 0x00100000>;
1342 reg-names = "dbi", "apb", "config";
1343 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1344 reset-names = "pwr", "pipe";
1345 #address-cells = <3>;
1347 status = "disabled";
1349 pcie2x1l2_intc: legacy-interrupt-controller {
1350 interrupt-controller;
1351 #address-cells = <0>;
1352 #interrupt-cells = <1>;
1353 interrupt-parent = <&gic>;
1354 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1359 reg = <0x00 0xfe060000 0x00 0x10000>;
1360 compatible = "rockchip,rk3588-dfi";
1361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1362 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1363 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1364 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1365 rockchip,pmu = <&pmu1grf>;
1368 gmac1: ethernet@fe1c0000 {
1369 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1370 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1371 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1372 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1373 interrupt-names = "macirq", "eth_wake_irq";
1374 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1375 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1376 <&cru CLK_GMAC1_PTP_REF>;
1377 clock-names = "stmmaceth", "clk_mac_ref",
1378 "pclk_mac", "aclk_mac",
1380 power-domains = <&power RK3588_PD_GMAC>;
1381 resets = <&cru SRST_A_GMAC1>;
1382 reset-names = "stmmaceth";
1383 rockchip,grf = <&sys_grf>;
1384 rockchip,php-grf = <&php_grf>;
1385 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1387 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1388 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1390 status = "disabled";
1393 compatible = "snps,dwmac-mdio";
1394 #address-cells = <0x1>;
1395 #size-cells = <0x0>;
1398 gmac1_stmmac_axi_setup: stmmac-axi-config {
1399 snps,blen = <0 0 0 0 16 8 4>;
1400 snps,wr_osr_lmt = <4>;
1401 snps,rd_osr_lmt = <8>;
1404 gmac1_mtl_rx_setup: rx-queues-config {
1405 snps,rx-queues-to-use = <2>;
1410 gmac1_mtl_tx_setup: tx-queues-config {
1411 snps,tx-queues-to-use = <2>;
1417 sata0: sata@fe210000 {
1418 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1419 reg = <0 0xfe210000 0 0x1000>;
1420 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1421 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1422 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1423 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1424 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1425 ports-implemented = <0x1>;
1426 #address-cells = <1>;
1428 status = "disabled";
1432 hba-port-cap = <HBA_PORT_FBSCP>;
1433 phys = <&combphy0_ps PHY_TYPE_SATA>;
1434 phy-names = "sata-phy";
1435 snps,rx-ts-max = <32>;
1436 snps,tx-ts-max = <32>;
1440 sata2: sata@fe230000 {
1441 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1442 reg = <0 0xfe230000 0 0x1000>;
1443 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1444 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1445 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1446 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1447 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1448 ports-implemented = <0x1>;
1449 #address-cells = <1>;
1451 status = "disabled";
1455 hba-port-cap = <HBA_PORT_FBSCP>;
1456 phys = <&combphy2_psu PHY_TYPE_SATA>;
1457 phy-names = "sata-phy";
1458 snps,rx-ts-max = <32>;
1459 snps,tx-ts-max = <32>;
1464 compatible = "rockchip,sfc";
1465 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1466 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1467 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1468 clock-names = "clk_sfc", "hclk_sfc";
1469 #address-cells = <1>;
1471 status = "disabled";
1474 sdmmc: mmc@fe2c0000 {
1475 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1476 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1477 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1478 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1479 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1480 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1481 fifo-depth = <0x100>;
1482 max-frequency = <200000000>;
1483 pinctrl-names = "default";
1484 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1485 power-domains = <&power RK3588_PD_SDMMC>;
1486 status = "disabled";
1489 sdio: mmc@fe2d0000 {
1490 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1491 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1492 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1493 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1494 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1495 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1496 fifo-depth = <0x100>;
1497 max-frequency = <200000000>;
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&sdiom1_pins>;
1500 power-domains = <&power RK3588_PD_SDIO>;
1501 status = "disabled";
1504 sdhci: mmc@fe2e0000 {
1505 compatible = "rockchip,rk3588-dwcmshc";
1506 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1507 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1508 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1509 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1510 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1511 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1513 clock-names = "core", "bus", "axi", "block", "timer";
1514 max-frequency = <200000000>;
1515 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1516 <&emmc_cmd>, <&emmc_data_strobe>;
1517 pinctrl-names = "default";
1518 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1519 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1521 reset-names = "core", "bus", "axi", "block", "timer";
1522 status = "disabled";
1525 i2s0_8ch: i2s@fe470000 {
1526 compatible = "rockchip,rk3588-i2s-tdm";
1527 reg = <0x0 0xfe470000 0x0 0x1000>;
1528 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1529 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1530 clock-names = "mclk_tx", "mclk_rx", "hclk";
1531 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1532 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1533 dmas = <&dmac0 0>, <&dmac0 1>;
1534 dma-names = "tx", "rx";
1535 power-domains = <&power RK3588_PD_AUDIO>;
1536 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1537 reset-names = "tx-m", "rx-m";
1538 rockchip,trcm-sync-tx-only;
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&i2s0_lrck
1550 #sound-dai-cells = <0>;
1551 status = "disabled";
1554 i2s1_8ch: i2s@fe480000 {
1555 compatible = "rockchip,rk3588-i2s-tdm";
1556 reg = <0x0 0xfe480000 0x0 0x1000>;
1557 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1558 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1559 clock-names = "mclk_tx", "mclk_rx", "hclk";
1560 dmas = <&dmac0 2>, <&dmac0 3>;
1561 dma-names = "tx", "rx";
1562 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1563 reset-names = "tx-m", "rx-m";
1564 rockchip,trcm-sync-tx-only;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&i2s1m0_lrck
1576 #sound-dai-cells = <0>;
1577 status = "disabled";
1580 i2s2_2ch: i2s@fe490000 {
1581 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1582 reg = <0x0 0xfe490000 0x0 0x1000>;
1583 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1584 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1585 clock-names = "i2s_clk", "i2s_hclk";
1586 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1587 assigned-clock-parents = <&cru PLL_AUPLL>;
1588 dmas = <&dmac1 0>, <&dmac1 1>;
1589 dma-names = "tx", "rx";
1590 power-domains = <&power RK3588_PD_AUDIO>;
1591 rockchip,trcm-sync-tx-only;
1592 pinctrl-names = "default";
1593 pinctrl-0 = <&i2s2m1_lrck
1597 #sound-dai-cells = <0>;
1598 status = "disabled";
1601 i2s3_2ch: i2s@fe4a0000 {
1602 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1603 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1604 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1605 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1606 clock-names = "i2s_clk", "i2s_hclk";
1607 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1608 assigned-clock-parents = <&cru PLL_AUPLL>;
1609 dmas = <&dmac1 2>, <&dmac1 3>;
1610 dma-names = "tx", "rx";
1611 power-domains = <&power RK3588_PD_AUDIO>;
1612 rockchip,trcm-sync-tx-only;
1613 pinctrl-names = "default";
1614 pinctrl-0 = <&i2s3_lrck
1618 #sound-dai-cells = <0>;
1619 status = "disabled";
1622 gic: interrupt-controller@fe600000 {
1623 compatible = "arm,gic-v3";
1624 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1625 <0x0 0xfe680000 0 0x100000>; /* GICR */
1626 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1627 interrupt-controller;
1628 mbi-alias = <0x0 0xfe610000>;
1629 mbi-ranges = <424 56>;
1632 #address-cells = <2>;
1633 #interrupt-cells = <4>;
1636 its0: msi-controller@fe640000 {
1637 compatible = "arm,gic-v3-its";
1638 reg = <0x0 0xfe640000 0x0 0x20000>;
1643 its1: msi-controller@fe660000 {
1644 compatible = "arm,gic-v3-its";
1645 reg = <0x0 0xfe660000 0x0 0x20000>;
1651 ppi_partition0: interrupt-partition-0 {
1652 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1655 ppi_partition1: interrupt-partition-1 {
1656 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1661 dmac0: dma-controller@fea10000 {
1662 compatible = "arm,pl330", "arm,primecell";
1663 reg = <0x0 0xfea10000 0x0 0x4000>;
1664 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1665 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1666 arm,pl330-periph-burst;
1667 clocks = <&cru ACLK_DMAC0>;
1668 clock-names = "apb_pclk";
1672 dmac1: dma-controller@fea30000 {
1673 compatible = "arm,pl330", "arm,primecell";
1674 reg = <0x0 0xfea30000 0x0 0x4000>;
1675 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1676 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1677 arm,pl330-periph-burst;
1678 clocks = <&cru ACLK_DMAC1>;
1679 clock-names = "apb_pclk";
1683 i2c1: i2c@fea90000 {
1684 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1685 reg = <0x0 0xfea90000 0x0 0x1000>;
1686 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1687 clock-names = "i2c", "pclk";
1688 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1689 pinctrl-0 = <&i2c1m0_xfer>;
1690 pinctrl-names = "default";
1691 #address-cells = <1>;
1693 status = "disabled";
1696 i2c2: i2c@feaa0000 {
1697 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1698 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1699 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1700 clock-names = "i2c", "pclk";
1701 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1702 pinctrl-0 = <&i2c2m0_xfer>;
1703 pinctrl-names = "default";
1704 #address-cells = <1>;
1706 status = "disabled";
1709 i2c3: i2c@feab0000 {
1710 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1711 reg = <0x0 0xfeab0000 0x0 0x1000>;
1712 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1713 clock-names = "i2c", "pclk";
1714 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1715 pinctrl-0 = <&i2c3m0_xfer>;
1716 pinctrl-names = "default";
1717 #address-cells = <1>;
1719 status = "disabled";
1722 i2c4: i2c@feac0000 {
1723 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1724 reg = <0x0 0xfeac0000 0x0 0x1000>;
1725 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1726 clock-names = "i2c", "pclk";
1727 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1728 pinctrl-0 = <&i2c4m0_xfer>;
1729 pinctrl-names = "default";
1730 #address-cells = <1>;
1732 status = "disabled";
1735 i2c5: i2c@fead0000 {
1736 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1737 reg = <0x0 0xfead0000 0x0 0x1000>;
1738 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1739 clock-names = "i2c", "pclk";
1740 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1741 pinctrl-0 = <&i2c5m0_xfer>;
1742 pinctrl-names = "default";
1743 #address-cells = <1>;
1745 status = "disabled";
1748 timer0: timer@feae0000 {
1749 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1750 reg = <0x0 0xfeae0000 0x0 0x20>;
1751 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1752 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1753 clock-names = "pclk", "timer";
1756 wdt: watchdog@feaf0000 {
1757 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1758 reg = <0x0 0xfeaf0000 0x0 0x100>;
1759 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1760 clock-names = "tclk", "pclk";
1761 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1764 spi0: spi@feb00000 {
1765 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1766 reg = <0x0 0xfeb00000 0x0 0x1000>;
1767 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1768 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1769 clock-names = "spiclk", "apb_pclk";
1770 dmas = <&dmac0 14>, <&dmac0 15>;
1771 dma-names = "tx", "rx";
1773 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1774 pinctrl-names = "default";
1775 #address-cells = <1>;
1777 status = "disabled";
1780 spi1: spi@feb10000 {
1781 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1782 reg = <0x0 0xfeb10000 0x0 0x1000>;
1783 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1784 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1785 clock-names = "spiclk", "apb_pclk";
1786 dmas = <&dmac0 16>, <&dmac0 17>;
1787 dma-names = "tx", "rx";
1789 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1790 pinctrl-names = "default";
1791 #address-cells = <1>;
1793 status = "disabled";
1796 spi2: spi@feb20000 {
1797 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1798 reg = <0x0 0xfeb20000 0x0 0x1000>;
1799 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1800 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1801 clock-names = "spiclk", "apb_pclk";
1802 dmas = <&dmac1 15>, <&dmac1 16>;
1803 dma-names = "tx", "rx";
1805 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1806 pinctrl-names = "default";
1807 #address-cells = <1>;
1809 status = "disabled";
1812 spi3: spi@feb30000 {
1813 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1814 reg = <0x0 0xfeb30000 0x0 0x1000>;
1815 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1816 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1817 clock-names = "spiclk", "apb_pclk";
1818 dmas = <&dmac1 17>, <&dmac1 18>;
1819 dma-names = "tx", "rx";
1821 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1822 pinctrl-names = "default";
1823 #address-cells = <1>;
1825 status = "disabled";
1828 uart1: serial@feb40000 {
1829 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1830 reg = <0x0 0xfeb40000 0x0 0x100>;
1831 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1832 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1833 clock-names = "baudclk", "apb_pclk";
1834 dmas = <&dmac0 8>, <&dmac0 9>;
1835 dma-names = "tx", "rx";
1836 pinctrl-0 = <&uart1m1_xfer>;
1837 pinctrl-names = "default";
1840 status = "disabled";
1843 uart2: serial@feb50000 {
1844 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1845 reg = <0x0 0xfeb50000 0x0 0x100>;
1846 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1847 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1848 clock-names = "baudclk", "apb_pclk";
1849 dmas = <&dmac0 10>, <&dmac0 11>;
1850 dma-names = "tx", "rx";
1851 pinctrl-0 = <&uart2m1_xfer>;
1852 pinctrl-names = "default";
1855 status = "disabled";
1858 uart3: serial@feb60000 {
1859 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1860 reg = <0x0 0xfeb60000 0x0 0x100>;
1861 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1862 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1863 clock-names = "baudclk", "apb_pclk";
1864 dmas = <&dmac0 12>, <&dmac0 13>;
1865 dma-names = "tx", "rx";
1866 pinctrl-0 = <&uart3m1_xfer>;
1867 pinctrl-names = "default";
1870 status = "disabled";
1873 uart4: serial@feb70000 {
1874 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1875 reg = <0x0 0xfeb70000 0x0 0x100>;
1876 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1877 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1878 clock-names = "baudclk", "apb_pclk";
1879 dmas = <&dmac1 9>, <&dmac1 10>;
1880 dma-names = "tx", "rx";
1881 pinctrl-0 = <&uart4m1_xfer>;
1882 pinctrl-names = "default";
1885 status = "disabled";
1888 uart5: serial@feb80000 {
1889 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1890 reg = <0x0 0xfeb80000 0x0 0x100>;
1891 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1892 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1893 clock-names = "baudclk", "apb_pclk";
1894 dmas = <&dmac1 11>, <&dmac1 12>;
1895 dma-names = "tx", "rx";
1896 pinctrl-0 = <&uart5m1_xfer>;
1897 pinctrl-names = "default";
1900 status = "disabled";
1903 uart6: serial@feb90000 {
1904 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1905 reg = <0x0 0xfeb90000 0x0 0x100>;
1906 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1907 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1908 clock-names = "baudclk", "apb_pclk";
1909 dmas = <&dmac1 13>, <&dmac1 14>;
1910 dma-names = "tx", "rx";
1911 pinctrl-0 = <&uart6m1_xfer>;
1912 pinctrl-names = "default";
1915 status = "disabled";
1918 uart7: serial@feba0000 {
1919 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1920 reg = <0x0 0xfeba0000 0x0 0x100>;
1921 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1922 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1923 clock-names = "baudclk", "apb_pclk";
1924 dmas = <&dmac2 7>, <&dmac2 8>;
1925 dma-names = "tx", "rx";
1926 pinctrl-0 = <&uart7m1_xfer>;
1927 pinctrl-names = "default";
1930 status = "disabled";
1933 uart8: serial@febb0000 {
1934 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1935 reg = <0x0 0xfebb0000 0x0 0x100>;
1936 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1937 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1938 clock-names = "baudclk", "apb_pclk";
1939 dmas = <&dmac2 9>, <&dmac2 10>;
1940 dma-names = "tx", "rx";
1941 pinctrl-0 = <&uart8m1_xfer>;
1942 pinctrl-names = "default";
1945 status = "disabled";
1948 uart9: serial@febc0000 {
1949 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1950 reg = <0x0 0xfebc0000 0x0 0x100>;
1951 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1952 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1953 clock-names = "baudclk", "apb_pclk";
1954 dmas = <&dmac2 11>, <&dmac2 12>;
1955 dma-names = "tx", "rx";
1956 pinctrl-0 = <&uart9m1_xfer>;
1957 pinctrl-names = "default";
1960 status = "disabled";
1963 pwm4: pwm@febd0000 {
1964 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1965 reg = <0x0 0xfebd0000 0x0 0x10>;
1966 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1967 clock-names = "pwm", "pclk";
1968 pinctrl-0 = <&pwm4m0_pins>;
1969 pinctrl-names = "default";
1971 status = "disabled";
1974 pwm5: pwm@febd0010 {
1975 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1976 reg = <0x0 0xfebd0010 0x0 0x10>;
1977 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1978 clock-names = "pwm", "pclk";
1979 pinctrl-0 = <&pwm5m0_pins>;
1980 pinctrl-names = "default";
1982 status = "disabled";
1985 pwm6: pwm@febd0020 {
1986 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1987 reg = <0x0 0xfebd0020 0x0 0x10>;
1988 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1989 clock-names = "pwm", "pclk";
1990 pinctrl-0 = <&pwm6m0_pins>;
1991 pinctrl-names = "default";
1993 status = "disabled";
1996 pwm7: pwm@febd0030 {
1997 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1998 reg = <0x0 0xfebd0030 0x0 0x10>;
1999 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2000 clock-names = "pwm", "pclk";
2001 pinctrl-0 = <&pwm7m0_pins>;
2002 pinctrl-names = "default";
2004 status = "disabled";
2007 pwm8: pwm@febe0000 {
2008 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2009 reg = <0x0 0xfebe0000 0x0 0x10>;
2010 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2011 clock-names = "pwm", "pclk";
2012 pinctrl-0 = <&pwm8m0_pins>;
2013 pinctrl-names = "default";
2015 status = "disabled";
2018 pwm9: pwm@febe0010 {
2019 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2020 reg = <0x0 0xfebe0010 0x0 0x10>;
2021 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2022 clock-names = "pwm", "pclk";
2023 pinctrl-0 = <&pwm9m0_pins>;
2024 pinctrl-names = "default";
2026 status = "disabled";
2029 pwm10: pwm@febe0020 {
2030 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2031 reg = <0x0 0xfebe0020 0x0 0x10>;
2032 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2033 clock-names = "pwm", "pclk";
2034 pinctrl-0 = <&pwm10m0_pins>;
2035 pinctrl-names = "default";
2037 status = "disabled";
2040 pwm11: pwm@febe0030 {
2041 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2042 reg = <0x0 0xfebe0030 0x0 0x10>;
2043 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2044 clock-names = "pwm", "pclk";
2045 pinctrl-0 = <&pwm11m0_pins>;
2046 pinctrl-names = "default";
2048 status = "disabled";
2051 pwm12: pwm@febf0000 {
2052 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2053 reg = <0x0 0xfebf0000 0x0 0x10>;
2054 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2055 clock-names = "pwm", "pclk";
2056 pinctrl-0 = <&pwm12m0_pins>;
2057 pinctrl-names = "default";
2059 status = "disabled";
2062 pwm13: pwm@febf0010 {
2063 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2064 reg = <0x0 0xfebf0010 0x0 0x10>;
2065 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2066 clock-names = "pwm", "pclk";
2067 pinctrl-0 = <&pwm13m0_pins>;
2068 pinctrl-names = "default";
2070 status = "disabled";
2073 pwm14: pwm@febf0020 {
2074 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2075 reg = <0x0 0xfebf0020 0x0 0x10>;
2076 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2077 clock-names = "pwm", "pclk";
2078 pinctrl-0 = <&pwm14m0_pins>;
2079 pinctrl-names = "default";
2081 status = "disabled";
2084 pwm15: pwm@febf0030 {
2085 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2086 reg = <0x0 0xfebf0030 0x0 0x10>;
2087 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2088 clock-names = "pwm", "pclk";
2089 pinctrl-0 = <&pwm15m0_pins>;
2090 pinctrl-names = "default";
2092 status = "disabled";
2095 tsadc: tsadc@fec00000 {
2096 compatible = "rockchip,rk3588-tsadc";
2097 reg = <0x0 0xfec00000 0x0 0x400>;
2098 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2099 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2100 clock-names = "tsadc", "apb_pclk";
2101 assigned-clocks = <&cru CLK_TSADC>;
2102 assigned-clock-rates = <2000000>;
2103 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2104 reset-names = "tsadc-apb", "tsadc";
2105 rockchip,hw-tshut-temp = <120000>;
2106 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2107 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2108 pinctrl-0 = <&tsadc_gpio_func>;
2109 pinctrl-1 = <&tsadc_shut>;
2110 pinctrl-names = "gpio", "otpout";
2111 #thermal-sensor-cells = <1>;
2112 status = "disabled";
2115 saradc: adc@fec10000 {
2116 compatible = "rockchip,rk3588-saradc";
2117 reg = <0x0 0xfec10000 0x0 0x10000>;
2118 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2119 #io-channel-cells = <1>;
2120 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2121 clock-names = "saradc", "apb_pclk";
2122 resets = <&cru SRST_P_SARADC>;
2123 reset-names = "saradc-apb";
2124 status = "disabled";
2127 i2c6: i2c@fec80000 {
2128 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2129 reg = <0x0 0xfec80000 0x0 0x1000>;
2130 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2131 clock-names = "i2c", "pclk";
2132 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2133 pinctrl-0 = <&i2c6m0_xfer>;
2134 pinctrl-names = "default";
2135 #address-cells = <1>;
2137 status = "disabled";
2140 i2c7: i2c@fec90000 {
2141 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2142 reg = <0x0 0xfec90000 0x0 0x1000>;
2143 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2144 clock-names = "i2c", "pclk";
2145 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2146 pinctrl-0 = <&i2c7m0_xfer>;
2147 pinctrl-names = "default";
2148 #address-cells = <1>;
2150 status = "disabled";
2153 i2c8: i2c@feca0000 {
2154 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2155 reg = <0x0 0xfeca0000 0x0 0x1000>;
2156 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2157 clock-names = "i2c", "pclk";
2158 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2159 pinctrl-0 = <&i2c8m0_xfer>;
2160 pinctrl-names = "default";
2161 #address-cells = <1>;
2163 status = "disabled";
2166 spi4: spi@fecb0000 {
2167 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2168 reg = <0x0 0xfecb0000 0x0 0x1000>;
2169 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2170 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2171 clock-names = "spiclk", "apb_pclk";
2172 dmas = <&dmac2 13>, <&dmac2 14>;
2173 dma-names = "tx", "rx";
2175 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2176 pinctrl-names = "default";
2177 #address-cells = <1>;
2179 status = "disabled";
2182 otp: efuse@fecc0000 {
2183 compatible = "rockchip,rk3588-otp";
2184 reg = <0x0 0xfecc0000 0x0 0x400>;
2185 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2186 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2187 clock-names = "otp", "apb_pclk", "phy", "arb";
2188 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2189 <&cru SRST_OTPC_ARB>;
2190 reset-names = "otp", "apb", "arb";
2191 #address-cells = <1>;
2194 cpu_code: cpu-code@2 {
2202 cpub0_leakage: cpu-leakage@17 {
2206 cpub1_leakage: cpu-leakage@18 {
2210 cpul_leakage: cpu-leakage@19 {
2214 log_leakage: log-leakage@1a {
2218 gpu_leakage: gpu-leakage@1b {
2222 otp_cpu_version: cpu-version@1c {
2227 npu_leakage: npu-leakage@28 {
2231 codec_leakage: codec-leakage@29 {
2236 dmac2: dma-controller@fed10000 {
2237 compatible = "arm,pl330", "arm,primecell";
2238 reg = <0x0 0xfed10000 0x0 0x4000>;
2239 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2240 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2241 arm,pl330-periph-burst;
2242 clocks = <&cru ACLK_DMAC2>;
2243 clock-names = "apb_pclk";
2247 combphy0_ps: phy@fee00000 {
2248 compatible = "rockchip,rk3588-naneng-combphy";
2249 reg = <0x0 0xfee00000 0x0 0x100>;
2250 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2251 <&cru PCLK_PHP_ROOT>;
2252 clock-names = "ref", "apb", "pipe";
2253 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2254 assigned-clock-rates = <100000000>;
2256 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2257 reset-names = "phy", "apb";
2258 rockchip,pipe-grf = <&php_grf>;
2259 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2260 status = "disabled";
2263 combphy2_psu: phy@fee20000 {
2264 compatible = "rockchip,rk3588-naneng-combphy";
2265 reg = <0x0 0xfee20000 0x0 0x100>;
2266 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2267 <&cru PCLK_PHP_ROOT>;
2268 clock-names = "ref", "apb", "pipe";
2269 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2270 assigned-clock-rates = <100000000>;
2272 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2273 reset-names = "phy", "apb";
2274 rockchip,pipe-grf = <&php_grf>;
2275 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2276 status = "disabled";
2279 system_sram2: sram@ff001000 {
2280 compatible = "mmio-sram";
2281 reg = <0x0 0xff001000 0x0 0xef000>;
2282 ranges = <0x0 0x0 0xff001000 0xef000>;
2283 #address-cells = <1>;
2288 compatible = "rockchip,rk3588-pinctrl";
2290 rockchip,grf = <&ioc>;
2291 #address-cells = <2>;
2294 gpio0: gpio@fd8a0000 {
2295 compatible = "rockchip,gpio-bank";
2296 reg = <0x0 0xfd8a0000 0x0 0x100>;
2297 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2298 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2300 gpio-ranges = <&pinctrl 0 0 32>;
2301 interrupt-controller;
2303 #interrupt-cells = <2>;
2306 gpio1: gpio@fec20000 {
2307 compatible = "rockchip,gpio-bank";
2308 reg = <0x0 0xfec20000 0x0 0x100>;
2309 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2310 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2312 gpio-ranges = <&pinctrl 0 32 32>;
2313 interrupt-controller;
2315 #interrupt-cells = <2>;
2318 gpio2: gpio@fec30000 {
2319 compatible = "rockchip,gpio-bank";
2320 reg = <0x0 0xfec30000 0x0 0x100>;
2321 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2322 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2324 gpio-ranges = <&pinctrl 0 64 32>;
2325 interrupt-controller;
2327 #interrupt-cells = <2>;
2330 gpio3: gpio@fec40000 {
2331 compatible = "rockchip,gpio-bank";
2332 reg = <0x0 0xfec40000 0x0 0x100>;
2333 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2334 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2336 gpio-ranges = <&pinctrl 0 96 32>;
2337 interrupt-controller;
2339 #interrupt-cells = <2>;
2342 gpio4: gpio@fec50000 {
2343 compatible = "rockchip,gpio-bank";
2344 reg = <0x0 0xfec50000 0x0 0x100>;
2345 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2346 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2348 gpio-ranges = <&pinctrl 0 128 32>;
2349 interrupt-controller;
2351 #interrupt-cells = <2>;
2355 av1d: video-codec@fdc70000 {
2356 compatible = "rockchip,rk3588-av1-vpu";
2357 reg = <0x0 0xfdc70000 0x0 0x800>;
2358 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
2359 interrupt-names = "vdpu";
2360 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2361 assigned-clock-rates = <400000000>, <400000000>;
2362 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2363 clock-names = "aclk", "hclk";
2364 power-domains = <&power RK3588_PD_AV1>;
2365 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
2369 #include "rk3588s-pinctrl.dtsi"