1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
16 auddsm_pins: auddsm-pins {
19 <3 RK_PA1 4 &pcfg_pull_none>,
21 <3 RK_PA2 4 &pcfg_pull_none>,
23 <3 RK_PA3 4 &pcfg_pull_none>,
25 <3 RK_PA4 4 &pcfg_pull_none>;
31 bt1120_pins: bt1120-pins {
34 <4 RK_PB0 2 &pcfg_pull_none>,
36 <4 RK_PA0 2 &pcfg_pull_none>,
38 <4 RK_PA1 2 &pcfg_pull_none>,
40 <4 RK_PA2 2 &pcfg_pull_none>,
42 <4 RK_PA3 2 &pcfg_pull_none>,
44 <4 RK_PA4 2 &pcfg_pull_none>,
46 <4 RK_PA5 2 &pcfg_pull_none>,
48 <4 RK_PA6 2 &pcfg_pull_none>,
50 <4 RK_PA7 2 &pcfg_pull_none>,
52 <4 RK_PB2 2 &pcfg_pull_none>,
54 <4 RK_PB3 2 &pcfg_pull_none>,
56 <4 RK_PB4 2 &pcfg_pull_none>,
58 <4 RK_PB5 2 &pcfg_pull_none>,
60 <4 RK_PB6 2 &pcfg_pull_none>,
62 <4 RK_PB7 2 &pcfg_pull_none>,
64 <4 RK_PC0 2 &pcfg_pull_none>,
66 <4 RK_PC1 2 &pcfg_pull_none>;
72 can0m0_pins: can0m0-pins {
75 <0 RK_PC0 11 &pcfg_pull_none>,
77 <0 RK_PB7 11 &pcfg_pull_none>;
81 can0m1_pins: can0m1-pins {
84 <4 RK_PD5 9 &pcfg_pull_none>,
86 <4 RK_PD4 9 &pcfg_pull_none>;
92 can1m0_pins: can1m0-pins {
95 <3 RK_PB5 9 &pcfg_pull_none>,
97 <3 RK_PB6 9 &pcfg_pull_none>;
101 can1m1_pins: can1m1-pins {
104 <4 RK_PB2 12 &pcfg_pull_none>,
106 <4 RK_PB3 12 &pcfg_pull_none>;
112 can2m0_pins: can2m0-pins {
115 <3 RK_PC4 9 &pcfg_pull_none>,
117 <3 RK_PC5 9 &pcfg_pull_none>;
121 can2m1_pins: can2m1-pins {
124 <0 RK_PD4 10 &pcfg_pull_none>,
126 <0 RK_PD5 10 &pcfg_pull_none>;
135 <4 RK_PB4 1 &pcfg_pull_none>;
139 cif_dvp_clk: cif-dvp-clk {
142 <4 RK_PB0 1 &pcfg_pull_none>,
144 <4 RK_PB2 1 &pcfg_pull_none>,
146 <4 RK_PB3 1 &pcfg_pull_none>;
150 cif_dvp_bus16: cif-dvp-bus16 {
153 <3 RK_PC4 1 &pcfg_pull_none>,
155 <3 RK_PC5 1 &pcfg_pull_none>,
157 <3 RK_PC6 1 &pcfg_pull_none>,
159 <3 RK_PC7 1 &pcfg_pull_none>,
161 <3 RK_PD0 1 &pcfg_pull_none>,
163 <3 RK_PD1 1 &pcfg_pull_none>,
165 <3 RK_PD2 1 &pcfg_pull_none>,
167 <3 RK_PD3 1 &pcfg_pull_none>;
171 cif_dvp_bus8: cif-dvp-bus8 {
174 <4 RK_PA0 1 &pcfg_pull_none>,
176 <4 RK_PA1 1 &pcfg_pull_none>,
178 <4 RK_PA2 1 &pcfg_pull_none>,
180 <4 RK_PA3 1 &pcfg_pull_none>,
182 <4 RK_PA4 1 &pcfg_pull_none>,
184 <4 RK_PA5 1 &pcfg_pull_none>,
186 <4 RK_PA6 1 &pcfg_pull_none>,
188 <4 RK_PA7 1 &pcfg_pull_none>;
194 clk32k_in: clk32k-in {
197 <0 RK_PB2 1 &pcfg_pull_none>;
201 clk32k_out0: clk32k-out0 {
204 <0 RK_PB2 2 &pcfg_pull_none>;
213 <0 RK_PD1 2 &pcfg_pull_none>,
215 <0 RK_PD5 2 &pcfg_pull_none>;
221 ddrphych0_pins: ddrphych0-pins {
224 <4 RK_PA0 7 &pcfg_pull_none>,
226 <4 RK_PA1 7 &pcfg_pull_none>,
228 <4 RK_PA2 7 &pcfg_pull_none>,
230 <4 RK_PA3 7 &pcfg_pull_none>;
236 ddrphych1_pins: ddrphych1-pins {
239 <4 RK_PA4 7 &pcfg_pull_none>,
241 <4 RK_PA5 7 &pcfg_pull_none>,
243 <4 RK_PA6 7 &pcfg_pull_none>,
245 <4 RK_PA7 7 &pcfg_pull_none>;
251 ddrphych2_pins: ddrphych2-pins {
254 <4 RK_PB0 7 &pcfg_pull_none>,
256 <4 RK_PB1 7 &pcfg_pull_none>,
258 <4 RK_PB2 7 &pcfg_pull_none>,
260 <4 RK_PB3 7 &pcfg_pull_none>;
266 ddrphych3_pins: ddrphych3-pins {
269 <4 RK_PB4 7 &pcfg_pull_none>,
271 <4 RK_PB5 7 &pcfg_pull_none>,
273 <4 RK_PB6 7 &pcfg_pull_none>,
275 <4 RK_PB7 7 &pcfg_pull_none>;
281 dp0m0_pins: dp0m0-pins {
284 <4 RK_PB4 5 &pcfg_pull_none>;
288 dp0m1_pins: dp0m1-pins {
291 <0 RK_PC4 10 &pcfg_pull_none>;
295 dp0m2_pins: dp0m2-pins {
298 <1 RK_PA0 5 &pcfg_pull_none>;
304 dp1m0_pins: dp1m0-pins {
307 <3 RK_PD5 5 &pcfg_pull_none>;
311 dp1m1_pins: dp1m1-pins {
314 <0 RK_PC5 10 &pcfg_pull_none>;
318 dp1m2_pins: dp1m2-pins {
321 <1 RK_PA1 5 &pcfg_pull_none>;
327 emmc_rstnout: emmc-rstnout {
330 <2 RK_PA3 1 &pcfg_pull_none>;
334 emmc_bus8: emmc-bus8 {
337 <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
339 <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
341 <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
343 <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
345 <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
347 <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
349 <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
351 <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
358 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
365 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
369 emmc_data_strobe: emmc-data-strobe {
371 /* emmc_data_strobe */
372 <2 RK_PA2 1 &pcfg_pull_down>;
378 eth1_pins: eth1-pins {
380 /* eth1_refclko_25m */
381 <3 RK_PA6 1 &pcfg_pull_none>;
387 fspim0_pins: fspim0-pins {
390 <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
392 <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
394 <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
396 <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
398 <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
400 <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
404 fspim0_cs1: fspim0-cs1 {
407 <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
411 fspim2_pins: fspim2-pins {
414 <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
416 <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
418 <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
420 <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
422 <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
424 <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
428 fspim2_cs1: fspim2-cs1 {
431 <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
437 gmac1_miim: gmac1-miim {
440 <3 RK_PC2 1 &pcfg_pull_none>,
442 <3 RK_PC3 1 &pcfg_pull_none>;
446 gmac1_clkinout: gmac1-clkinout {
448 /* gmac1_mclkinout */
449 <3 RK_PB6 1 &pcfg_pull_none>;
453 gmac1_rx_bus2: gmac1-rx-bus2 {
456 <3 RK_PA7 1 &pcfg_pull_none>,
458 <3 RK_PB0 1 &pcfg_pull_none>,
460 <3 RK_PB1 1 &pcfg_pull_none>;
464 gmac1_tx_bus2: gmac1-tx-bus2 {
467 <3 RK_PB3 1 &pcfg_pull_none>,
469 <3 RK_PB4 1 &pcfg_pull_none>,
471 <3 RK_PB5 1 &pcfg_pull_none>;
475 gmac1_rgmii_clk: gmac1-rgmii-clk {
478 <3 RK_PA5 1 &pcfg_pull_none>,
480 <3 RK_PA4 1 &pcfg_pull_none>;
484 gmac1_rgmii_bus: gmac1-rgmii-bus {
487 <3 RK_PA2 1 &pcfg_pull_none>,
489 <3 RK_PA3 1 &pcfg_pull_none>,
491 <3 RK_PA0 1 &pcfg_pull_none>,
493 <3 RK_PA1 1 &pcfg_pull_none>;
497 gmac1_ppsclk: gmac1-ppsclk {
500 <3 RK_PC1 1 &pcfg_pull_none>;
504 gmac1_ppstrig: gmac1-ppstrig {
507 <3 RK_PC0 1 &pcfg_pull_none>;
511 gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
513 /* gmac1_ptp_ref_clk */
514 <3 RK_PB7 1 &pcfg_pull_none>;
518 gmac1_txer: gmac1-txer {
521 <3 RK_PB2 1 &pcfg_pull_none>;
530 <0 RK_PC5 2 &pcfg_pull_none>;
536 hdmim0_rx_cec: hdmim0-rx-cec {
539 <4 RK_PB5 5 &pcfg_pull_none>;
543 hdmim0_rx_hpdin: hdmim0-rx-hpdin {
545 /* hdmim0_rx_hpdin */
546 <4 RK_PB6 5 &pcfg_pull_none>;
550 hdmim0_rx_scl: hdmim0-rx-scl {
553 <0 RK_PD2 11 &pcfg_pull_none>;
557 hdmim0_rx_sda: hdmim0-rx-sda {
560 <0 RK_PD1 11 &pcfg_pull_none>;
564 hdmim0_tx0_cec: hdmim0-tx0-cec {
567 <4 RK_PC1 5 &pcfg_pull_none>;
571 hdmim0_tx0_hpd: hdmim0-tx0-hpd {
574 <1 RK_PA5 5 &pcfg_pull_none>;
578 hdmim0_tx0_scl: hdmim0-tx0-scl {
581 <4 RK_PB7 5 &pcfg_pull_none>;
585 hdmim0_tx0_sda: hdmim0-tx0-sda {
588 <4 RK_PC0 5 &pcfg_pull_none>;
592 hdmim0_tx1_hpd: hdmim0-tx1-hpd {
595 <1 RK_PA6 5 &pcfg_pull_none>;
598 hdmim1_rx_cec: hdmim1-rx-cec {
601 <3 RK_PD1 5 &pcfg_pull_none>;
605 hdmim1_rx_hpdin: hdmim1-rx-hpdin {
607 /* hdmim1_rx_hpdin */
608 <3 RK_PD4 5 &pcfg_pull_none>;
612 hdmim1_rx_scl: hdmim1-rx-scl {
615 <3 RK_PD2 5 &pcfg_pull_none>;
619 hdmim1_rx_sda: hdmim1-rx-sda {
622 <3 RK_PD3 5 &pcfg_pull_none>;
626 hdmim1_tx0_cec: hdmim1-tx0-cec {
629 <0 RK_PD1 13 &pcfg_pull_none>;
633 hdmim1_tx0_hpd: hdmim1-tx0-hpd {
636 <3 RK_PD4 3 &pcfg_pull_none>;
640 hdmim1_tx0_scl: hdmim1-tx0-scl {
643 <0 RK_PD5 11 &pcfg_pull_none>;
647 hdmim1_tx0_sda: hdmim1-tx0-sda {
650 <0 RK_PD4 11 &pcfg_pull_none>;
654 hdmim1_tx1_cec: hdmim1-tx1-cec {
657 <0 RK_PD2 13 &pcfg_pull_none>;
661 hdmim1_tx1_hpd: hdmim1-tx1-hpd {
664 <3 RK_PB7 5 &pcfg_pull_none>;
668 hdmim1_tx1_scl: hdmim1-tx1-scl {
671 <3 RK_PC6 5 &pcfg_pull_none>;
675 hdmim1_tx1_sda: hdmim1-tx1-sda {
678 <3 RK_PC5 5 &pcfg_pull_none>;
681 hdmim2_rx_cec: hdmim2-rx-cec {
684 <1 RK_PB7 5 &pcfg_pull_none>;
688 hdmim2_rx_hpdin: hdmim2-rx-hpdin {
690 /* hdmim2_rx_hpdin */
691 <1 RK_PB6 5 &pcfg_pull_none>;
695 hdmim2_rx_scl: hdmim2-rx-scl {
698 <1 RK_PD6 5 &pcfg_pull_none>;
702 hdmim2_rx_sda: hdmim2-rx-sda {
705 <1 RK_PD7 5 &pcfg_pull_none>;
709 hdmim2_tx0_scl: hdmim2-tx0-scl {
712 <3 RK_PC7 5 &pcfg_pull_none>;
716 hdmim2_tx0_sda: hdmim2-tx0-sda {
719 <3 RK_PD0 5 &pcfg_pull_none>;
723 hdmim2_tx1_cec: hdmim2-tx1-cec {
726 <3 RK_PC4 5 &pcfg_pull_none>;
730 hdmim2_tx1_scl: hdmim2-tx1-scl {
733 <1 RK_PA4 5 &pcfg_pull_none>;
737 hdmim2_tx1_sda: hdmim2-tx1-sda {
740 <1 RK_PA3 5 &pcfg_pull_none>;
744 hdmi_debug0: hdmi-debug0 {
747 <1 RK_PA7 7 &pcfg_pull_none>;
751 hdmi_debug1: hdmi-debug1 {
754 <1 RK_PB0 7 &pcfg_pull_none>;
758 hdmi_debug2: hdmi-debug2 {
761 <1 RK_PB1 7 &pcfg_pull_none>;
765 hdmi_debug3: hdmi-debug3 {
768 <1 RK_PB2 7 &pcfg_pull_none>;
772 hdmi_debug4: hdmi-debug4 {
775 <1 RK_PB3 7 &pcfg_pull_none>;
779 hdmi_debug5: hdmi-debug5 {
782 <1 RK_PB4 7 &pcfg_pull_none>;
786 hdmi_debug6: hdmi-debug6 {
789 <1 RK_PA0 7 &pcfg_pull_none>;
795 i2c0m0_xfer: i2c0m0-xfer {
798 <0 RK_PB3 2 &pcfg_pull_none_smt>,
800 <0 RK_PA6 2 &pcfg_pull_none_smt>;
804 i2c0m2_xfer: i2c0m2-xfer {
807 <0 RK_PD1 3 &pcfg_pull_none_smt>,
809 <0 RK_PD2 3 &pcfg_pull_none_smt>;
815 i2c1m0_xfer: i2c1m0-xfer {
818 <0 RK_PB5 9 &pcfg_pull_none_smt>,
820 <0 RK_PB6 9 &pcfg_pull_none_smt>;
824 i2c1m1_xfer: i2c1m1-xfer {
827 <0 RK_PB0 2 &pcfg_pull_none_smt>,
829 <0 RK_PB1 2 &pcfg_pull_none_smt>;
833 i2c1m2_xfer: i2c1m2-xfer {
836 <0 RK_PD4 9 &pcfg_pull_none_smt>,
838 <0 RK_PD5 9 &pcfg_pull_none_smt>;
842 i2c1m3_xfer: i2c1m3-xfer {
845 <2 RK_PD4 9 &pcfg_pull_none_smt>,
847 <2 RK_PD5 9 &pcfg_pull_none_smt>;
851 i2c1m4_xfer: i2c1m4-xfer {
854 <1 RK_PD2 9 &pcfg_pull_none_smt>,
856 <1 RK_PD3 9 &pcfg_pull_none_smt>;
862 i2c2m0_xfer: i2c2m0-xfer {
865 <0 RK_PB7 9 &pcfg_pull_none_smt>,
867 <0 RK_PC0 9 &pcfg_pull_none_smt>;
871 i2c2m2_xfer: i2c2m2-xfer {
874 <2 RK_PA3 9 &pcfg_pull_none_smt>,
876 <2 RK_PA2 9 &pcfg_pull_none_smt>;
880 i2c2m3_xfer: i2c2m3-xfer {
883 <1 RK_PC5 9 &pcfg_pull_none_smt>,
885 <1 RK_PC4 9 &pcfg_pull_none_smt>;
889 i2c2m4_xfer: i2c2m4-xfer {
892 <1 RK_PA1 9 &pcfg_pull_none_smt>,
894 <1 RK_PA0 9 &pcfg_pull_none_smt>;
900 i2c3m0_xfer: i2c3m0-xfer {
903 <1 RK_PC1 9 &pcfg_pull_none_smt>,
905 <1 RK_PC0 9 &pcfg_pull_none_smt>;
909 i2c3m1_xfer: i2c3m1-xfer {
912 <3 RK_PB7 9 &pcfg_pull_none_smt>,
914 <3 RK_PC0 9 &pcfg_pull_none_smt>;
918 i2c3m2_xfer: i2c3m2-xfer {
921 <4 RK_PA4 9 &pcfg_pull_none_smt>,
923 <4 RK_PA5 9 &pcfg_pull_none_smt>;
927 i2c3m4_xfer: i2c3m4-xfer {
930 <4 RK_PD0 9 &pcfg_pull_none_smt>,
932 <4 RK_PD1 9 &pcfg_pull_none_smt>;
938 i2c4m0_xfer: i2c4m0-xfer {
941 <3 RK_PA6 9 &pcfg_pull_none_smt>,
943 <3 RK_PA5 9 &pcfg_pull_none_smt>;
947 i2c4m2_xfer: i2c4m2-xfer {
950 <0 RK_PC5 9 &pcfg_pull_none_smt>,
952 <0 RK_PC4 9 &pcfg_pull_none_smt>;
956 i2c4m3_xfer: i2c4m3-xfer {
959 <1 RK_PA3 9 &pcfg_pull_none_smt>,
961 <1 RK_PA2 9 &pcfg_pull_none_smt>;
965 i2c4m4_xfer: i2c4m4-xfer {
968 <1 RK_PC7 9 &pcfg_pull_none_smt>,
970 <1 RK_PC6 9 &pcfg_pull_none_smt>;
976 i2c5m0_xfer: i2c5m0-xfer {
979 <3 RK_PC7 9 &pcfg_pull_none_smt>,
981 <3 RK_PD0 9 &pcfg_pull_none_smt>;
985 i2c5m1_xfer: i2c5m1-xfer {
988 <4 RK_PB6 9 &pcfg_pull_none_smt>,
990 <4 RK_PB7 9 &pcfg_pull_none_smt>;
994 i2c5m2_xfer: i2c5m2-xfer {
997 <4 RK_PA6 9 &pcfg_pull_none_smt>,
999 <4 RK_PA7 9 &pcfg_pull_none_smt>;
1003 i2c5m3_xfer: i2c5m3-xfer {
1006 <1 RK_PB6 9 &pcfg_pull_none_smt>,
1008 <1 RK_PB7 9 &pcfg_pull_none_smt>;
1014 i2c6m0_xfer: i2c6m0-xfer {
1017 <0 RK_PD0 9 &pcfg_pull_none_smt>,
1019 <0 RK_PC7 9 &pcfg_pull_none_smt>;
1023 i2c6m1_xfer: i2c6m1-xfer {
1026 <1 RK_PC3 9 &pcfg_pull_none_smt>,
1028 <1 RK_PC2 9 &pcfg_pull_none_smt>;
1032 i2c6m3_xfer: i2c6m3-xfer {
1035 <4 RK_PB1 9 &pcfg_pull_none_smt>,
1037 <4 RK_PB0 9 &pcfg_pull_none_smt>;
1041 i2c6m4_xfer: i2c6m4-xfer {
1044 <3 RK_PA1 9 &pcfg_pull_none_smt>,
1046 <3 RK_PA0 9 &pcfg_pull_none_smt>;
1052 i2c7m0_xfer: i2c7m0-xfer {
1055 <1 RK_PD0 9 &pcfg_pull_none_smt>,
1057 <1 RK_PD1 9 &pcfg_pull_none_smt>;
1061 i2c7m2_xfer: i2c7m2-xfer {
1064 <3 RK_PD2 9 &pcfg_pull_none_smt>,
1066 <3 RK_PD3 9 &pcfg_pull_none_smt>;
1070 i2c7m3_xfer: i2c7m3-xfer {
1073 <4 RK_PB2 9 &pcfg_pull_none_smt>,
1075 <4 RK_PB3 9 &pcfg_pull_none_smt>;
1081 i2c8m0_xfer: i2c8m0-xfer {
1084 <4 RK_PD2 9 &pcfg_pull_none_smt>,
1086 <4 RK_PD3 9 &pcfg_pull_none_smt>;
1090 i2c8m2_xfer: i2c8m2-xfer {
1093 <1 RK_PD6 9 &pcfg_pull_none_smt>,
1095 <1 RK_PD7 9 &pcfg_pull_none_smt>;
1099 i2c8m3_xfer: i2c8m3-xfer {
1102 <4 RK_PC0 9 &pcfg_pull_none_smt>,
1104 <4 RK_PC1 9 &pcfg_pull_none_smt>;
1108 i2c8m4_xfer: i2c8m4-xfer {
1111 <3 RK_PC2 9 &pcfg_pull_none_smt>,
1113 <3 RK_PC3 9 &pcfg_pull_none_smt>;
1119 i2s0_lrck: i2s0-lrck {
1122 <1 RK_PC5 1 &pcfg_pull_none>;
1126 i2s0_mclk: i2s0-mclk {
1129 <1 RK_PC2 1 &pcfg_pull_none>;
1133 i2s0_sclk: i2s0-sclk {
1136 <1 RK_PC3 1 &pcfg_pull_none>;
1140 i2s0_sdi0: i2s0-sdi0 {
1143 <1 RK_PD4 2 &pcfg_pull_none>;
1147 i2s0_sdi1: i2s0-sdi1 {
1150 <1 RK_PD3 2 &pcfg_pull_none>;
1154 i2s0_sdi2: i2s0-sdi2 {
1157 <1 RK_PD2 2 &pcfg_pull_none>;
1161 i2s0_sdi3: i2s0-sdi3 {
1164 <1 RK_PD1 2 &pcfg_pull_none>;
1168 i2s0_sdo0: i2s0-sdo0 {
1171 <1 RK_PC7 1 &pcfg_pull_none>;
1175 i2s0_sdo1: i2s0-sdo1 {
1178 <1 RK_PD0 1 &pcfg_pull_none>;
1182 i2s0_sdo2: i2s0-sdo2 {
1185 <1 RK_PD1 1 &pcfg_pull_none>;
1189 i2s0_sdo3: i2s0-sdo3 {
1192 <1 RK_PD2 1 &pcfg_pull_none>;
1198 i2s1m0_lrck: i2s1m0-lrck {
1201 <4 RK_PA2 3 &pcfg_pull_none>;
1205 i2s1m0_mclk: i2s1m0-mclk {
1208 <4 RK_PA0 3 &pcfg_pull_none>;
1212 i2s1m0_sclk: i2s1m0-sclk {
1215 <4 RK_PA1 3 &pcfg_pull_none>;
1219 i2s1m0_sdi0: i2s1m0-sdi0 {
1222 <4 RK_PA5 3 &pcfg_pull_none>;
1226 i2s1m0_sdi1: i2s1m0-sdi1 {
1229 <4 RK_PA6 3 &pcfg_pull_none>;
1233 i2s1m0_sdi2: i2s1m0-sdi2 {
1236 <4 RK_PA7 3 &pcfg_pull_none>;
1240 i2s1m0_sdi3: i2s1m0-sdi3 {
1243 <4 RK_PB0 3 &pcfg_pull_none>;
1247 i2s1m0_sdo0: i2s1m0-sdo0 {
1250 <4 RK_PB1 3 &pcfg_pull_none>;
1254 i2s1m0_sdo1: i2s1m0-sdo1 {
1257 <4 RK_PB2 3 &pcfg_pull_none>;
1261 i2s1m0_sdo2: i2s1m0-sdo2 {
1264 <4 RK_PB3 3 &pcfg_pull_none>;
1268 i2s1m0_sdo3: i2s1m0-sdo3 {
1271 <4 RK_PB4 3 &pcfg_pull_none>;
1274 i2s1m1_lrck: i2s1m1-lrck {
1277 <0 RK_PB7 1 &pcfg_pull_none>;
1281 i2s1m1_mclk: i2s1m1-mclk {
1284 <0 RK_PB5 1 &pcfg_pull_none>;
1288 i2s1m1_sclk: i2s1m1-sclk {
1291 <0 RK_PB6 1 &pcfg_pull_none>;
1295 i2s1m1_sdi0: i2s1m1-sdi0 {
1298 <0 RK_PC5 1 &pcfg_pull_none>;
1302 i2s1m1_sdi1: i2s1m1-sdi1 {
1305 <0 RK_PC6 1 &pcfg_pull_none>;
1309 i2s1m1_sdi2: i2s1m1-sdi2 {
1312 <0 RK_PC7 1 &pcfg_pull_none>;
1316 i2s1m1_sdi3: i2s1m1-sdi3 {
1319 <0 RK_PD0 1 &pcfg_pull_none>;
1323 i2s1m1_sdo0: i2s1m1-sdo0 {
1326 <0 RK_PD1 1 &pcfg_pull_none>;
1330 i2s1m1_sdo1: i2s1m1-sdo1 {
1333 <0 RK_PD2 1 &pcfg_pull_none>;
1337 i2s1m1_sdo2: i2s1m1-sdo2 {
1340 <0 RK_PD4 1 &pcfg_pull_none>;
1344 i2s1m1_sdo3: i2s1m1-sdo3 {
1347 <0 RK_PD5 1 &pcfg_pull_none>;
1353 i2s2m0_lrck: i2s2m0-lrck {
1356 <2 RK_PC0 2 &pcfg_pull_none>;
1360 i2s2m0_mclk: i2s2m0-mclk {
1363 <2 RK_PB6 2 &pcfg_pull_none>;
1367 i2s2m0_sclk: i2s2m0-sclk {
1370 <2 RK_PB7 2 &pcfg_pull_none>;
1374 i2s2m0_sdi: i2s2m0-sdi {
1377 <2 RK_PC3 2 &pcfg_pull_none>;
1381 i2s2m0_sdo: i2s2m0-sdo {
1384 <4 RK_PC3 2 &pcfg_pull_none>;
1388 i2s2m1_lrck: i2s2m1-lrck {
1391 <3 RK_PB6 3 &pcfg_pull_none>;
1395 i2s2m1_mclk: i2s2m1-mclk {
1398 <3 RK_PB4 3 &pcfg_pull_none>;
1402 i2s2m1_sclk: i2s2m1-sclk {
1405 <3 RK_PB5 3 &pcfg_pull_none>;
1409 i2s2m1_sdi: i2s2m1-sdi {
1412 <3 RK_PB2 3 &pcfg_pull_none>;
1416 i2s2m1_sdo: i2s2m1-sdo {
1419 <3 RK_PB3 3 &pcfg_pull_none>;
1425 i2s3_lrck: i2s3-lrck {
1428 <3 RK_PA2 3 &pcfg_pull_none>;
1432 i2s3_mclk: i2s3-mclk {
1435 <3 RK_PA0 3 &pcfg_pull_none>;
1439 i2s3_sclk: i2s3-sclk {
1442 <3 RK_PA1 3 &pcfg_pull_none>;
1446 i2s3_sdi: i2s3-sdi {
1449 <3 RK_PA4 3 &pcfg_pull_none>;
1453 i2s3_sdo: i2s3-sdo {
1456 <3 RK_PA3 3 &pcfg_pull_none>;
1462 jtagm0_pins: jtagm0-pins {
1465 <4 RK_PD2 5 &pcfg_pull_none>,
1467 <4 RK_PD3 5 &pcfg_pull_none>;
1471 jtagm1_pins: jtagm1-pins {
1474 <4 RK_PD0 5 &pcfg_pull_none>,
1476 <4 RK_PD1 5 &pcfg_pull_none>;
1480 jtagm2_pins: jtagm2-pins {
1483 <0 RK_PB5 2 &pcfg_pull_none>,
1485 <0 RK_PB6 2 &pcfg_pull_none>;
1491 litcpu_pins: litcpu-pins {
1494 <0 RK_PD3 1 &pcfg_pull_none>;
1500 mcum0_pins: mcum0-pins {
1502 /* mcu_jtag_tck_m0 */
1503 <4 RK_PD4 5 &pcfg_pull_none>,
1504 /* mcu_jtag_tms_m0 */
1505 <4 RK_PD5 5 &pcfg_pull_none>;
1509 mcum1_pins: mcum1-pins {
1511 /* mcu_jtag_tck_m1 */
1512 <3 RK_PD4 6 &pcfg_pull_none>,
1513 /* mcu_jtag_tms_m1 */
1514 <3 RK_PD5 6 &pcfg_pull_none>;
1520 mipim0_camera0_clk: mipim0-camera0-clk {
1522 /* mipim0_camera0_clk */
1523 <4 RK_PB1 1 &pcfg_pull_none>;
1527 mipim0_camera1_clk: mipim0-camera1-clk {
1529 /* mipim0_camera1_clk */
1530 <1 RK_PB6 2 &pcfg_pull_none>;
1534 mipim0_camera2_clk: mipim0-camera2-clk {
1536 /* mipim0_camera2_clk */
1537 <1 RK_PB7 2 &pcfg_pull_none>;
1541 mipim0_camera3_clk: mipim0-camera3-clk {
1543 /* mipim0_camera3_clk */
1544 <1 RK_PD6 2 &pcfg_pull_none>;
1548 mipim0_camera4_clk: mipim0-camera4-clk {
1550 /* mipim0_camera4_clk */
1551 <1 RK_PD7 2 &pcfg_pull_none>;
1555 mipim1_camera0_clk: mipim1-camera0-clk {
1557 /* mipim1_camera0_clk */
1558 <3 RK_PA5 4 &pcfg_pull_none>;
1562 mipim1_camera1_clk: mipim1-camera1-clk {
1564 /* mipim1_camera1_clk */
1565 <3 RK_PA6 4 &pcfg_pull_none>;
1569 mipim1_camera2_clk: mipim1-camera2-clk {
1571 /* mipim1_camera2_clk */
1572 <3 RK_PA7 4 &pcfg_pull_none>;
1576 mipim1_camera3_clk: mipim1-camera3-clk {
1578 /* mipim1_camera3_clk */
1579 <3 RK_PB0 4 &pcfg_pull_none>;
1583 mipim1_camera4_clk: mipim1-camera4-clk {
1585 /* mipim1_camera4_clk */
1586 <3 RK_PB1 4 &pcfg_pull_none>;
1590 mipi_te0: mipi-te0 {
1593 <3 RK_PC2 2 &pcfg_pull_none>;
1597 mipi_te1: mipi-te1 {
1600 <3 RK_PC3 2 &pcfg_pull_none>;
1606 npu_pins: npu-pins {
1609 <0 RK_PC6 2 &pcfg_pull_none>;
1615 pcie20x1m0_pins: pcie20x1m0-pins {
1617 /* pcie20x1_2_clkreqn_m0 */
1618 <3 RK_PC7 4 &pcfg_pull_none>,
1619 /* pcie20x1_2_perstn_m0 */
1620 <3 RK_PD1 4 &pcfg_pull_none>,
1621 /* pcie20x1_2_waken_m0 */
1622 <3 RK_PD0 4 &pcfg_pull_none>;
1626 pcie20x1m1_pins: pcie20x1m1-pins {
1628 /* pcie20x1_2_clkreqn_m1 */
1629 <4 RK_PB7 4 &pcfg_pull_none>,
1630 /* pcie20x1_2_perstn_m1 */
1631 <4 RK_PC1 4 &pcfg_pull_none>,
1632 /* pcie20x1_2_waken_m1 */
1633 <4 RK_PC0 4 &pcfg_pull_none>;
1637 pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
1639 /* pcie20x1_2_button_rstn */
1640 <4 RK_PB3 4 &pcfg_pull_none>;
1646 pcie30phy_pins: pcie30phy-pins {
1648 /* pcie30phy_dtb0 */
1649 <1 RK_PC4 4 &pcfg_pull_none>,
1650 /* pcie30phy_dtb1 */
1651 <1 RK_PD1 4 &pcfg_pull_none>;
1657 pcie30x1m0_pins: pcie30x1m0-pins {
1659 /* pcie30x1_0_clkreqn_m0 */
1660 <0 RK_PC0 12 &pcfg_pull_none>,
1661 /* pcie30x1_0_perstn_m0 */
1662 <0 RK_PC5 12 &pcfg_pull_none>,
1663 /* pcie30x1_0_waken_m0 */
1664 <0 RK_PC4 12 &pcfg_pull_none>,
1665 /* pcie30x1_1_clkreqn_m0 */
1666 <0 RK_PB5 12 &pcfg_pull_none>,
1667 /* pcie30x1_1_perstn_m0 */
1668 <0 RK_PB7 12 &pcfg_pull_none>,
1669 /* pcie30x1_1_waken_m0 */
1670 <0 RK_PB6 12 &pcfg_pull_none>;
1674 pcie30x1m1_pins: pcie30x1m1-pins {
1676 /* pcie30x1_0_clkreqn_m1 */
1677 <4 RK_PA3 4 &pcfg_pull_none>,
1678 /* pcie30x1_0_perstn_m1 */
1679 <4 RK_PA5 4 &pcfg_pull_none>,
1680 /* pcie30x1_0_waken_m1 */
1681 <4 RK_PA4 4 &pcfg_pull_none>,
1682 /* pcie30x1_1_clkreqn_m1 */
1683 <4 RK_PA0 4 &pcfg_pull_none>,
1684 /* pcie30x1_1_perstn_m1 */
1685 <4 RK_PA2 4 &pcfg_pull_none>,
1686 /* pcie30x1_1_waken_m1 */
1687 <4 RK_PA1 4 &pcfg_pull_none>;
1691 pcie30x1m2_pins: pcie30x1m2-pins {
1693 /* pcie30x1_0_clkreqn_m2 */
1694 <1 RK_PB5 4 &pcfg_pull_none>,
1695 /* pcie30x1_0_perstn_m2 */
1696 <1 RK_PB4 4 &pcfg_pull_none>,
1697 /* pcie30x1_0_waken_m2 */
1698 <1 RK_PB3 4 &pcfg_pull_none>,
1699 /* pcie30x1_1_clkreqn_m2 */
1700 <1 RK_PA0 4 &pcfg_pull_none>,
1701 /* pcie30x1_1_perstn_m2 */
1702 <1 RK_PA7 4 &pcfg_pull_none>,
1703 /* pcie30x1_1_waken_m2 */
1704 <1 RK_PA1 4 &pcfg_pull_none>;
1708 pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
1710 /* pcie30x1_0_button_rstn */
1711 <4 RK_PB1 4 &pcfg_pull_none>;
1715 pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
1717 /* pcie30x1_1_button_rstn */
1718 <4 RK_PB2 4 &pcfg_pull_none>;
1724 pcie30x2m0_pins: pcie30x2m0-pins {
1726 /* pcie30x2_clkreqn_m0 */
1727 <0 RK_PD1 12 &pcfg_pull_none>,
1728 /* pcie30x2_perstn_m0 */
1729 <0 RK_PD4 12 &pcfg_pull_none>,
1730 /* pcie30x2_waken_m0 */
1731 <0 RK_PD2 12 &pcfg_pull_none>;
1735 pcie30x2m1_pins: pcie30x2m1-pins {
1737 /* pcie30x2_clkreqn_m1 */
1738 <4 RK_PA6 4 &pcfg_pull_none>,
1739 /* pcie30x2_perstn_m1 */
1740 <4 RK_PB0 4 &pcfg_pull_none>,
1741 /* pcie30x2_waken_m1 */
1742 <4 RK_PA7 4 &pcfg_pull_none>;
1746 pcie30x2m2_pins: pcie30x2m2-pins {
1748 /* pcie30x2_clkreqn_m2 */
1749 <3 RK_PD2 4 &pcfg_pull_none>,
1750 /* pcie30x2_perstn_m2 */
1751 <3 RK_PD4 4 &pcfg_pull_none>,
1752 /* pcie30x2_waken_m2 */
1753 <3 RK_PD3 4 &pcfg_pull_none>;
1757 pcie30x2m3_pins: pcie30x2m3-pins {
1759 /* pcie30x2_clkreqn_m3 */
1760 <1 RK_PD7 4 &pcfg_pull_none>,
1761 /* pcie30x2_perstn_m3 */
1762 <1 RK_PB7 4 &pcfg_pull_none>,
1763 /* pcie30x2_waken_m3 */
1764 <1 RK_PB6 4 &pcfg_pull_none>;
1768 pcie30x2_button_rstn: pcie30x2-button-rstn {
1770 /* pcie30x2_button_rstn */
1771 <3 RK_PC1 4 &pcfg_pull_none>;
1777 pcie30x4m0_pins: pcie30x4m0-pins {
1779 /* pcie30x4_clkreqn_m0 */
1780 <0 RK_PC6 12 &pcfg_pull_none>,
1781 /* pcie30x4_perstn_m0 */
1782 <0 RK_PD0 12 &pcfg_pull_none>,
1783 /* pcie30x4_waken_m0 */
1784 <0 RK_PC7 12 &pcfg_pull_none>;
1788 pcie30x4m1_pins: pcie30x4m1-pins {
1790 /* pcie30x4_clkreqn_m1 */
1791 <4 RK_PB4 4 &pcfg_pull_none>,
1792 /* pcie30x4_perstn_m1 */
1793 <4 RK_PB6 4 &pcfg_pull_none>,
1794 /* pcie30x4_waken_m1 */
1795 <4 RK_PB5 4 &pcfg_pull_none>;
1799 pcie30x4m2_pins: pcie30x4m2-pins {
1801 /* pcie30x4_clkreqn_m2 */
1802 <3 RK_PC4 4 &pcfg_pull_none>,
1803 /* pcie30x4_perstn_m2 */
1804 <3 RK_PC6 4 &pcfg_pull_none>,
1805 /* pcie30x4_waken_m2 */
1806 <3 RK_PC5 4 &pcfg_pull_none>;
1810 pcie30x4m3_pins: pcie30x4m3-pins {
1812 /* pcie30x4_clkreqn_m3 */
1813 <1 RK_PB0 4 &pcfg_pull_none>,
1814 /* pcie30x4_perstn_m3 */
1815 <1 RK_PB2 4 &pcfg_pull_none>,
1816 /* pcie30x4_waken_m3 */
1817 <1 RK_PB1 4 &pcfg_pull_none>;
1821 pcie30x4_button_rstn: pcie30x4-button-rstn {
1823 /* pcie30x4_button_rstn */
1824 <3 RK_PD5 4 &pcfg_pull_none>;
1830 pdm0m0_clk: pdm0m0-clk {
1833 <1 RK_PC6 3 &pcfg_pull_none>;
1837 pdm0m0_clk1: pdm0m0-clk1 {
1840 <1 RK_PC4 3 &pcfg_pull_none>;
1844 pdm0m0_sdi0: pdm0m0-sdi0 {
1847 <1 RK_PD5 3 &pcfg_pull_none>;
1851 pdm0m0_sdi1: pdm0m0-sdi1 {
1854 <1 RK_PD1 3 &pcfg_pull_none>;
1858 pdm0m0_sdi2: pdm0m0-sdi2 {
1861 <1 RK_PD2 3 &pcfg_pull_none>;
1865 pdm0m0_sdi3: pdm0m0-sdi3 {
1868 <1 RK_PD3 3 &pcfg_pull_none>;
1871 pdm0m1_clk: pdm0m1-clk {
1874 <0 RK_PC0 2 &pcfg_pull_none>;
1878 pdm0m1_clk1: pdm0m1-clk1 {
1881 <0 RK_PC4 2 &pcfg_pull_none>;
1885 pdm0m1_sdi0: pdm0m1-sdi0 {
1888 <0 RK_PC7 2 &pcfg_pull_none>;
1892 pdm0m1_sdi1: pdm0m1-sdi1 {
1895 <0 RK_PD0 2 &pcfg_pull_none>;
1899 pdm0m1_sdi2: pdm0m1-sdi2 {
1902 <0 RK_PD4 2 &pcfg_pull_none>;
1906 pdm0m1_sdi3: pdm0m1-sdi3 {
1909 <0 RK_PD6 2 &pcfg_pull_none>;
1915 pdm1m0_clk: pdm1m0-clk {
1918 <4 RK_PD5 2 &pcfg_pull_none>;
1922 pdm1m0_clk1: pdm1m0-clk1 {
1925 <4 RK_PD4 2 &pcfg_pull_none>;
1929 pdm1m0_sdi0: pdm1m0-sdi0 {
1932 <4 RK_PD3 2 &pcfg_pull_none>;
1936 pdm1m0_sdi1: pdm1m0-sdi1 {
1939 <4 RK_PD2 2 &pcfg_pull_none>;
1943 pdm1m0_sdi2: pdm1m0-sdi2 {
1946 <4 RK_PD1 2 &pcfg_pull_none>;
1950 pdm1m0_sdi3: pdm1m0-sdi3 {
1953 <4 RK_PD0 2 &pcfg_pull_none>;
1956 pdm1m1_clk: pdm1m1-clk {
1959 <1 RK_PB4 2 &pcfg_pull_none>;
1963 pdm1m1_clk1: pdm1m1-clk1 {
1966 <1 RK_PB3 2 &pcfg_pull_none>;
1970 pdm1m1_sdi0: pdm1m1-sdi0 {
1973 <1 RK_PA7 2 &pcfg_pull_none>;
1977 pdm1m1_sdi1: pdm1m1-sdi1 {
1980 <1 RK_PB0 2 &pcfg_pull_none>;
1984 pdm1m1_sdi2: pdm1m1-sdi2 {
1987 <1 RK_PB1 2 &pcfg_pull_none>;
1991 pdm1m1_sdi3: pdm1m1-sdi3 {
1994 <1 RK_PB2 2 &pcfg_pull_none>;
2000 pmic_pins: pmic-pins {
2003 <0 RK_PA7 0 &pcfg_pull_up>,
2005 <0 RK_PA2 1 &pcfg_pull_none>,
2007 <0 RK_PA3 1 &pcfg_pull_none>,
2009 <0 RK_PC1 1 &pcfg_pull_none>,
2011 <0 RK_PC2 1 &pcfg_pull_none>,
2013 <0 RK_PC3 1 &pcfg_pull_none>,
2015 <0 RK_PD6 1 &pcfg_pull_none>;
2021 pmu_pins: pmu-pins {
2024 <0 RK_PA5 3 &pcfg_pull_none>;
2030 pwm0m0_pins: pwm0m0-pins {
2033 <0 RK_PB7 3 &pcfg_pull_none>;
2037 pwm0m1_pins: pwm0m1-pins {
2040 <1 RK_PD2 11 &pcfg_pull_none>;
2044 pwm0m2_pins: pwm0m2-pins {
2047 <1 RK_PA2 11 &pcfg_pull_none>;
2053 pwm1m0_pins: pwm1m0-pins {
2056 <0 RK_PC0 3 &pcfg_pull_none>;
2060 pwm1m1_pins: pwm1m1-pins {
2063 <1 RK_PD3 11 &pcfg_pull_none>;
2067 pwm1m2_pins: pwm1m2-pins {
2070 <1 RK_PA3 11 &pcfg_pull_none>;
2076 pwm2m0_pins: pwm2m0-pins {
2079 <0 RK_PC4 3 &pcfg_pull_none>;
2083 pwm2m1_pins: pwm2m1-pins {
2086 <3 RK_PB1 11 &pcfg_pull_none>;
2092 pwm3m0_pins: pwm3m0-pins {
2095 <0 RK_PD4 3 &pcfg_pull_none>;
2099 pwm3m1_pins: pwm3m1-pins {
2102 <3 RK_PB2 11 &pcfg_pull_none>;
2106 pwm3m2_pins: pwm3m2-pins {
2109 <1 RK_PC2 11 &pcfg_pull_none>;
2113 pwm3m3_pins: pwm3m3-pins {
2116 <1 RK_PA7 11 &pcfg_pull_none>;
2122 pwm4m0_pins: pwm4m0-pins {
2125 <0 RK_PC5 11 &pcfg_pull_none>;
2131 pwm5m0_pins: pwm5m0-pins {
2134 <0 RK_PB1 3 &pcfg_pull_none>;
2138 pwm5m1_pins: pwm5m1-pins {
2141 <0 RK_PC6 11 &pcfg_pull_none>;
2147 pwm6m0_pins: pwm6m0-pins {
2150 <0 RK_PC7 11 &pcfg_pull_none>;
2154 pwm6m1_pins: pwm6m1-pins {
2157 <4 RK_PC1 11 &pcfg_pull_none>;
2163 pwm7m0_pins: pwm7m0-pins {
2166 <0 RK_PD0 11 &pcfg_pull_none>;
2170 pwm7m1_pins: pwm7m1-pins {
2173 <4 RK_PD4 11 &pcfg_pull_none>;
2177 pwm7m2_pins: pwm7m2-pins {
2180 <1 RK_PC3 11 &pcfg_pull_none>;
2186 pwm8m0_pins: pwm8m0-pins {
2189 <3 RK_PA7 11 &pcfg_pull_none>;
2193 pwm8m1_pins: pwm8m1-pins {
2196 <4 RK_PD0 11 &pcfg_pull_none>;
2200 pwm8m2_pins: pwm8m2-pins {
2203 <3 RK_PD0 11 &pcfg_pull_none>;
2209 pwm9m0_pins: pwm9m0-pins {
2212 <3 RK_PB0 11 &pcfg_pull_none>;
2216 pwm9m1_pins: pwm9m1-pins {
2219 <4 RK_PD1 11 &pcfg_pull_none>;
2223 pwm9m2_pins: pwm9m2-pins {
2226 <3 RK_PD1 11 &pcfg_pull_none>;
2232 pwm10m0_pins: pwm10m0-pins {
2235 <3 RK_PA0 11 &pcfg_pull_none>;
2239 pwm10m1_pins: pwm10m1-pins {
2242 <4 RK_PD3 11 &pcfg_pull_none>;
2246 pwm10m2_pins: pwm10m2-pins {
2249 <3 RK_PD3 11 &pcfg_pull_none>;
2255 pwm11m0_pins: pwm11m0-pins {
2258 <3 RK_PA1 11 &pcfg_pull_none>;
2262 pwm11m1_pins: pwm11m1-pins {
2265 <4 RK_PB4 11 &pcfg_pull_none>;
2269 pwm11m2_pins: pwm11m2-pins {
2272 <1 RK_PC4 11 &pcfg_pull_none>;
2276 pwm11m3_pins: pwm11m3-pins {
2279 <3 RK_PD5 11 &pcfg_pull_none>;
2285 pwm12m0_pins: pwm12m0-pins {
2288 <3 RK_PB5 11 &pcfg_pull_none>;
2292 pwm12m1_pins: pwm12m1-pins {
2295 <4 RK_PB5 11 &pcfg_pull_none>;
2301 pwm13m0_pins: pwm13m0-pins {
2304 <3 RK_PB6 11 &pcfg_pull_none>;
2308 pwm13m1_pins: pwm13m1-pins {
2311 <4 RK_PB6 11 &pcfg_pull_none>;
2315 pwm13m2_pins: pwm13m2-pins {
2318 <1 RK_PB7 11 &pcfg_pull_none>;
2324 pwm14m0_pins: pwm14m0-pins {
2327 <3 RK_PC2 11 &pcfg_pull_none>;
2331 pwm14m1_pins: pwm14m1-pins {
2334 <4 RK_PB2 11 &pcfg_pull_none>;
2338 pwm14m2_pins: pwm14m2-pins {
2341 <1 RK_PD6 11 &pcfg_pull_none>;
2347 pwm15m0_pins: pwm15m0-pins {
2350 <3 RK_PC3 11 &pcfg_pull_none>;
2354 pwm15m1_pins: pwm15m1-pins {
2357 <4 RK_PB3 11 &pcfg_pull_none>;
2361 pwm15m2_pins: pwm15m2-pins {
2364 <1 RK_PC6 11 &pcfg_pull_none>;
2368 pwm15m3_pins: pwm15m3-pins {
2371 <1 RK_PD7 11 &pcfg_pull_none>;
2377 refclk_pins: refclk-pins {
2380 <0 RK_PA0 1 &pcfg_pull_none>;
2386 sata_pins: sata-pins {
2389 <0 RK_PC6 13 &pcfg_pull_none>,
2391 <0 RK_PD4 13 &pcfg_pull_none>,
2392 /* sata_mp_switch */
2393 <0 RK_PD5 13 &pcfg_pull_none>;
2399 sata0m0_pins: sata0m0-pins {
2401 /* sata0_act_led_m0 */
2402 <4 RK_PB6 6 &pcfg_pull_none>;
2406 sata0m1_pins: sata0m1-pins {
2408 /* sata0_act_led_m1 */
2409 <1 RK_PB3 6 &pcfg_pull_none>;
2415 sata1m0_pins: sata1m0-pins {
2417 /* sata1_act_led_m0 */
2418 <4 RK_PB5 6 &pcfg_pull_none>;
2422 sata1m1_pins: sata1m1-pins {
2424 /* sata1_act_led_m1 */
2425 <1 RK_PA1 6 &pcfg_pull_none>;
2431 sata2m0_pins: sata2m0-pins {
2433 /* sata2_act_led_m0 */
2434 <4 RK_PB1 6 &pcfg_pull_none>;
2438 sata2m1_pins: sata2m1-pins {
2440 /* sata2_act_led_m1 */
2441 <1 RK_PB7 6 &pcfg_pull_none>;
2447 sdiom1_pins: sdiom1-pins {
2450 <3 RK_PA5 2 &pcfg_pull_none>,
2452 <3 RK_PA4 2 &pcfg_pull_none>,
2454 <3 RK_PA0 2 &pcfg_pull_none>,
2456 <3 RK_PA1 2 &pcfg_pull_none>,
2458 <3 RK_PA2 2 &pcfg_pull_none>,
2460 <3 RK_PA3 2 &pcfg_pull_none>;
2466 sdmmc_bus4: sdmmc-bus4 {
2469 <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
2471 <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
2473 <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
2475 <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
2479 sdmmc_clk: sdmmc-clk {
2482 <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
2486 sdmmc_cmd: sdmmc-cmd {
2489 <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
2493 sdmmc_det: sdmmc-det {
2496 <0 RK_PA4 1 &pcfg_pull_up>;
2500 sdmmc_pwren: sdmmc-pwren {
2503 <0 RK_PA5 2 &pcfg_pull_none>;
2509 spdif0m0_tx: spdif0m0-tx {
2512 <1 RK_PB6 3 &pcfg_pull_none>;
2516 spdif0m1_tx: spdif0m1-tx {
2519 <4 RK_PB4 6 &pcfg_pull_none>;
2525 spdif1m0_tx: spdif1m0-tx {
2528 <1 RK_PB7 3 &pcfg_pull_none>;
2532 spdif1m1_tx: spdif1m1-tx {
2535 <4 RK_PB1 2 &pcfg_pull_none>;
2539 spdif1m2_tx: spdif1m2-tx {
2542 <4 RK_PC1 3 &pcfg_pull_none>;
2548 spi0m0_pins: spi0m0-pins {
2551 <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2553 <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
2555 <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2559 spi0m0_cs0: spi0m0-cs0 {
2562 <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2566 spi0m0_cs1: spi0m0-cs1 {
2569 <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2572 spi0m1_pins: spi0m1-pins {
2575 <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2577 <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2579 <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2583 spi0m1_cs0: spi0m1-cs0 {
2586 <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2590 spi0m1_cs1: spi0m1-cs1 {
2593 <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
2596 spi0m2_pins: spi0m2-pins {
2599 <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
2601 <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
2603 <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2607 spi0m2_cs0: spi0m2-cs0 {
2610 <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
2614 spi0m2_cs1: spi0m2-cs1 {
2617 <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
2620 spi0m3_pins: spi0m3-pins {
2623 <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2625 <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
2627 <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2631 spi0m3_cs0: spi0m3-cs0 {
2634 <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2638 spi0m3_cs1: spi0m3-cs1 {
2641 <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2647 spi1m1_pins: spi1m1-pins {
2650 <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
2652 <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2654 <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2658 spi1m1_cs0: spi1m1-cs0 {
2661 <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
2665 spi1m1_cs1: spi1m1-cs1 {
2668 <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2672 spi1m2_pins: spi1m2-pins {
2675 <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
2677 <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2679 <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2683 spi1m2_cs0: spi1m2-cs0 {
2686 <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
2690 spi1m2_cs1: spi1m2-cs1 {
2693 <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2699 spi2m0_pins: spi2m0-pins {
2702 <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2704 <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2706 <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2710 spi2m0_cs0: spi2m0-cs0 {
2713 <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2717 spi2m0_cs1: spi2m0-cs1 {
2720 <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2724 spi2m1_pins: spi2m1-pins {
2727 <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2729 <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2731 <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2735 spi2m1_cs0: spi2m1-cs0 {
2738 <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2742 spi2m1_cs1: spi2m1-cs1 {
2745 <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2749 spi2m2_pins: spi2m2-pins {
2752 <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
2754 <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
2756 <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
2760 spi2m2_cs0: spi2m2-cs0 {
2763 <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
2767 spi2m2_cs1: spi2m2-cs1 {
2770 <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
2776 spi3m1_pins: spi3m1-pins {
2779 <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
2781 <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
2783 <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
2787 spi3m1_cs0: spi3m1-cs0 {
2790 <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2794 spi3m1_cs1: spi3m1-cs1 {
2797 <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2801 spi3m2_pins: spi3m2-pins {
2804 <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2806 <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2808 <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2812 spi3m2_cs0: spi3m2-cs0 {
2815 <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2819 spi3m2_cs1: spi3m2-cs1 {
2822 <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2826 spi3m3_pins: spi3m3-pins {
2829 <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2831 <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2833 <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
2837 spi3m3_cs0: spi3m3-cs0 {
2840 <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2844 spi3m3_cs1: spi3m3-cs1 {
2847 <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
2853 spi4m0_pins: spi4m0-pins {
2856 <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
2858 <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2860 <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2864 spi4m0_cs0: spi4m0-cs0 {
2867 <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2871 spi4m0_cs1: spi4m0-cs1 {
2874 <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2878 spi4m1_pins: spi4m1-pins {
2881 <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2883 <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2885 <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2889 spi4m1_cs0: spi4m1-cs0 {
2892 <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2896 spi4m1_cs1: spi4m1-cs1 {
2899 <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
2903 spi4m2_pins: spi4m2-pins {
2906 <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2908 <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2910 <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2914 spi4m2_cs0: spi4m2-cs0 {
2917 <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2923 tsadcm1_shut: tsadcm1-shut {
2926 <0 RK_PA2 2 &pcfg_pull_none>;
2930 tsadc_shut: tsadc-shut {
2933 <0 RK_PA1 2 &pcfg_pull_none>;
2937 tsadc_shut_org: tsadc-shut-org {
2939 /* tsadc_shut_org */
2940 <0 RK_PA1 1 &pcfg_pull_none>;
2946 uart0m0_xfer: uart0m0-xfer {
2949 <0 RK_PC4 4 &pcfg_pull_up>,
2951 <0 RK_PC5 4 &pcfg_pull_up>;
2955 uart0m1_xfer: uart0m1-xfer {
2958 <0 RK_PB0 4 &pcfg_pull_up>,
2960 <0 RK_PB1 4 &pcfg_pull_up>;
2964 uart0m2_xfer: uart0m2-xfer {
2967 <4 RK_PA4 10 &pcfg_pull_up>,
2969 <4 RK_PA3 10 &pcfg_pull_up>;
2973 uart0_ctsn: uart0-ctsn {
2976 <0 RK_PD1 4 &pcfg_pull_none>;
2980 uart0_rtsn: uart0-rtsn {
2983 <0 RK_PC6 4 &pcfg_pull_none>;
2989 uart1m1_xfer: uart1m1-xfer {
2992 <1 RK_PB7 10 &pcfg_pull_up>,
2994 <1 RK_PB6 10 &pcfg_pull_up>;
2998 uart1m1_ctsn: uart1m1-ctsn {
3001 <1 RK_PD7 10 &pcfg_pull_none>;
3005 uart1m1_rtsn: uart1m1-rtsn {
3008 <1 RK_PD6 10 &pcfg_pull_none>;
3012 uart1m2_xfer: uart1m2-xfer {
3015 <0 RK_PD2 10 &pcfg_pull_up>,
3017 <0 RK_PD1 10 &pcfg_pull_up>;
3021 uart1m2_ctsn: uart1m2-ctsn {
3024 <0 RK_PD0 10 &pcfg_pull_none>;
3028 uart1m2_rtsn: uart1m2-rtsn {
3031 <0 RK_PC7 10 &pcfg_pull_none>;
3037 uart2m0_xfer: uart2m0-xfer {
3040 <0 RK_PB6 10 &pcfg_pull_up>,
3042 <0 RK_PB5 10 &pcfg_pull_up>;
3046 uart2m1_xfer: uart2m1-xfer {
3049 <4 RK_PD1 10 &pcfg_pull_up>,
3051 <4 RK_PD0 10 &pcfg_pull_up>;
3055 uart2m2_xfer: uart2m2-xfer {
3058 <3 RK_PB2 10 &pcfg_pull_up>,
3060 <3 RK_PB1 10 &pcfg_pull_up>;
3064 uart2_ctsn: uart2-ctsn {
3067 <3 RK_PB4 10 &pcfg_pull_none>;
3071 uart2_rtsn: uart2-rtsn {
3074 <3 RK_PB3 10 &pcfg_pull_none>;
3080 uart3m0_xfer: uart3m0-xfer {
3083 <1 RK_PC0 10 &pcfg_pull_up>,
3085 <1 RK_PC1 10 &pcfg_pull_up>;
3089 uart3m1_xfer: uart3m1-xfer {
3092 <3 RK_PB6 10 &pcfg_pull_up>,
3094 <3 RK_PB5 10 &pcfg_pull_up>;
3098 uart3m2_xfer: uart3m2-xfer {
3101 <4 RK_PA6 10 &pcfg_pull_up>,
3103 <4 RK_PA5 10 &pcfg_pull_up>;
3107 uart3_ctsn: uart3-ctsn {
3110 <1 RK_PC3 10 &pcfg_pull_none>;
3114 uart3_rtsn: uart3-rtsn {
3117 <1 RK_PC2 10 &pcfg_pull_none>;
3123 uart4m0_xfer: uart4m0-xfer {
3126 <1 RK_PD3 10 &pcfg_pull_up>,
3128 <1 RK_PD2 10 &pcfg_pull_up>;
3132 uart4m1_xfer: uart4m1-xfer {
3135 <3 RK_PD0 10 &pcfg_pull_up>,
3137 <3 RK_PD1 10 &pcfg_pull_up>;
3141 uart4m2_xfer: uart4m2-xfer {
3144 <1 RK_PB2 10 &pcfg_pull_up>,
3146 <1 RK_PB3 10 &pcfg_pull_up>;
3150 uart4_ctsn: uart4-ctsn {
3153 <1 RK_PC7 10 &pcfg_pull_none>;
3157 uart4_rtsn: uart4-rtsn {
3160 <1 RK_PC5 10 &pcfg_pull_none>;
3166 uart5m0_xfer: uart5m0-xfer {
3169 <4 RK_PD4 10 &pcfg_pull_up>,
3171 <4 RK_PD5 10 &pcfg_pull_up>;
3175 uart5m0_ctsn: uart5m0-ctsn {
3178 <4 RK_PD2 10 &pcfg_pull_none>;
3182 uart5m0_rtsn: uart5m0-rtsn {
3185 <4 RK_PD3 10 &pcfg_pull_none>;
3189 uart5m1_xfer: uart5m1-xfer {
3192 <3 RK_PC5 10 &pcfg_pull_up>,
3194 <3 RK_PC4 10 &pcfg_pull_up>;
3198 uart5m1_ctsn: uart5m1-ctsn {
3201 <2 RK_PA2 10 &pcfg_pull_none>;
3205 uart5m1_rtsn: uart5m1-rtsn {
3208 <2 RK_PA3 10 &pcfg_pull_none>;
3212 uart5m2_xfer: uart5m2-xfer {
3215 <2 RK_PD4 10 &pcfg_pull_up>,
3217 <2 RK_PD5 10 &pcfg_pull_up>;
3223 uart6m1_xfer: uart6m1-xfer {
3226 <1 RK_PA0 10 &pcfg_pull_up>,
3228 <1 RK_PA1 10 &pcfg_pull_up>;
3232 uart6m1_ctsn: uart6m1-ctsn {
3235 <1 RK_PA3 10 &pcfg_pull_none>;
3239 uart6m1_rtsn: uart6m1-rtsn {
3242 <1 RK_PA2 10 &pcfg_pull_none>;
3246 uart6m2_xfer: uart6m2-xfer {
3249 <1 RK_PD1 10 &pcfg_pull_up>,
3251 <1 RK_PD0 10 &pcfg_pull_up>;
3257 uart7m1_xfer: uart7m1-xfer {
3260 <3 RK_PC1 10 &pcfg_pull_up>,
3262 <3 RK_PC0 10 &pcfg_pull_up>;
3266 uart7m1_ctsn: uart7m1-ctsn {
3269 <3 RK_PC3 10 &pcfg_pull_none>;
3273 uart7m1_rtsn: uart7m1-rtsn {
3276 <3 RK_PC2 10 &pcfg_pull_none>;
3280 uart7m2_xfer: uart7m2-xfer {
3283 <1 RK_PB4 10 &pcfg_pull_up>,
3285 <1 RK_PB5 10 &pcfg_pull_up>;
3291 uart8m0_xfer: uart8m0-xfer {
3294 <4 RK_PB1 10 &pcfg_pull_up>,
3296 <4 RK_PB0 10 &pcfg_pull_up>;
3300 uart8m0_ctsn: uart8m0-ctsn {
3303 <4 RK_PB3 10 &pcfg_pull_none>;
3307 uart8m0_rtsn: uart8m0-rtsn {
3310 <4 RK_PB2 10 &pcfg_pull_none>;
3314 uart8m1_xfer: uart8m1-xfer {
3317 <3 RK_PA3 10 &pcfg_pull_up>,
3319 <3 RK_PA2 10 &pcfg_pull_up>;
3323 uart8m1_ctsn: uart8m1-ctsn {
3326 <3 RK_PA5 10 &pcfg_pull_none>;
3330 uart8m1_rtsn: uart8m1-rtsn {
3333 <3 RK_PA4 10 &pcfg_pull_none>;
3337 uart8_xfer: uart8-xfer {
3340 <4 RK_PB1 10 &pcfg_pull_up>;
3346 uart9m0_xfer: uart9m0-xfer {
3349 <2 RK_PC4 10 &pcfg_pull_up>,
3351 <2 RK_PC2 10 &pcfg_pull_up>;
3355 uart9m1_xfer: uart9m1-xfer {
3358 <4 RK_PB5 10 &pcfg_pull_up>,
3360 <4 RK_PB4 10 &pcfg_pull_up>;
3364 uart9m1_ctsn: uart9m1-ctsn {
3367 <4 RK_PA1 10 &pcfg_pull_none>;
3371 uart9m1_rtsn: uart9m1-rtsn {
3374 <4 RK_PA0 10 &pcfg_pull_none>;
3378 uart9m2_xfer: uart9m2-xfer {
3381 <3 RK_PD4 10 &pcfg_pull_up>,
3383 <3 RK_PD5 10 &pcfg_pull_up>;
3387 uart9m2_ctsn: uart9m2-ctsn {
3390 <3 RK_PD3 10 &pcfg_pull_none>;
3394 uart9m2_rtsn: uart9m2-rtsn {
3397 <3 RK_PD2 10 &pcfg_pull_none>;
3403 vop_pins: vop-pins {
3405 /* vop_post_empty */
3406 <1 RK_PA2 1 &pcfg_pull_none>;
3412 * This part is edited handly.
3417 bt656_pins: bt656-pins {
3420 <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
3422 <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
3424 <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
3426 <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
3428 <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
3430 <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
3432 <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
3434 <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
3436 <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
3442 tsadc_gpio_func: tsadc-gpio-func {
3444 <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;