arch/arm64/boot/dts/rockchip/rk3588.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include "rk3588s.dtsi"
   7 #include "rk3588-pinctrl.dtsi"
   8
   9 / {
  10         pcie30_phy_grf: syscon@fd5b8000 {
  11                 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
  12                 reg = <0x0 0xfd5b8000 0x0 0x10000>;
  13         };
  14
  15         pipe_phy1_grf: syscon@fd5c0000 {
  16                 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
  17                 reg = <0x0 0xfd5c0000 0x0 0x100>;
  18         };
  19
  20         i2s8_8ch: i2s@fddc8000 {
  21                 compatible = "rockchip,rk3588-i2s-tdm";
  22                 reg = <0x0 0xfddc8000 0x0 0x1000>;
  23                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
  24                 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
  25                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  26                 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
  27                 assigned-clock-parents = <&cru PLL_AUPLL>;
  28                 dmas = <&dmac2 22>;
  29                 dma-names = "tx";
  30                 power-domains = <&power RK3588_PD_VO0>;
  31                 resets = <&cru SRST_M_I2S8_8CH_TX>;
  32                 reset-names = "tx-m";
  33                 #sound-dai-cells = <0>;
  34                 status = "disabled";
  35         };
  36
  37         i2s6_8ch: i2s@fddf4000 {
  38                 compatible = "rockchip,rk3588-i2s-tdm";
  39                 reg = <0x0 0xfddf4000 0x0 0x1000>;
  40                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
  41                 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
  42                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  43                 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
  44                 assigned-clock-parents = <&cru PLL_AUPLL>;
  45                 dmas = <&dmac2 4>;
  46                 dma-names = "tx";
  47                 power-domains = <&power RK3588_PD_VO1>;
  48                 resets = <&cru SRST_M_I2S6_8CH_TX>;
  49                 reset-names = "tx-m";
  50                 #sound-dai-cells = <0>;
  51                 status = "disabled";
  52         };
  53
  54         i2s7_8ch: i2s@fddf8000 {
  55                 compatible = "rockchip,rk3588-i2s-tdm";
  56                 reg = <0x0 0xfddf8000 0x0 0x1000>;
  57                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
  58                 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
  59                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  60                 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
  61                 assigned-clock-parents = <&cru PLL_AUPLL>;
  62                 dmas = <&dmac2 21>;
  63                 dma-names = "rx";
  64                 power-domains = <&power RK3588_PD_VO1>;
  65                 resets = <&cru SRST_M_I2S7_8CH_RX>;
  66                 reset-names = "rx-m";
  67                 #sound-dai-cells = <0>;
  68                 status = "disabled";
  69         };
  70
  71         i2s10_8ch: i2s@fde00000 {
  72                 compatible = "rockchip,rk3588-i2s-tdm";
  73                 reg = <0x0 0xfde00000 0x0 0x1000>;
  74                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
  75                 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
  76                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  77                 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
  78                 assigned-clock-parents = <&cru PLL_AUPLL>;
  79                 dmas = <&dmac2 24>;
  80                 dma-names = "rx";
  81                 power-domains = <&power RK3588_PD_VO1>;
  82                 resets = <&cru SRST_M_I2S10_8CH_RX>;
  83                 reset-names = "rx-m";
  84                 #sound-dai-cells = <0>;
  85                 status = "disabled";
  86         };
  87
  88         pcie3x4: pcie@fe150000 {
  89                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  90                 #address-cells = <3>;
  91                 #size-cells = <2>;
  92                 bus-range = <0x00 0x0f>;
  93                 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
  94                          <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
  95                          <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
  96                 clock-names = "aclk_mst", "aclk_slv",
  97                               "aclk_dbi", "pclk",
  98                               "aux", "pipe";
  99                 device_type = "pci";
 100                 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
 101                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
 102                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
 103                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
 104                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
 105                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 106                 #interrupt-cells = <1>;
 107                 interrupt-map-mask = <0 0 0 7>;
 108                 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
 109                                 <0 0 0 2 &pcie3x4_intc 1>,
 110                                 <0 0 0 3 &pcie3x4_intc 2>,
 111                                 <0 0 0 4 &pcie3x4_intc 3>;
 112                 linux,pci-domain = <0>;
 113                 max-link-speed = <3>;
 114                 msi-map = <0x0000 &its1 0x0000 0x1000>;
 115                 num-lanes = <4>;
 116                 phys = <&pcie30phy>;
 117                 phy-names = "pcie-phy";
 118                 power-domains = <&power RK3588_PD_PCIE>;
 119                 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
 120                          <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
 121                          <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
 122                 reg = <0xa 0x40000000 0x0 0x00400000>,
 123                       <0x0 0xfe150000 0x0 0x00010000>,
 124                       <0x0 0xf0000000 0x0 0x00100000>;
 125                 reg-names = "dbi", "apb", "config";
 126                 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
 127                 reset-names = "pwr", "pipe";
 128                 status = "disabled";
 129
 130                 pcie3x4_intc: legacy-interrupt-controller {
 131                         interrupt-controller;
 132                         #address-cells = <0>;
 133                         #interrupt-cells = <1>;
 134                         interrupt-parent = <&gic>;
 135                         interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
 136                 };
 137         };
 138
 139         pcie3x2: pcie@fe160000 {
 140                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 141                 #address-cells = <3>;
 142                 #size-cells = <2>;
 143                 bus-range = <0x10 0x1f>;
 144                 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
 145                          <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
 146                          <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
 147                 clock-names = "aclk_mst", "aclk_slv",
 148                               "aclk_dbi", "pclk",
 149                               "aux", "pipe";
 150                 device_type = "pci";
 151                 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
 152                              <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
 153                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
 154                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
 155                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
 156                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 157                 #interrupt-cells = <1>;
 158                 interrupt-map-mask = <0 0 0 7>;
 159                 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
 160                                 <0 0 0 2 &pcie3x2_intc 1>,
 161                                 <0 0 0 3 &pcie3x2_intc 2>,
 162                                 <0 0 0 4 &pcie3x2_intc 3>;
 163                 linux,pci-domain = <1>;
 164                 max-link-speed = <3>;
 165                 msi-map = <0x1000 &its1 0x1000 0x1000>;
 166                 num-lanes = <2>;
 167                 phys = <&pcie30phy>;
 168                 phy-names = "pcie-phy";
 169                 power-domains = <&power RK3588_PD_PCIE>;
 170                 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
 171                          <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
 172                          <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
 173                 reg = <0xa 0x40400000 0x0 0x00400000>,
 174                       <0x0 0xfe160000 0x0 0x00010000>,
 175                       <0x0 0xf1000000 0x0 0x00100000>;
 176                 reg-names = "dbi", "apb", "config";
 177                 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
 178                 reset-names = "pwr", "pipe";
 179                 status = "disabled";
 180
 181                 pcie3x2_intc: legacy-interrupt-controller {
 182                         interrupt-controller;
 183                         #address-cells = <0>;
 184                         #interrupt-cells = <1>;
 185                         interrupt-parent = <&gic>;
 186                         interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
 187                 };
 188         };
 189
 190         pcie2x1l0: pcie@fe170000 {
 191                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 192                 bus-range = <0x20 0x2f>;
 193                 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
 194                          <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
 195                          <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
 196                 clock-names = "aclk_mst", "aclk_slv",
 197                               "aclk_dbi", "pclk",
 198                               "aux", "pipe";
 199                 device_type = "pci";
 200                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
 201                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
 202                              <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
 203                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
 204                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
 205                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 206                 #interrupt-cells = <1>;
 207                 interrupt-map-mask = <0 0 0 7>;
 208                 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
 209                                 <0 0 0 2 &pcie2x1l0_intc 1>,
 210                                 <0 0 0 3 &pcie2x1l0_intc 2>,
 211                                 <0 0 0 4 &pcie2x1l0_intc 3>;
 212                 linux,pci-domain = <2>;
 213                 max-link-speed = <2>;
 214                 msi-map = <0x2000 &its0 0x2000 0x1000>;
 215                 num-lanes = <1>;
 216                 phys = <&combphy1_ps PHY_TYPE_PCIE>;
 217                 phy-names = "pcie-phy";
 218                 power-domains = <&power RK3588_PD_PCIE>;
 219                 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
 220                          <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
 221                          <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
 222                 reg = <0xa 0x40800000 0x0 0x00400000>,
 223                       <0x0 0xfe170000 0x0 0x00010000>,
 224                       <0x0 0xf2000000 0x0 0x00100000>;
 225                 reg-names = "dbi", "apb", "config";
 226                 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
 227                 reset-names = "pwr", "pipe";
 228                 #address-cells = <3>;
 229                 #size-cells = <2>;
 230                 status = "disabled";
 231
 232                 pcie2x1l0_intc: legacy-interrupt-controller {
 233                         interrupt-controller;
 234                         #address-cells = <0>;
 235                         #interrupt-cells = <1>;
 236                         interrupt-parent = <&gic>;
 237                         interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
 238                 };
 239         };
 240
 241         gmac0: ethernet@fe1b0000 {
 242                 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
 243                 reg = <0x0 0xfe1b0000 0x0 0x10000>;
 244                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
 245                              <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 246                 interrupt-names = "macirq", "eth_wake_irq";
 247                 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
 248                          <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
 249                          <&cru CLK_GMAC0_PTP_REF>;
 250                 clock-names = "stmmaceth", "clk_mac_ref",
 251                               "pclk_mac", "aclk_mac",
 252                               "ptp_ref";
 253                 power-domains = <&power RK3588_PD_GMAC>;
 254                 resets = <&cru SRST_A_GMAC0>;
 255                 reset-names = "stmmaceth";
 256                 rockchip,grf = <&sys_grf>;
 257                 rockchip,php-grf = <&php_grf>;
 258                 snps,axi-config = <&gmac0_stmmac_axi_setup>;
 259                 snps,mixed-burst;
 260                 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
 261                 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
 262                 snps,tso;
 263                 status = "disabled";
 264
 265                 mdio0: mdio {
 266                         compatible = "snps,dwmac-mdio";
 267                         #address-cells = <0x1>;
 268                         #size-cells = <0x0>;
 269                 };
 270
 271                 gmac0_stmmac_axi_setup: stmmac-axi-config {
 272                         snps,blen = <0 0 0 0 16 8 4>;
 273                         snps,wr_osr_lmt = <4>;
 274                         snps,rd_osr_lmt = <8>;
 275                 };
 276
 277                 gmac0_mtl_rx_setup: rx-queues-config {
 278                         snps,rx-queues-to-use = <2>;
 279                         queue0 {};
 280                         queue1 {};
 281                 };
 282
 283                 gmac0_mtl_tx_setup: tx-queues-config {
 284                         snps,tx-queues-to-use = <2>;
 285                         queue0 {};
 286                         queue1 {};
 287                 };
 288         };
 289
 290         sata1: sata@fe220000 {
 291                 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
 292                 reg = <0 0xfe220000 0 0x1000>;
 293                 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
 294                 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
 295                          <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
 296                          <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
 297                 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
 298                 ports-implemented = <0x1>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 status = "disabled";
 302
 303                 sata-port@0 {
 304                         reg = <0>;
 305                         hba-port-cap = <HBA_PORT_FBSCP>;
 306                         phys = <&combphy1_ps PHY_TYPE_SATA>;
 307                         phy-names = "sata-phy";
 308                         snps,rx-ts-max = <32>;
 309                         snps,tx-ts-max = <32>;
 310                 };
 311         };
 312
 313         combphy1_ps: phy@fee10000 {
 314                 compatible = "rockchip,rk3588-naneng-combphy";
 315                 reg = <0x0 0xfee10000 0x0 0x100>;
 316                 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
 317                          <&cru PCLK_PHP_ROOT>;
 318                 clock-names = "ref", "apb", "pipe";
 319                 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
 320                 assigned-clock-rates = <100000000>;
 321                 #phy-cells = <1>;
 322                 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
 323                 reset-names = "phy", "apb";
 324                 rockchip,pipe-grf = <&php_grf>;
 325                 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
 326                 status = "disabled";
 327         };
 328
 329         pcie30phy: phy@fee80000 {
 330                 compatible = "rockchip,rk3588-pcie3-phy";
 331                 reg = <0x0 0xfee80000 0x0 0x20000>;
 332                 #phy-cells = <0>;
 333                 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
 334                 clock-names = "pclk";
 335                 resets = <&cru SRST_PCIE30_PHY>;
 336                 reset-names = "phy";
 337                 rockchip,pipe-grf = <&php_grf>;
 338                 rockchip,phy-grf = <&pcie30_phy_grf>;
 339                 status = "disabled";
 340         };
 341 };