1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
16 clk32k_out1: clk32k-out1 {
19 <2 RK_PC5 1 &pcfg_pull_none>;
26 eth0_pins: eth0-pins {
28 /* eth0_refclko_25m */
29 <2 RK_PC3 1 &pcfg_pull_none>;
36 fspim1_pins: fspim1-pins {
39 <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
41 <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
43 <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
45 <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
47 <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
49 <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
53 fspim1_cs1: fspim1-cs1 {
56 <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
62 gmac0_miim: gmac0-miim {
65 <4 RK_PC4 1 &pcfg_pull_none>,
67 <4 RK_PC5 1 &pcfg_pull_none>;
71 gmac0_clkinout: gmac0-clkinout {
74 <4 RK_PC3 1 &pcfg_pull_none>;
78 gmac0_rx_bus2: gmac0-rx-bus2 {
81 <2 RK_PC1 1 &pcfg_pull_none>,
83 <2 RK_PC2 1 &pcfg_pull_none>,
85 <4 RK_PC2 1 &pcfg_pull_none>;
89 gmac0_tx_bus2: gmac0-tx-bus2 {
92 <2 RK_PB6 1 &pcfg_pull_none>,
94 <2 RK_PB7 1 &pcfg_pull_none>,
96 <2 RK_PC0 1 &pcfg_pull_none>;
100 gmac0_rgmii_clk: gmac0-rgmii-clk {
103 <2 RK_PB0 1 &pcfg_pull_none>,
105 <2 RK_PB3 1 &pcfg_pull_none>;
109 gmac0_rgmii_bus: gmac0-rgmii-bus {
112 <2 RK_PA6 1 &pcfg_pull_none>,
114 <2 RK_PA7 1 &pcfg_pull_none>,
116 <2 RK_PB1 1 &pcfg_pull_none>,
118 <2 RK_PB2 1 &pcfg_pull_none>;
122 gmac0_ppsclk: gmac0-ppsclk {
125 <2 RK_PC4 1 &pcfg_pull_none>;
129 gmac0_ppstring: gmac0-ppstring {
132 <2 RK_PB5 1 &pcfg_pull_none>;
136 gmac0_ptp_refclk: gmac0-ptp-refclk {
138 /* gmac0_ptp_refclk */
139 <2 RK_PB4 1 &pcfg_pull_none>;
143 gmac0_txer: gmac0-txer {
146 <4 RK_PC6 1 &pcfg_pull_none>;
153 hdmim0_tx1_cec: hdmim0-tx1-cec {
156 <2 RK_PC4 4 &pcfg_pull_none>;
160 hdmim0_tx1_scl: hdmim0-tx1-scl {
163 <2 RK_PB5 4 &pcfg_pull_none>;
167 hdmim0_tx1_sda: hdmim0-tx1-sda {
170 <2 RK_PB4 4 &pcfg_pull_none>;
176 i2c0m1_xfer: i2c0m1-xfer {
179 <4 RK_PC5 9 &pcfg_pull_none_smt>,
181 <4 RK_PC6 9 &pcfg_pull_none_smt>;
187 i2c2m1_xfer: i2c2m1-xfer {
190 <2 RK_PC1 9 &pcfg_pull_none_smt>,
192 <2 RK_PC0 9 &pcfg_pull_none_smt>;
198 i2c3m3_xfer: i2c3m3-xfer {
201 <2 RK_PB2 9 &pcfg_pull_none_smt>,
203 <2 RK_PB3 9 &pcfg_pull_none_smt>;
209 i2c4m1_xfer: i2c4m1-xfer {
212 <2 RK_PB5 9 &pcfg_pull_none_smt>,
214 <2 RK_PB4 9 &pcfg_pull_none_smt>;
220 i2c5m4_xfer: i2c5m4-xfer {
223 <2 RK_PB6 9 &pcfg_pull_none_smt>,
225 <2 RK_PB7 9 &pcfg_pull_none_smt>;
231 i2c6m2_xfer: i2c6m2-xfer {
234 <2 RK_PC3 9 &pcfg_pull_none_smt>,
236 <2 RK_PC2 9 &pcfg_pull_none_smt>;
242 i2c7m1_xfer: i2c7m1-xfer {
245 <4 RK_PC3 9 &pcfg_pull_none_smt>,
247 <4 RK_PC4 9 &pcfg_pull_none_smt>;
253 i2c8m1_xfer: i2c8m1-xfer {
256 <2 RK_PB0 9 &pcfg_pull_none_smt>,
258 <2 RK_PB1 9 &pcfg_pull_none_smt>;
264 i2s2m0_lrck: i2s2m0-lrck {
267 <2 RK_PC0 2 &pcfg_pull_none>;
271 i2s2m0_mclk: i2s2m0-mclk {
274 <2 RK_PB6 2 &pcfg_pull_none>;
278 i2s2m0_sclk: i2s2m0-sclk {
281 <2 RK_PB7 2 &pcfg_pull_none>;
285 i2s2m0_sdi: i2s2m0-sdi {
288 <2 RK_PC3 2 &pcfg_pull_none>;
292 i2s2m0_sdo: i2s2m0-sdo {
295 <4 RK_PC3 2 &pcfg_pull_none>;
301 pwm2m2_pins: pwm2m2-pins {
304 <4 RK_PC2 11 &pcfg_pull_none>;
310 pwm4m1_pins: pwm4m1-pins {
313 <4 RK_PC3 11 &pcfg_pull_none>;
319 pwm5m2_pins: pwm5m2-pins {
322 <4 RK_PC4 11 &pcfg_pull_none>;
328 pwm6m2_pins: pwm6m2-pins {
331 <4 RK_PC5 11 &pcfg_pull_none>;
337 pwm7m3_pins: pwm7m3-pins {
340 <4 RK_PC6 11 &pcfg_pull_none>;
346 sdiom0_pins: sdiom0-pins {
349 <2 RK_PB3 2 &pcfg_pull_none>,
351 <2 RK_PB2 2 &pcfg_pull_none>,
353 <2 RK_PA6 2 &pcfg_pull_none>,
355 <2 RK_PA7 2 &pcfg_pull_none>,
357 <2 RK_PB0 2 &pcfg_pull_none>,
359 <2 RK_PB1 2 &pcfg_pull_none>;
365 spi1m0_pins: spi1m0-pins {
368 <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
370 <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
372 <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
376 spi1m0_cs0: spi1m0-cs0 {
379 <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
383 spi1m0_cs1: spi1m0-cs1 {
386 <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
392 spi3m0_pins: spi3m0-pins {
395 <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
397 <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
399 <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
403 spi3m0_cs0: spi3m0-cs0 {
406 <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
410 spi3m0_cs1: spi3m0-cs1 {
413 <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
419 uart1m0_xfer: uart1m0-xfer {
422 <2 RK_PB6 10 &pcfg_pull_up>,
424 <2 RK_PB7 10 &pcfg_pull_up>;
428 uart1m0_ctsn: uart1m0-ctsn {
431 <2 RK_PC1 10 &pcfg_pull_none>;
435 uart1m0_rtsn: uart1m0-rtsn {
438 <2 RK_PC0 10 &pcfg_pull_none>;
444 uart6m0_xfer: uart6m0-xfer {
447 <2 RK_PA6 10 &pcfg_pull_up>,
449 <2 RK_PA7 10 &pcfg_pull_up>;
453 uart6m0_ctsn: uart6m0-ctsn {
456 <2 RK_PB1 10 &pcfg_pull_none>;
460 uart6m0_rtsn: uart6m0-rtsn {
463 <2 RK_PB0 10 &pcfg_pull_none>;
469 uart7m0_xfer: uart7m0-xfer {
472 <2 RK_PB4 10 &pcfg_pull_up>,
474 <2 RK_PB5 10 &pcfg_pull_up>;
478 uart7m0_ctsn: uart7m0-ctsn {
481 <4 RK_PC6 10 &pcfg_pull_none>;
485 uart7m0_rtsn: uart7m0-rtsn {
488 <4 RK_PC2 10 &pcfg_pull_none>;
494 uart9m0_xfer: uart9m0-xfer {
497 <2 RK_PC4 10 &pcfg_pull_up>,
499 <2 RK_PC2 10 &pcfg_pull_up>;
503 uart9m0_ctsn: uart9m0-ctsn {
506 <4 RK_PC5 10 &pcfg_pull_none>;
510 uart9m0_rtsn: uart9m0-rtsn {
513 <4 RK_PC4 10 &pcfg_pull_none>;