arch/arm64/boot/dts/rockchip/rk356x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rk3568-cru.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/phy/phy.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3568-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 gpio0 = &gpio0;
  22                 gpio1 = &gpio1;
  23                 gpio2 = &gpio2;
  24                 gpio3 = &gpio3;
  25                 gpio4 = &gpio4;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 serial5 = &uart5;
  38                 serial6 = &uart6;
  39                 serial7 = &uart7;
  40                 serial8 = &uart8;
  41                 serial9 = &uart9;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45                 spi3 = &spi3;
  46         };
  47
  48         cpus {
  49                 #address-cells = <2>;
  50                 #size-cells = <0>;
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a55";
  55                         reg = <0x0 0x0>;
  56                         clocks = <&scmi_clk 0>;
  57                         #cooling-cells = <2>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu1: cpu@100 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a55";
  65                         reg = <0x0 0x100>;
  66                         #cooling-cells = <2>;
  67                         enable-method = "psci";
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                 };
  70
  71                 cpu2: cpu@200 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x0 0x200>;
  75                         #cooling-cells = <2>;
  76                         enable-method = "psci";
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                 };
  79
  80                 cpu3: cpu@300 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a55";
  83                         reg = <0x0 0x300>;
  84                         #cooling-cells = <2>;
  85                         enable-method = "psci";
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88         };
  89
  90         cpu0_opp_table: opp-table-0 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp-408000000 {
  95                         opp-hz = /bits/ 64 <408000000>;
  96                         opp-microvolt = <900000 900000 1150000>;
  97                         clock-latency-ns = <40000>;
  98                 };
  99
 100                 opp-600000000 {
 101                         opp-hz = /bits/ 64 <600000000>;
 102                         opp-microvolt = <900000 900000 1150000>;
 103                 };
 104
 105                 opp-816000000 {
 106                         opp-hz = /bits/ 64 <816000000>;
 107                         opp-microvolt = <900000 900000 1150000>;
 108                         opp-suspend;
 109                 };
 110
 111                 opp-1104000000 {
 112                         opp-hz = /bits/ 64 <1104000000>;
 113                         opp-microvolt = <900000 900000 1150000>;
 114                 };
 115
 116                 opp-1416000000 {
 117                         opp-hz = /bits/ 64 <1416000000>;
 118                         opp-microvolt = <900000 900000 1150000>;
 119                 };
 120
 121                 opp-1608000000 {
 122                         opp-hz = /bits/ 64 <1608000000>;
 123                         opp-microvolt = <975000 975000 1150000>;
 124                 };
 125
 126                 opp-1800000000 {
 127                         opp-hz = /bits/ 64 <1800000000>;
 128                         opp-microvolt = <1050000 1050000 1150000>;
 129                 };
 130         };
 131
 132         display_subsystem: display-subsystem {
 133                 compatible = "rockchip,display-subsystem";
 134                 ports = <&vop_out>;
 135         };
 136
 137         firmware {
 138                 scmi: scmi {
 139                         compatible = "arm,scmi-smc";
 140                         arm,smc-id = <0x82000010>;
 141                         shmem = <&scmi_shmem>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144
 145                         scmi_clk: protocol@14 {
 146                                 reg = <0x14>;
 147                                 #clock-cells = <1>;
 148                         };
 149                 };
 150         };
 151
 152         gpu_opp_table: opp-table-1 {
 153                 compatible = "operating-points-v2";
 154
 155                 opp-200000000 {
 156                         opp-hz = /bits/ 64 <200000000>;
 157                         opp-microvolt = <825000>;
 158                 };
 159
 160                 opp-300000000 {
 161                         opp-hz = /bits/ 64 <300000000>;
 162                         opp-microvolt = <825000>;
 163                 };
 164
 165                 opp-400000000 {
 166                         opp-hz = /bits/ 64 <400000000>;
 167                         opp-microvolt = <825000>;
 168                 };
 169
 170                 opp-600000000 {
 171                         opp-hz = /bits/ 64 <600000000>;
 172                         opp-microvolt = <825000>;
 173                 };
 174
 175                 opp-700000000 {
 176                         opp-hz = /bits/ 64 <700000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179
 180                 opp-800000000 {
 181                         opp-hz = /bits/ 64 <800000000>;
 182                         opp-microvolt = <1000000>;
 183                 };
 184         };
 185
 186         hdmi_sound: hdmi-sound {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "HDMI";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,mclk-fs = <256>;
 191                 status = "disabled";
 192
 193                 simple-audio-card,codec {
 194                         sound-dai = <&hdmi>;
 195                 };
 196
 197                 simple-audio-card,cpu {
 198                         sound-dai = <&i2s0_8ch>;
 199                 };
 200         };
 201
 202         pmu {
 203                 compatible = "arm,cortex-a55-pmu";
 204                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 208                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 209         };
 210
 211         psci {
 212                 compatible = "arm,psci-1.0";
 213                 method = "smc";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 222                 arm,no-tick-in-suspend;
 223         };
 224
 225         xin24m: xin24m {
 226                 compatible = "fixed-clock";
 227                 clock-frequency = <24000000>;
 228                 clock-output-names = "xin24m";
 229                 #clock-cells = <0>;
 230         };
 231
 232         xin32k: xin32k {
 233                 compatible = "fixed-clock";
 234                 clock-frequency = <32768>;
 235                 clock-output-names = "xin32k";
 236                 pinctrl-0 = <&clk32k_out0>;
 237                 pinctrl-names = "default";
 238                 #clock-cells = <0>;
 239         };
 240
 241         sram@10f000 {
 242                 compatible = "mmio-sram";
 243                 reg = <0x0 0x0010f000 0x0 0x100>;
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246                 ranges = <0 0x0 0x0010f000 0x100>;
 247
 248                 scmi_shmem: sram@0 {
 249                         compatible = "arm,scmi-shmem";
 250                         reg = <0x0 0x100>;
 251                 };
 252         };
 253
 254         sata1: sata@fc400000 {
 255                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 256                 reg = <0 0xfc400000 0 0x1000>;
 257                 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
 258                          <&cru CLK_SATA1_RXOOB>;
 259                 clock-names = "sata", "pmalive", "rxoob";
 260                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 261                 phys = <&combphy1 PHY_TYPE_SATA>;
 262                 phy-names = "sata-phy";
 263                 ports-implemented = <0x1>;
 264                 power-domains = <&power RK3568_PD_PIPE>;
 265                 status = "disabled";
 266         };
 267
 268         sata2: sata@fc800000 {
 269                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 270                 reg = <0 0xfc800000 0 0x1000>;
 271                 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
 272                          <&cru CLK_SATA2_RXOOB>;
 273                 clock-names = "sata", "pmalive", "rxoob";
 274                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 275                 phys = <&combphy2 PHY_TYPE_SATA>;
 276                 phy-names = "sata-phy";
 277                 ports-implemented = <0x1>;
 278                 power-domains = <&power RK3568_PD_PIPE>;
 279                 status = "disabled";
 280         };
 281
 282         usb_host0_xhci: usb@fcc00000 {
 283                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 284                 reg = <0x0 0xfcc00000 0x0 0x400000>;
 285                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
 287                          <&cru ACLK_USB3OTG0>;
 288                 clock-names = "ref_clk", "suspend_clk",
 289                               "bus_clk";
 290                 dr_mode = "otg";
 291                 phy_type = "utmi_wide";
 292                 power-domains = <&power RK3568_PD_PIPE>;
 293                 resets = <&cru SRST_USB3OTG0>;
 294                 snps,dis_u2_susphy_quirk;
 295                 status = "disabled";
 296         };
 297
 298         usb_host1_xhci: usb@fd000000 {
 299                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 300                 reg = <0x0 0xfd000000 0x0 0x400000>;
 301                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
 303                          <&cru ACLK_USB3OTG1>;
 304                 clock-names = "ref_clk", "suspend_clk",
 305                               "bus_clk";
 306                 dr_mode = "host";
 307                 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
 308                 phy-names = "usb2-phy", "usb3-phy";
 309                 phy_type = "utmi_wide";
 310                 power-domains = <&power RK3568_PD_PIPE>;
 311                 resets = <&cru SRST_USB3OTG1>;
 312                 snps,dis_u2_susphy_quirk;
 313                 status = "disabled";
 314         };
 315
 316         gic: interrupt-controller@fd400000 {
 317                 compatible = "arm,gic-v3";
 318                 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
 319                       <0x0 0xfd460000 0 0x80000>; /* GICR */
 320                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 321                 interrupt-controller;
 322                 #interrupt-cells = <3>;
 323                 mbi-alias = <0x0 0xfd410000>;
 324                 mbi-ranges = <296 24>;
 325                 msi-controller;
 326         };
 327
 328         usb_host0_ehci: usb@fd800000 {
 329                 compatible = "generic-ehci";
 330                 reg = <0x0 0xfd800000 0x0 0x40000>;
 331                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 333                          <&cru PCLK_USB>;
 334                 phys = <&usb2phy1_otg>;
 335                 phy-names = "usb";
 336                 status = "disabled";
 337         };
 338
 339         usb_host0_ohci: usb@fd840000 {
 340                 compatible = "generic-ohci";
 341                 reg = <0x0 0xfd840000 0x0 0x40000>;
 342                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 344                          <&cru PCLK_USB>;
 345                 phys = <&usb2phy1_otg>;
 346                 phy-names = "usb";
 347                 status = "disabled";
 348         };
 349
 350         usb_host1_ehci: usb@fd880000 {
 351                 compatible = "generic-ehci";
 352                 reg = <0x0 0xfd880000 0x0 0x40000>;
 353                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 355                          <&cru PCLK_USB>;
 356                 phys = <&usb2phy1_host>;
 357                 phy-names = "usb";
 358                 status = "disabled";
 359         };
 360
 361         usb_host1_ohci: usb@fd8c0000 {
 362                 compatible = "generic-ohci";
 363                 reg = <0x0 0xfd8c0000 0x0 0x40000>;
 364                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 366                          <&cru PCLK_USB>;
 367                 phys = <&usb2phy1_host>;
 368                 phy-names = "usb";
 369                 status = "disabled";
 370         };
 371
 372         pmugrf: syscon@fdc20000 {
 373                 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
 374                 reg = <0x0 0xfdc20000 0x0 0x10000>;
 375
 376                 pmu_io_domains: io-domains {
 377                         compatible = "rockchip,rk3568-pmu-io-voltage-domain";
 378                         status = "disabled";
 379                 };
 380         };
 381
 382         pipegrf: syscon@fdc50000 {
 383                 reg = <0x0 0xfdc50000 0x0 0x1000>;
 384         };
 385
 386         grf: syscon@fdc60000 {
 387                 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 388                 reg = <0x0 0xfdc60000 0x0 0x10000>;
 389         };
 390
 391         pipe_phy_grf1: syscon@fdc80000 {
 392                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 393                 reg = <0x0 0xfdc80000 0x0 0x1000>;
 394         };
 395
 396         pipe_phy_grf2: syscon@fdc90000 {
 397                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 398                 reg = <0x0 0xfdc90000 0x0 0x1000>;
 399         };
 400
 401         usb2phy0_grf: syscon@fdca0000 {
 402                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 403                 reg = <0x0 0xfdca0000 0x0 0x8000>;
 404         };
 405
 406         usb2phy1_grf: syscon@fdca8000 {
 407                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 408                 reg = <0x0 0xfdca8000 0x0 0x8000>;
 409         };
 410
 411         pmucru: clock-controller@fdd00000 {
 412                 compatible = "rockchip,rk3568-pmucru";
 413                 reg = <0x0 0xfdd00000 0x0 0x1000>;
 414                 #clock-cells = <1>;
 415                 #reset-cells = <1>;
 416         };
 417
 418         cru: clock-controller@fdd20000 {
 419                 compatible = "rockchip,rk3568-cru";
 420                 reg = <0x0 0xfdd20000 0x0 0x1000>;
 421                 clocks = <&xin24m>;
 422                 clock-names = "xin24m";
 423                 #clock-cells = <1>;
 424                 #reset-cells = <1>;
 425                 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
 426                 assigned-clock-rates = <1200000000>, <200000000>;
 427                 rockchip,grf = <&grf>;
 428         };
 429
 430         i2c0: i2c@fdd40000 {
 431                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 432                 reg = <0x0 0xfdd40000 0x0 0x1000>;
 433                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
 435                 clock-names = "i2c", "pclk";
 436                 pinctrl-0 = <&i2c0_xfer>;
 437                 pinctrl-names = "default";
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 status = "disabled";
 441         };
 442
 443         uart0: serial@fdd50000 {
 444                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 445                 reg = <0x0 0xfdd50000 0x0 0x100>;
 446                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 dmas = <&dmac0 0>, <&dmac0 1>;
 450                 pinctrl-0 = <&uart0_xfer>;
 451                 pinctrl-names = "default";
 452                 reg-io-width = <4>;
 453                 reg-shift = <2>;
 454                 status = "disabled";
 455         };
 456
 457         pwm0: pwm@fdd70000 {
 458                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 459                 reg = <0x0 0xfdd70000 0x0 0x10>;
 460                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 461                 clock-names = "pwm", "pclk";
 462                 pinctrl-0 = <&pwm0m0_pins>;
 463                 pinctrl-names = "default";
 464                 #pwm-cells = <3>;
 465                 status = "disabled";
 466         };
 467
 468         pwm1: pwm@fdd70010 {
 469                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 470                 reg = <0x0 0xfdd70010 0x0 0x10>;
 471                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 472                 clock-names = "pwm", "pclk";
 473                 pinctrl-0 = <&pwm1m0_pins>;
 474                 pinctrl-names = "default";
 475                 #pwm-cells = <3>;
 476                 status = "disabled";
 477         };
 478
 479         pwm2: pwm@fdd70020 {
 480                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 481                 reg = <0x0 0xfdd70020 0x0 0x10>;
 482                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 483                 clock-names = "pwm", "pclk";
 484                 pinctrl-0 = <&pwm2m0_pins>;
 485                 pinctrl-names = "default";
 486                 #pwm-cells = <3>;
 487                 status = "disabled";
 488         };
 489
 490         pwm3: pwm@fdd70030 {
 491                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 492                 reg = <0x0 0xfdd70030 0x0 0x10>;
 493                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 494                 clock-names = "pwm", "pclk";
 495                 pinctrl-0 = <&pwm3_pins>;
 496                 pinctrl-names = "default";
 497                 #pwm-cells = <3>;
 498                 status = "disabled";
 499         };
 500
 501         pmu: power-management@fdd90000 {
 502                 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
 503                 reg = <0x0 0xfdd90000 0x0 0x1000>;
 504
 505                 power: power-controller {
 506                         compatible = "rockchip,rk3568-power-controller";
 507                         #power-domain-cells = <1>;
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510
 511                         /* These power domains are grouped by VD_GPU */
 512                         power-domain@RK3568_PD_GPU {
 513                                 reg = <RK3568_PD_GPU>;
 514                                 clocks = <&cru ACLK_GPU_PRE>,
 515                                          <&cru PCLK_GPU_PRE>;
 516                                 pm_qos = <&qos_gpu>;
 517                                 #power-domain-cells = <0>;
 518                         };
 519
 520                         /* These power domains are grouped by VD_LOGIC */
 521                         power-domain@RK3568_PD_VI {
 522                                 reg = <RK3568_PD_VI>;
 523                                 clocks = <&cru HCLK_VI>,
 524                                          <&cru PCLK_VI>;
 525                                 pm_qos = <&qos_isp>,
 526                                          <&qos_vicap0>,
 527                                          <&qos_vicap1>;
 528                                 #power-domain-cells = <0>;
 529                         };
 530
 531                         power-domain@RK3568_PD_VO {
 532                                 reg = <RK3568_PD_VO>;
 533                                 clocks = <&cru HCLK_VO>,
 534                                          <&cru PCLK_VO>,
 535                                          <&cru ACLK_VOP_PRE>;
 536                                 pm_qos = <&qos_hdcp>,
 537                                          <&qos_vop_m0>,
 538                                          <&qos_vop_m1>;
 539                                 #power-domain-cells = <0>;
 540                         };
 541
 542                         power-domain@RK3568_PD_RGA {
 543                                 reg = <RK3568_PD_RGA>;
 544                                 clocks = <&cru HCLK_RGA_PRE>,
 545                                          <&cru PCLK_RGA_PRE>;
 546                                 pm_qos = <&qos_ebc>,
 547                                          <&qos_iep>,
 548                                          <&qos_jpeg_dec>,
 549                                          <&qos_jpeg_enc>,
 550                                          <&qos_rga_rd>,
 551                                          <&qos_rga_wr>;
 552                                 #power-domain-cells = <0>;
 553                         };
 554
 555                         power-domain@RK3568_PD_VPU {
 556                                 reg = <RK3568_PD_VPU>;
 557                                 clocks = <&cru HCLK_VPU_PRE>;
 558                                 pm_qos = <&qos_vpu>;
 559                                 #power-domain-cells = <0>;
 560                         };
 561
 562                         power-domain@RK3568_PD_RKVDEC {
 563                                 clocks = <&cru HCLK_RKVDEC_PRE>;
 564                                 reg = <RK3568_PD_RKVDEC>;
 565                                 pm_qos = <&qos_rkvdec>;
 566                                 #power-domain-cells = <0>;
 567                         };
 568
 569                         power-domain@RK3568_PD_RKVENC {
 570                                 reg = <RK3568_PD_RKVENC>;
 571                                 clocks = <&cru HCLK_RKVENC_PRE>;
 572                                 pm_qos = <&qos_rkvenc_rd_m0>,
 573                                          <&qos_rkvenc_rd_m1>,
 574                                          <&qos_rkvenc_wr_m0>;
 575                                 #power-domain-cells = <0>;
 576                         };
 577                 };
 578         };
 579
 580         gpu: gpu@fde60000 {
 581                 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
 582                 reg = <0x0 0xfde60000 0x0 0x4000>;
 583                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 584                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 585                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 586                 interrupt-names = "job", "mmu", "gpu";
 587                 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
 588                 clock-names = "gpu", "bus";
 589                 #cooling-cells = <2>;
 590                 operating-points-v2 = <&gpu_opp_table>;
 591                 power-domains = <&power RK3568_PD_GPU>;
 592                 status = "disabled";
 593         };
 594
 595         vpu: video-codec@fdea0400 {
 596                 compatible = "rockchip,rk3568-vpu";
 597                 reg = <0x0 0xfdea0000 0x0 0x800>;
 598                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 599                 interrupt-names = "vdpu";
 600                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 601                 clock-names = "aclk", "hclk";
 602                 iommus = <&vdpu_mmu>;
 603                 power-domains = <&power RK3568_PD_VPU>;
 604         };
 605
 606         vdpu_mmu: iommu@fdea0800 {
 607                 compatible = "rockchip,rk3568-iommu";
 608                 reg = <0x0 0xfdea0800 0x0 0x40>;
 609                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 610                 clock-names = "aclk", "iface";
 611                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 612                 power-domains = <&power RK3568_PD_VPU>;
 613                 #iommu-cells = <0>;
 614         };
 615
 616         vepu: video-codec@fdee0000 {
 617                 compatible = "rockchip,rk3568-vepu";
 618                 reg = <0x0 0xfdee0000 0x0 0x800>;
 619                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 621                 clock-names = "aclk", "hclk";
 622                 iommus = <&vepu_mmu>;
 623                 power-domains = <&power RK3568_PD_RGA>;
 624         };
 625
 626         vepu_mmu: iommu@fdee0800 {
 627                 compatible = "rockchip,rk3568-iommu";
 628                 reg = <0x0 0xfdee0800 0x0 0x40>;
 629                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 631                 clock-names = "aclk", "iface";
 632                 power-domains = <&power RK3568_PD_RGA>;
 633                 #iommu-cells = <0>;
 634         };
 635
 636         sdmmc2: mmc@fe000000 {
 637                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 638                 reg = <0x0 0xfe000000 0x0 0x4000>;
 639                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
 641                          <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
 642                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 643                 fifo-depth = <0x100>;
 644                 max-frequency = <150000000>;
 645                 resets = <&cru SRST_SDMMC2>;
 646                 reset-names = "reset";
 647                 status = "disabled";
 648         };
 649
 650         gmac1: ethernet@fe010000 {
 651                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
 652                 reg = <0x0 0xfe010000 0x0 0x10000>;
 653                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 654                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 655                 interrupt-names = "macirq", "eth_wake_irq";
 656                 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
 657                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
 658                          <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
 659                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
 660                 clock-names = "stmmaceth", "mac_clk_rx",
 661                               "mac_clk_tx", "clk_mac_refout",
 662                               "aclk_mac", "pclk_mac",
 663                               "clk_mac_speed", "ptp_ref";
 664                 resets = <&cru SRST_A_GMAC1>;
 665                 reset-names = "stmmaceth";
 666                 rockchip,grf = <&grf>;
 667                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
 668                 snps,mixed-burst;
 669                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
 670                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
 671                 snps,tso;
 672                 status = "disabled";
 673
 674                 mdio1: mdio {
 675                         compatible = "snps,dwmac-mdio";
 676                         #address-cells = <0x1>;
 677                         #size-cells = <0x0>;
 678                 };
 679
 680                 gmac1_stmmac_axi_setup: stmmac-axi-config {
 681                         snps,blen = <0 0 0 0 16 8 4>;
 682                         snps,rd_osr_lmt = <8>;
 683                         snps,wr_osr_lmt = <4>;
 684                 };
 685
 686                 gmac1_mtl_rx_setup: rx-queues-config {
 687                         snps,rx-queues-to-use = <1>;
 688                         queue0 {};
 689                 };
 690
 691                 gmac1_mtl_tx_setup: tx-queues-config {
 692                         snps,tx-queues-to-use = <1>;
 693                         queue0 {};
 694                 };
 695         };
 696
 697         vop: vop@fe040000 {
 698                 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
 699                 reg-names = "vop", "gamma-lut";
 700                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 701                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
 702                          <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
 703                 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
 704                 iommus = <&vop_mmu>;
 705                 power-domains = <&power RK3568_PD_VO>;
 706                 rockchip,grf = <&grf>;
 707                 status = "disabled";
 708
 709                 vop_out: ports {
 710                         #address-cells = <1>;
 711                         #size-cells = <0>;
 712
 713                         vp0: port@0 {
 714                                 reg = <0>;
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717                         };
 718
 719                         vp1: port@1 {
 720                                 reg = <1>;
 721                                 #address-cells = <1>;
 722                                 #size-cells = <0>;
 723                         };
 724
 725                         vp2: port@2 {
 726                                 reg = <2>;
 727                                 #address-cells = <1>;
 728                                 #size-cells = <0>;
 729                         };
 730                 };
 731         };
 732
 733         vop_mmu: iommu@fe043e00 {
 734                 compatible = "rockchip,rk3568-iommu";
 735                 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
 736                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 738                 clock-names = "aclk", "iface";
 739                 #iommu-cells = <0>;
 740                 status = "disabled";
 741         };
 742
 743         dsi0: dsi@fe060000 {
 744                 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 745                 reg = <0x00 0xfe060000 0x00 0x10000>;
 746                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 747                 clock-names = "pclk", "hclk";
 748                 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
 749                 phy-names = "dphy";
 750                 phys = <&dsi_dphy0>;
 751                 power-domains = <&power RK3568_PD_VO>;
 752                 reset-names = "apb";
 753                 resets = <&cru SRST_P_DSITX_0>;
 754                 rockchip,grf = <&grf>;
 755                 status = "disabled";
 756
 757                 ports {
 758                         #address-cells = <1>;
 759                         #size-cells = <0>;
 760
 761                         dsi0_in: port@0 {
 762                                 reg = <0>;
 763                         };
 764
 765                         dsi0_out: port@1 {
 766                                 reg = <1>;
 767                         };
 768                 };
 769         };
 770
 771         dsi1: dsi@fe070000 {
 772                 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 773                 reg = <0x0 0xfe070000 0x0 0x10000>;
 774                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 775                 clock-names = "pclk", "hclk";
 776                 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
 777                 phy-names = "dphy";
 778                 phys = <&dsi_dphy1>;
 779                 power-domains = <&power RK3568_PD_VO>;
 780                 reset-names = "apb";
 781                 resets = <&cru SRST_P_DSITX_1>;
 782                 rockchip,grf = <&grf>;
 783                 status = "disabled";
 784
 785                 ports {
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788
 789                         dsi1_in: port@0 {
 790                                 reg = <0>;
 791                         };
 792
 793                         dsi1_out: port@1 {
 794                                 reg = <1>;
 795                         };
 796                 };
 797         };
 798
 799         hdmi: hdmi@fe0a0000 {
 800                 compatible = "rockchip,rk3568-dw-hdmi";
 801                 reg = <0x0 0xfe0a0000 0x0 0x20000>;
 802                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 803                 clocks = <&cru PCLK_HDMI_HOST>,
 804                          <&cru CLK_HDMI_SFR>,
 805                          <&cru CLK_HDMI_CEC>,
 806                          <&pmucru CLK_HDMI_REF>,
 807                          <&cru HCLK_VO>;
 808                 clock-names = "iahb", "isfr", "cec", "ref";
 809                 pinctrl-names = "default";
 810                 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
 811                 power-domains = <&power RK3568_PD_VO>;
 812                 reg-io-width = <4>;
 813                 rockchip,grf = <&grf>;
 814                 #sound-dai-cells = <0>;
 815                 status = "disabled";
 816
 817                 ports {
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820
 821                         hdmi_in: port@0 {
 822                                 reg = <0>;
 823                         };
 824
 825                         hdmi_out: port@1 {
 826                                 reg = <1>;
 827                         };
 828                 };
 829         };
 830
 831         qos_gpu: qos@fe128000 {
 832                 compatible = "rockchip,rk3568-qos", "syscon";
 833                 reg = <0x0 0xfe128000 0x0 0x20>;
 834         };
 835
 836         qos_rkvenc_rd_m0: qos@fe138080 {
 837                 compatible = "rockchip,rk3568-qos", "syscon";
 838                 reg = <0x0 0xfe138080 0x0 0x20>;
 839         };
 840
 841         qos_rkvenc_rd_m1: qos@fe138100 {
 842                 compatible = "rockchip,rk3568-qos", "syscon";
 843                 reg = <0x0 0xfe138100 0x0 0x20>;
 844         };
 845
 846         qos_rkvenc_wr_m0: qos@fe138180 {
 847                 compatible = "rockchip,rk3568-qos", "syscon";
 848                 reg = <0x0 0xfe138180 0x0 0x20>;
 849         };
 850
 851         qos_isp: qos@fe148000 {
 852                 compatible = "rockchip,rk3568-qos", "syscon";
 853                 reg = <0x0 0xfe148000 0x0 0x20>;
 854         };
 855
 856         qos_vicap0: qos@fe148080 {
 857                 compatible = "rockchip,rk3568-qos", "syscon";
 858                 reg = <0x0 0xfe148080 0x0 0x20>;
 859         };
 860
 861         qos_vicap1: qos@fe148100 {
 862                 compatible = "rockchip,rk3568-qos", "syscon";
 863                 reg = <0x0 0xfe148100 0x0 0x20>;
 864         };
 865
 866         qos_vpu: qos@fe150000 {
 867                 compatible = "rockchip,rk3568-qos", "syscon";
 868                 reg = <0x0 0xfe150000 0x0 0x20>;
 869         };
 870
 871         qos_ebc: qos@fe158000 {
 872                 compatible = "rockchip,rk3568-qos", "syscon";
 873                 reg = <0x0 0xfe158000 0x0 0x20>;
 874         };
 875
 876         qos_iep: qos@fe158100 {
 877                 compatible = "rockchip,rk3568-qos", "syscon";
 878                 reg = <0x0 0xfe158100 0x0 0x20>;
 879         };
 880
 881         qos_jpeg_dec: qos@fe158180 {
 882                 compatible = "rockchip,rk3568-qos", "syscon";
 883                 reg = <0x0 0xfe158180 0x0 0x20>;
 884         };
 885
 886         qos_jpeg_enc: qos@fe158200 {
 887                 compatible = "rockchip,rk3568-qos", "syscon";
 888                 reg = <0x0 0xfe158200 0x0 0x20>;
 889         };
 890
 891         qos_rga_rd: qos@fe158280 {
 892                 compatible = "rockchip,rk3568-qos", "syscon";
 893                 reg = <0x0 0xfe158280 0x0 0x20>;
 894         };
 895
 896         qos_rga_wr: qos@fe158300 {
 897                 compatible = "rockchip,rk3568-qos", "syscon";
 898                 reg = <0x0 0xfe158300 0x0 0x20>;
 899         };
 900
 901         qos_npu: qos@fe180000 {
 902                 compatible = "rockchip,rk3568-qos", "syscon";
 903                 reg = <0x0 0xfe180000 0x0 0x20>;
 904         };
 905
 906         qos_pcie2x1: qos@fe190000 {
 907                 compatible = "rockchip,rk3568-qos", "syscon";
 908                 reg = <0x0 0xfe190000 0x0 0x20>;
 909         };
 910
 911         qos_sata1: qos@fe190280 {
 912                 compatible = "rockchip,rk3568-qos", "syscon";
 913                 reg = <0x0 0xfe190280 0x0 0x20>;
 914         };
 915
 916         qos_sata2: qos@fe190300 {
 917                 compatible = "rockchip,rk3568-qos", "syscon";
 918                 reg = <0x0 0xfe190300 0x0 0x20>;
 919         };
 920
 921         qos_usb3_0: qos@fe190380 {
 922                 compatible = "rockchip,rk3568-qos", "syscon";
 923                 reg = <0x0 0xfe190380 0x0 0x20>;
 924         };
 925
 926         qos_usb3_1: qos@fe190400 {
 927                 compatible = "rockchip,rk3568-qos", "syscon";
 928                 reg = <0x0 0xfe190400 0x0 0x20>;
 929         };
 930
 931         qos_rkvdec: qos@fe198000 {
 932                 compatible = "rockchip,rk3568-qos", "syscon";
 933                 reg = <0x0 0xfe198000 0x0 0x20>;
 934         };
 935
 936         qos_hdcp: qos@fe1a8000 {
 937                 compatible = "rockchip,rk3568-qos", "syscon";
 938                 reg = <0x0 0xfe1a8000 0x0 0x20>;
 939         };
 940
 941         qos_vop_m0: qos@fe1a8080 {
 942                 compatible = "rockchip,rk3568-qos", "syscon";
 943                 reg = <0x0 0xfe1a8080 0x0 0x20>;
 944         };
 945
 946         qos_vop_m1: qos@fe1a8100 {
 947                 compatible = "rockchip,rk3568-qos", "syscon";
 948                 reg = <0x0 0xfe1a8100 0x0 0x20>;
 949         };
 950
 951         pcie2x1: pcie@fe260000 {
 952                 compatible = "rockchip,rk3568-pcie";
 953                 reg = <0x3 0xc0000000 0x0 0x00400000>,
 954                       <0x0 0xfe260000 0x0 0x00010000>,
 955                       <0x0 0xf4000000 0x0 0x00100000>;
 956                 reg-names = "dbi", "apb", "config";
 957                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 958                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 959                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 960                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 961                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 962                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 963                 bus-range = <0x0 0xf>;
 964                 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
 965                          <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
 966                          <&cru CLK_PCIE20_AUX_NDFT>;
 967                 clock-names = "aclk_mst", "aclk_slv",
 968                               "aclk_dbi", "pclk", "aux";
 969                 device_type = "pci";
 970                 #interrupt-cells = <1>;
 971                 interrupt-map-mask = <0 0 0 7>;
 972                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 973                                 <0 0 0 2 &pcie_intc 1>,
 974                                 <0 0 0 3 &pcie_intc 2>,
 975                                 <0 0 0 4 &pcie_intc 3>;
 976                 linux,pci-domain = <0>;
 977                 num-ib-windows = <6>;
 978                 num-ob-windows = <2>;
 979                 max-link-speed = <2>;
 980                 msi-map = <0x0 &gic 0x0 0x1000>;
 981                 num-lanes = <1>;
 982                 phys = <&combphy2 PHY_TYPE_PCIE>;
 983                 phy-names = "pcie-phy";
 984                 power-domains = <&power RK3568_PD_PIPE>;
 985                 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
 986                          <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
 987                          <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
 988                 resets = <&cru SRST_PCIE20_POWERUP>;
 989                 reset-names = "pipe";
 990                 #address-cells = <3>;
 991                 #size-cells = <2>;
 992                 status = "disabled";
 993
 994                 pcie_intc: legacy-interrupt-controller {
 995                         #address-cells = <0>;
 996                         #interrupt-cells = <1>;
 997                         interrupt-controller;
 998                         interrupt-parent = <&gic>;
 999                         interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
1000                 };
1001         };
1002
1003         sdmmc0: mmc@fe2b0000 {
1004                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1005                 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1006                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1008                          <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1009                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1010                 fifo-depth = <0x100>;
1011                 max-frequency = <150000000>;
1012                 resets = <&cru SRST_SDMMC0>;
1013                 reset-names = "reset";
1014                 status = "disabled";
1015         };
1016
1017         sdmmc1: mmc@fe2c0000 {
1018                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1019                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1020                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1022                          <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1023                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1024                 fifo-depth = <0x100>;
1025                 max-frequency = <150000000>;
1026                 resets = <&cru SRST_SDMMC1>;
1027                 reset-names = "reset";
1028                 status = "disabled";
1029         };
1030
1031         sfc: spi@fe300000 {
1032                 compatible = "rockchip,sfc";
1033                 reg = <0x0 0xfe300000 0x0 0x4000>;
1034                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1035                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1036                 clock-names = "clk_sfc", "hclk_sfc";
1037                 pinctrl-0 = <&fspi_pins>;
1038                 pinctrl-names = "default";
1039                 status = "disabled";
1040         };
1041
1042         sdhci: mmc@fe310000 {
1043                 compatible = "rockchip,rk3568-dwcmshc";
1044                 reg = <0x0 0xfe310000 0x0 0x10000>;
1045                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1046                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1047                 assigned-clock-rates = <200000000>, <24000000>;
1048                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1049                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1050                          <&cru TCLK_EMMC>;
1051                 clock-names = "core", "bus", "axi", "block", "timer";
1052                 status = "disabled";
1053         };
1054
1055         spdif: spdif@fe460000 {
1056                 compatible = "rockchip,rk3568-spdif";
1057                 reg = <0x0 0xfe460000 0x0 0x1000>;
1058                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1059                 clock-names = "mclk", "hclk";
1060                 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1061                 dmas = <&dmac1 1>;
1062                 dma-names = "tx";
1063                 pinctrl-names = "default";
1064                 pinctrl-0 = <&spdifm0_tx>;
1065                 #sound-dai-cells = <0>;
1066                 status = "disabled";
1067         };
1068
1069         i2s0_8ch: i2s@fe400000 {
1070                 compatible = "rockchip,rk3568-i2s-tdm";
1071                 reg = <0x0 0xfe400000 0x0 0x1000>;
1072                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1073                 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1074                 assigned-clock-rates = <1188000000>, <1188000000>;
1075                 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1076                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1077                 dmas = <&dmac1 0>;
1078                 dma-names = "tx";
1079                 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1080                 reset-names = "tx-m", "rx-m";
1081                 rockchip,grf = <&grf>;
1082                 #sound-dai-cells = <0>;
1083                 status = "disabled";
1084         };
1085
1086         i2s1_8ch: i2s@fe410000 {
1087                 compatible = "rockchip,rk3568-i2s-tdm";
1088                 reg = <0x0 0xfe410000 0x0 0x1000>;
1089                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1090                 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1091                 assigned-clock-rates = <1188000000>, <1188000000>;
1092                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1093                          <&cru HCLK_I2S1_8CH>;
1094                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1095                 dmas = <&dmac1 3>, <&dmac1 2>;
1096                 dma-names = "rx", "tx";
1097                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1098                 reset-names = "tx-m", "rx-m";
1099                 rockchip,grf = <&grf>;
1100                 pinctrl-names = "default";
1101                 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1102                              &i2s1m0_lrcktx &i2s1m0_lrckrx
1103                              &i2s1m0_sdi0   &i2s1m0_sdi1
1104                              &i2s1m0_sdi2   &i2s1m0_sdi3
1105                              &i2s1m0_sdo0   &i2s1m0_sdo1
1106                              &i2s1m0_sdo2   &i2s1m0_sdo3>;
1107                 #sound-dai-cells = <0>;
1108                 status = "disabled";
1109         };
1110
1111         i2s3_2ch: i2s@fe430000 {
1112                 compatible = "rockchip,rk3568-i2s-tdm";
1113                 reg = <0x0 0xfe430000 0x0 0x1000>;
1114                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1115                 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1116                          <&cru HCLK_I2S3_2CH>;
1117                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1118                 dmas = <&dmac1 6>, <&dmac1 7>;
1119                 dma-names = "tx", "rx";
1120                 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1121                 reset-names = "tx-m", "rx-m";
1122                 rockchip,grf = <&grf>;
1123                 #sound-dai-cells = <0>;
1124                 status = "disabled";
1125         };
1126
1127         pdm: pdm@fe440000 {
1128                 compatible = "rockchip,rk3568-pdm";
1129                 reg = <0x0 0xfe440000 0x0 0x1000>;
1130                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1131                 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1132                 clock-names = "pdm_clk", "pdm_hclk";
1133                 dmas = <&dmac1 9>;
1134                 dma-names = "rx";
1135                 pinctrl-0 = <&pdmm0_clk
1136                              &pdmm0_clk1
1137                              &pdmm0_sdi0
1138                              &pdmm0_sdi1
1139                              &pdmm0_sdi2
1140                              &pdmm0_sdi3>;
1141                 pinctrl-names = "default";
1142                 resets = <&cru SRST_M_PDM>;
1143                 reset-names = "pdm-m";
1144                 #sound-dai-cells = <0>;
1145                 status = "disabled";
1146         };
1147
1148         dmac0: dma-controller@fe530000 {
1149                 compatible = "arm,pl330", "arm,primecell";
1150                 reg = <0x0 0xfe530000 0x0 0x4000>;
1151                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1152                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1153                 arm,pl330-periph-burst;
1154                 clocks = <&cru ACLK_BUS>;
1155                 clock-names = "apb_pclk";
1156                 #dma-cells = <1>;
1157         };
1158
1159         dmac1: dma-controller@fe550000 {
1160                 compatible = "arm,pl330", "arm,primecell";
1161                 reg = <0x0 0xfe550000 0x0 0x4000>;
1162                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1163                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1164                 arm,pl330-periph-burst;
1165                 clocks = <&cru ACLK_BUS>;
1166                 clock-names = "apb_pclk";
1167                 #dma-cells = <1>;
1168         };
1169
1170         i2c1: i2c@fe5a0000 {
1171                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1172                 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1173                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1174                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1175                 clock-names = "i2c", "pclk";
1176                 pinctrl-0 = <&i2c1_xfer>;
1177                 pinctrl-names = "default";
1178                 #address-cells = <1>;
1179                 #size-cells = <0>;
1180                 status = "disabled";
1181         };
1182
1183         i2c2: i2c@fe5b0000 {
1184                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1185                 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1186                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1187                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1188                 clock-names = "i2c", "pclk";
1189                 pinctrl-0 = <&i2c2m0_xfer>;
1190                 pinctrl-names = "default";
1191                 #address-cells = <1>;
1192                 #size-cells = <0>;
1193                 status = "disabled";
1194         };
1195
1196         i2c3: i2c@fe5c0000 {
1197                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1198                 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1199                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1200                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1201                 clock-names = "i2c", "pclk";
1202                 pinctrl-0 = <&i2c3m0_xfer>;
1203                 pinctrl-names = "default";
1204                 #address-cells = <1>;
1205                 #size-cells = <0>;
1206                 status = "disabled";
1207         };
1208
1209         i2c4: i2c@fe5d0000 {
1210                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1211                 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1212                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1213                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1214                 clock-names = "i2c", "pclk";
1215                 pinctrl-0 = <&i2c4m0_xfer>;
1216                 pinctrl-names = "default";
1217                 #address-cells = <1>;
1218                 #size-cells = <0>;
1219                 status = "disabled";
1220         };
1221
1222         i2c5: i2c@fe5e0000 {
1223                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1224                 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1225                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1226                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1227                 clock-names = "i2c", "pclk";
1228                 pinctrl-0 = <&i2c5m0_xfer>;
1229                 pinctrl-names = "default";
1230                 #address-cells = <1>;
1231                 #size-cells = <0>;
1232                 status = "disabled";
1233         };
1234
1235         wdt: watchdog@fe600000 {
1236                 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1237                 reg = <0x0 0xfe600000 0x0 0x100>;
1238                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1239                 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1240                 clock-names = "tclk", "pclk";
1241         };
1242
1243         spi0: spi@fe610000 {
1244                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1245                 reg = <0x0 0xfe610000 0x0 0x1000>;
1246                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1247                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1248                 clock-names = "spiclk", "apb_pclk";
1249                 dmas = <&dmac0 20>, <&dmac0 21>;
1250                 dma-names = "tx", "rx";
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1253                 #address-cells = <1>;
1254                 #size-cells = <0>;
1255                 status = "disabled";
1256         };
1257
1258         spi1: spi@fe620000 {
1259                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1260                 reg = <0x0 0xfe620000 0x0 0x1000>;
1261                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1262                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1263                 clock-names = "spiclk", "apb_pclk";
1264                 dmas = <&dmac0 22>, <&dmac0 23>;
1265                 dma-names = "tx", "rx";
1266                 pinctrl-names = "default";
1267                 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1268                 #address-cells = <1>;
1269                 #size-cells = <0>;
1270                 status = "disabled";
1271         };
1272
1273         spi2: spi@fe630000 {
1274                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1275                 reg = <0x0 0xfe630000 0x0 0x1000>;
1276                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1277                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1278                 clock-names = "spiclk", "apb_pclk";
1279                 dmas = <&dmac0 24>, <&dmac0 25>;
1280                 dma-names = "tx", "rx";
1281                 pinctrl-names = "default";
1282                 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1283                 #address-cells = <1>;
1284                 #size-cells = <0>;
1285                 status = "disabled";
1286         };
1287
1288         spi3: spi@fe640000 {
1289                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1290                 reg = <0x0 0xfe640000 0x0 0x1000>;
1291                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1292                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1293                 clock-names = "spiclk", "apb_pclk";
1294                 dmas = <&dmac0 26>, <&dmac0 27>;
1295                 dma-names = "tx", "rx";
1296                 pinctrl-names = "default";
1297                 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1298                 #address-cells = <1>;
1299                 #size-cells = <0>;
1300                 status = "disabled";
1301         };
1302
1303         uart1: serial@fe650000 {
1304                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1305                 reg = <0x0 0xfe650000 0x0 0x100>;
1306                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1307                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1308                 clock-names = "baudclk", "apb_pclk";
1309                 dmas = <&dmac0 2>, <&dmac0 3>;
1310                 pinctrl-0 = <&uart1m0_xfer>;
1311                 pinctrl-names = "default";
1312                 reg-io-width = <4>;
1313                 reg-shift = <2>;
1314                 status = "disabled";
1315         };
1316
1317         uart2: serial@fe660000 {
1318                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1319                 reg = <0x0 0xfe660000 0x0 0x100>;
1320                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1321                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1322                 clock-names = "baudclk", "apb_pclk";
1323                 dmas = <&dmac0 4>, <&dmac0 5>;
1324                 pinctrl-0 = <&uart2m0_xfer>;
1325                 pinctrl-names = "default";
1326                 reg-io-width = <4>;
1327                 reg-shift = <2>;
1328                 status = "disabled";
1329         };
1330
1331         uart3: serial@fe670000 {
1332                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1333                 reg = <0x0 0xfe670000 0x0 0x100>;
1334                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1335                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1336                 clock-names = "baudclk", "apb_pclk";
1337                 dmas = <&dmac0 6>, <&dmac0 7>;
1338                 pinctrl-0 = <&uart3m0_xfer>;
1339                 pinctrl-names = "default";
1340                 reg-io-width = <4>;
1341                 reg-shift = <2>;
1342                 status = "disabled";
1343         };
1344
1345         uart4: serial@fe680000 {
1346                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1347                 reg = <0x0 0xfe680000 0x0 0x100>;
1348                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1349                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1350                 clock-names = "baudclk", "apb_pclk";
1351                 dmas = <&dmac0 8>, <&dmac0 9>;
1352                 pinctrl-0 = <&uart4m0_xfer>;
1353                 pinctrl-names = "default";
1354                 reg-io-width = <4>;
1355                 reg-shift = <2>;
1356                 status = "disabled";
1357         };
1358
1359         uart5: serial@fe690000 {
1360                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1361                 reg = <0x0 0xfe690000 0x0 0x100>;
1362                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1363                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1364                 clock-names = "baudclk", "apb_pclk";
1365                 dmas = <&dmac0 10>, <&dmac0 11>;
1366                 pinctrl-0 = <&uart5m0_xfer>;
1367                 pinctrl-names = "default";
1368                 reg-io-width = <4>;
1369                 reg-shift = <2>;
1370                 status = "disabled";
1371         };
1372
1373         uart6: serial@fe6a0000 {
1374                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1375                 reg = <0x0 0xfe6a0000 0x0 0x100>;
1376                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1377                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1378                 clock-names = "baudclk", "apb_pclk";
1379                 dmas = <&dmac0 12>, <&dmac0 13>;
1380                 pinctrl-0 = <&uart6m0_xfer>;
1381                 pinctrl-names = "default";
1382                 reg-io-width = <4>;
1383                 reg-shift = <2>;
1384                 status = "disabled";
1385         };
1386
1387         uart7: serial@fe6b0000 {
1388                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1389                 reg = <0x0 0xfe6b0000 0x0 0x100>;
1390                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1391                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1392                 clock-names = "baudclk", "apb_pclk";
1393                 dmas = <&dmac0 14>, <&dmac0 15>;
1394                 pinctrl-0 = <&uart7m0_xfer>;
1395                 pinctrl-names = "default";
1396                 reg-io-width = <4>;
1397                 reg-shift = <2>;
1398                 status = "disabled";
1399         };
1400
1401         uart8: serial@fe6c0000 {
1402                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1403                 reg = <0x0 0xfe6c0000 0x0 0x100>;
1404                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1405                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1406                 clock-names = "baudclk", "apb_pclk";
1407                 dmas = <&dmac0 16>, <&dmac0 17>;
1408                 pinctrl-0 = <&uart8m0_xfer>;
1409                 pinctrl-names = "default";
1410                 reg-io-width = <4>;
1411                 reg-shift = <2>;
1412                 status = "disabled";
1413         };
1414
1415         uart9: serial@fe6d0000 {
1416                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1417                 reg = <0x0 0xfe6d0000 0x0 0x100>;
1418                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1419                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1420                 clock-names = "baudclk", "apb_pclk";
1421                 dmas = <&dmac0 18>, <&dmac0 19>;
1422                 pinctrl-0 = <&uart9m0_xfer>;
1423                 pinctrl-names = "default";
1424                 reg-io-width = <4>;
1425                 reg-shift = <2>;
1426                 status = "disabled";
1427         };
1428
1429         thermal_zones: thermal-zones {
1430                 cpu_thermal: cpu-thermal {
1431                         polling-delay-passive = <100>;
1432                         polling-delay = <1000>;
1433
1434                         thermal-sensors = <&tsadc 0>;
1435
1436                         trips {
1437                                 cpu_alert0: cpu_alert0 {
1438                                         temperature = <70000>;
1439                                         hysteresis = <2000>;
1440                                         type = "passive";
1441                                 };
1442                                 cpu_alert1: cpu_alert1 {
1443                                         temperature = <75000>;
1444                                         hysteresis = <2000>;
1445                                         type = "passive";
1446                                 };
1447                                 cpu_crit: cpu_crit {
1448                                         temperature = <95000>;
1449                                         hysteresis = <2000>;
1450                                         type = "critical";
1451                                 };
1452                         };
1453
1454                         cooling-maps {
1455                                 map0 {
1456                                         trip = <&cpu_alert0>;
1457                                         cooling-device =
1458                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1459                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1460                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1461                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1462                                 };
1463                         };
1464                 };
1465
1466                 gpu_thermal: gpu-thermal {
1467                         polling-delay-passive = <20>; /* milliseconds */
1468                         polling-delay = <1000>; /* milliseconds */
1469
1470                         thermal-sensors = <&tsadc 1>;
1471
1472                         trips {
1473                                 gpu_threshold: gpu-threshold {
1474                                         temperature = <70000>;
1475                                         hysteresis = <2000>;
1476                                         type = "passive";
1477                                 };
1478                                 gpu_target: gpu-target {
1479                                         temperature = <75000>;
1480                                         hysteresis = <2000>;
1481                                         type = "passive";
1482                                 };
1483                                 gpu_crit: gpu-crit {
1484                                         temperature = <95000>;
1485                                         hysteresis = <2000>;
1486                                         type = "critical";
1487                                 };
1488                         };
1489
1490                         cooling-maps {
1491                                 map0 {
1492                                         trip = <&gpu_target>;
1493                                         cooling-device =
1494                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1495                                 };
1496                         };
1497                 };
1498         };
1499
1500         tsadc: tsadc@fe710000 {
1501                 compatible = "rockchip,rk3568-tsadc";
1502                 reg = <0x0 0xfe710000 0x0 0x100>;
1503                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1504                 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1505                 assigned-clock-rates = <17000000>, <700000>;
1506                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1507                 clock-names = "tsadc", "apb_pclk";
1508                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1509                          <&cru SRST_TSADCPHY>;
1510                 rockchip,grf = <&grf>;
1511                 rockchip,hw-tshut-temp = <95000>;
1512                 pinctrl-names = "init", "default", "sleep";
1513                 pinctrl-0 = <&tsadc_pin>;
1514                 pinctrl-1 = <&tsadc_shutorg>;
1515                 pinctrl-2 = <&tsadc_pin>;
1516                 #thermal-sensor-cells = <1>;
1517                 status = "disabled";
1518         };
1519
1520         saradc: saradc@fe720000 {
1521                 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1522                 reg = <0x0 0xfe720000 0x0 0x100>;
1523                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1524                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1525                 clock-names = "saradc", "apb_pclk";
1526                 resets = <&cru SRST_P_SARADC>;
1527                 reset-names = "saradc-apb";
1528                 #io-channel-cells = <1>;
1529                 status = "disabled";
1530         };
1531
1532         pwm4: pwm@fe6e0000 {
1533                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1534                 reg = <0x0 0xfe6e0000 0x0 0x10>;
1535                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1536                 clock-names = "pwm", "pclk";
1537                 pinctrl-0 = <&pwm4_pins>;
1538                 pinctrl-names = "default";
1539                 #pwm-cells = <3>;
1540                 status = "disabled";
1541         };
1542
1543         pwm5: pwm@fe6e0010 {
1544                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1545                 reg = <0x0 0xfe6e0010 0x0 0x10>;
1546                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1547                 clock-names = "pwm", "pclk";
1548                 pinctrl-0 = <&pwm5_pins>;
1549                 pinctrl-names = "default";
1550                 #pwm-cells = <3>;
1551                 status = "disabled";
1552         };
1553
1554         pwm6: pwm@fe6e0020 {
1555                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1556                 reg = <0x0 0xfe6e0020 0x0 0x10>;
1557                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1558                 clock-names = "pwm", "pclk";
1559                 pinctrl-0 = <&pwm6_pins>;
1560                 pinctrl-names = "default";
1561                 #pwm-cells = <3>;
1562                 status = "disabled";
1563         };
1564
1565         pwm7: pwm@fe6e0030 {
1566                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1567                 reg = <0x0 0xfe6e0030 0x0 0x10>;
1568                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1569                 clock-names = "pwm", "pclk";
1570                 pinctrl-0 = <&pwm7_pins>;
1571                 pinctrl-names = "default";
1572                 #pwm-cells = <3>;
1573                 status = "disabled";
1574         };
1575
1576         pwm8: pwm@fe6f0000 {
1577                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1578                 reg = <0x0 0xfe6f0000 0x0 0x10>;
1579                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1580                 clock-names = "pwm", "pclk";
1581                 pinctrl-0 = <&pwm8m0_pins>;
1582                 pinctrl-names = "default";
1583                 #pwm-cells = <3>;
1584                 status = "disabled";
1585         };
1586
1587         pwm9: pwm@fe6f0010 {
1588                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1589                 reg = <0x0 0xfe6f0010 0x0 0x10>;
1590                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1591                 clock-names = "pwm", "pclk";
1592                 pinctrl-0 = <&pwm9m0_pins>;
1593                 pinctrl-names = "default";
1594                 #pwm-cells = <3>;
1595                 status = "disabled";
1596         };
1597
1598         pwm10: pwm@fe6f0020 {
1599                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1600                 reg = <0x0 0xfe6f0020 0x0 0x10>;
1601                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1602                 clock-names = "pwm", "pclk";
1603                 pinctrl-0 = <&pwm10m0_pins>;
1604                 pinctrl-names = "default";
1605                 #pwm-cells = <3>;
1606                 status = "disabled";
1607         };
1608
1609         pwm11: pwm@fe6f0030 {
1610                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1611                 reg = <0x0 0xfe6f0030 0x0 0x10>;
1612                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1613                 clock-names = "pwm", "pclk";
1614                 pinctrl-0 = <&pwm11m0_pins>;
1615                 pinctrl-names = "default";
1616                 #pwm-cells = <3>;
1617                 status = "disabled";
1618         };
1619
1620         pwm12: pwm@fe700000 {
1621                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1622                 reg = <0x0 0xfe700000 0x0 0x10>;
1623                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1624                 clock-names = "pwm", "pclk";
1625                 pinctrl-0 = <&pwm12m0_pins>;
1626                 pinctrl-names = "default";
1627                 #pwm-cells = <3>;
1628                 status = "disabled";
1629         };
1630
1631         pwm13: pwm@fe700010 {
1632                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1633                 reg = <0x0 0xfe700010 0x0 0x10>;
1634                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1635                 clock-names = "pwm", "pclk";
1636                 pinctrl-0 = <&pwm13m0_pins>;
1637                 pinctrl-names = "default";
1638                 #pwm-cells = <3>;
1639                 status = "disabled";
1640         };
1641
1642         pwm14: pwm@fe700020 {
1643                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1644                 reg = <0x0 0xfe700020 0x0 0x10>;
1645                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1646                 clock-names = "pwm", "pclk";
1647                 pinctrl-0 = <&pwm14m0_pins>;
1648                 pinctrl-names = "default";
1649                 #pwm-cells = <3>;
1650                 status = "disabled";
1651         };
1652
1653         pwm15: pwm@fe700030 {
1654                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1655                 reg = <0x0 0xfe700030 0x0 0x10>;
1656                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1657                 clock-names = "pwm", "pclk";
1658                 pinctrl-0 = <&pwm15m0_pins>;
1659                 pinctrl-names = "default";
1660                 #pwm-cells = <3>;
1661                 status = "disabled";
1662         };
1663
1664         combphy1: phy@fe830000 {
1665                 compatible = "rockchip,rk3568-naneng-combphy";
1666                 reg = <0x0 0xfe830000 0x0 0x100>;
1667                 clocks = <&pmucru CLK_PCIEPHY1_REF>,
1668                          <&cru PCLK_PIPEPHY1>,
1669                          <&cru PCLK_PIPE>;
1670                 clock-names = "ref", "apb", "pipe";
1671                 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1672                 assigned-clock-rates = <100000000>;
1673                 resets = <&cru SRST_PIPEPHY1>;
1674                 rockchip,pipe-grf = <&pipegrf>;
1675                 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1676                 #phy-cells = <1>;
1677                 status = "disabled";
1678         };
1679
1680         combphy2: phy@fe840000 {
1681                 compatible = "rockchip,rk3568-naneng-combphy";
1682                 reg = <0x0 0xfe840000 0x0 0x100>;
1683                 clocks = <&pmucru CLK_PCIEPHY2_REF>,
1684                          <&cru PCLK_PIPEPHY2>,
1685                          <&cru PCLK_PIPE>;
1686                 clock-names = "ref", "apb", "pipe";
1687                 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1688                 assigned-clock-rates = <100000000>;
1689                 resets = <&cru SRST_PIPEPHY2>;
1690                 rockchip,pipe-grf = <&pipegrf>;
1691                 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1692                 #phy-cells = <1>;
1693                 status = "disabled";
1694         };
1695
1696         csi_dphy: phy@fe870000 {
1697                 compatible = "rockchip,rk3568-csi-dphy";
1698                 reg = <0x0 0xfe870000 0x0 0x10000>;
1699                 clocks = <&cru PCLK_MIPICSIPHY>;
1700                 clock-names = "pclk";
1701                 #phy-cells = <0>;
1702                 resets = <&cru SRST_P_MIPICSIPHY>;
1703                 reset-names = "apb";
1704                 rockchip,grf = <&grf>;
1705                 status = "disabled";
1706         };
1707
1708         dsi_dphy0: mipi-dphy@fe850000 {
1709                 compatible = "rockchip,rk3568-dsi-dphy";
1710                 reg = <0x0 0xfe850000 0x0 0x10000>;
1711                 clock-names = "ref", "pclk";
1712                 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1713                 #phy-cells = <0>;
1714                 power-domains = <&power RK3568_PD_VO>;
1715                 reset-names = "apb";
1716                 resets = <&cru SRST_P_MIPIDSIPHY0>;
1717                 status = "disabled";
1718         };
1719
1720         dsi_dphy1: mipi-dphy@fe860000 {
1721                 compatible = "rockchip,rk3568-dsi-dphy";
1722                 reg = <0x0 0xfe860000 0x0 0x10000>;
1723                 clock-names = "ref", "pclk";
1724                 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1725                 #phy-cells = <0>;
1726                 power-domains = <&power RK3568_PD_VO>;
1727                 reset-names = "apb";
1728                 resets = <&cru SRST_P_MIPIDSIPHY1>;
1729                 status = "disabled";
1730         };
1731
1732         usb2phy0: usb2phy@fe8a0000 {
1733                 compatible = "rockchip,rk3568-usb2phy";
1734                 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1735                 clocks = <&pmucru CLK_USBPHY0_REF>;
1736                 clock-names = "phyclk";
1737                 clock-output-names = "clk_usbphy0_480m";
1738                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1739                 rockchip,usbgrf = <&usb2phy0_grf>;
1740                 #clock-cells = <0>;
1741                 status = "disabled";
1742
1743                 usb2phy0_host: host-port {
1744                         #phy-cells = <0>;
1745                         status = "disabled";
1746                 };
1747
1748                 usb2phy0_otg: otg-port {
1749                         #phy-cells = <0>;
1750                         status = "disabled";
1751                 };
1752         };
1753
1754         usb2phy1: usb2phy@fe8b0000 {
1755                 compatible = "rockchip,rk3568-usb2phy";
1756                 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1757                 clocks = <&pmucru CLK_USBPHY1_REF>;
1758                 clock-names = "phyclk";
1759                 clock-output-names = "clk_usbphy1_480m";
1760                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1761                 rockchip,usbgrf = <&usb2phy1_grf>;
1762                 #clock-cells = <0>;
1763                 status = "disabled";
1764
1765                 usb2phy1_host: host-port {
1766                         #phy-cells = <0>;
1767                         status = "disabled";
1768                 };
1769
1770                 usb2phy1_otg: otg-port {
1771                         #phy-cells = <0>;
1772                         status = "disabled";
1773                 };
1774         };
1775
1776         pinctrl: pinctrl {
1777                 compatible = "rockchip,rk3568-pinctrl";
1778                 rockchip,grf = <&grf>;
1779                 rockchip,pmu = <&pmugrf>;
1780                 #address-cells = <2>;
1781                 #size-cells = <2>;
1782                 ranges;
1783
1784                 gpio0: gpio@fdd60000 {
1785                         compatible = "rockchip,gpio-bank";
1786                         reg = <0x0 0xfdd60000 0x0 0x100>;
1787                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1788                         clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1789                         gpio-controller;
1790                         #gpio-cells = <2>;
1791                         interrupt-controller;
1792                         #interrupt-cells = <2>;
1793                 };
1794
1795                 gpio1: gpio@fe740000 {
1796                         compatible = "rockchip,gpio-bank";
1797                         reg = <0x0 0xfe740000 0x0 0x100>;
1798                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1799                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1800                         gpio-controller;
1801                         #gpio-cells = <2>;
1802                         interrupt-controller;
1803                         #interrupt-cells = <2>;
1804                 };
1805
1806                 gpio2: gpio@fe750000 {
1807                         compatible = "rockchip,gpio-bank";
1808                         reg = <0x0 0xfe750000 0x0 0x100>;
1809                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1810                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1811                         gpio-controller;
1812                         #gpio-cells = <2>;
1813                         interrupt-controller;
1814                         #interrupt-cells = <2>;
1815                 };
1816
1817                 gpio3: gpio@fe760000 {
1818                         compatible = "rockchip,gpio-bank";
1819                         reg = <0x0 0xfe760000 0x0 0x100>;
1820                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1821                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1822                         gpio-controller;
1823                         #gpio-cells = <2>;
1824                         interrupt-controller;
1825                         #interrupt-cells = <2>;
1826                 };
1827
1828                 gpio4: gpio@fe770000 {
1829                         compatible = "rockchip,gpio-bank";
1830                         reg = <0x0 0xfe770000 0x0 0x100>;
1831                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1832                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1833                         gpio-controller;
1834                         #gpio-cells = <2>;
1835                         interrupt-controller;
1836                         #interrupt-cells = <2>;
1837                 };
1838         };
1839 };
1840
1841 #include "rk3568-pinctrl.dtsi"