1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
16 acodec_pins: acodec-pins {
19 <1 RK_PB1 5 &pcfg_pull_none>,
21 <1 RK_PA1 5 &pcfg_pull_none>,
23 <1 RK_PA0 5 &pcfg_pull_none>,
24 /* acodec_dac_datal */
25 <1 RK_PA7 5 &pcfg_pull_none>,
26 /* acodec_dac_datar */
27 <1 RK_PB0 5 &pcfg_pull_none>,
29 <1 RK_PA3 5 &pcfg_pull_none>,
31 <1 RK_PA5 5 &pcfg_pull_none>;
37 audiopwm_lout: audiopwm-lout {
40 <1 RK_PA0 4 &pcfg_pull_none>;
44 audiopwm_loutn: audiopwm-loutn {
47 <1 RK_PA1 6 &pcfg_pull_none>;
51 audiopwm_loutp: audiopwm-loutp {
54 <1 RK_PA0 6 &pcfg_pull_none>;
58 audiopwm_rout: audiopwm-rout {
61 <1 RK_PA1 4 &pcfg_pull_none>;
65 audiopwm_routn: audiopwm-routn {
68 <1 RK_PA7 4 &pcfg_pull_none>;
72 audiopwm_routp: audiopwm-routp {
75 <1 RK_PA6 4 &pcfg_pull_none>;
81 bt656m0_pins: bt656m0-pins {
84 <3 RK_PA0 2 &pcfg_pull_none>,
86 <2 RK_PD0 2 &pcfg_pull_none>,
88 <2 RK_PD1 2 &pcfg_pull_none>,
90 <2 RK_PD2 2 &pcfg_pull_none>,
92 <2 RK_PD3 2 &pcfg_pull_none>,
94 <2 RK_PD4 2 &pcfg_pull_none>,
96 <2 RK_PD5 2 &pcfg_pull_none>,
98 <2 RK_PD6 2 &pcfg_pull_none>,
100 <2 RK_PD7 2 &pcfg_pull_none>;
104 bt656m1_pins: bt656m1-pins {
107 <4 RK_PB4 5 &pcfg_pull_none>,
109 <3 RK_PC6 5 &pcfg_pull_none>,
111 <3 RK_PC7 5 &pcfg_pull_none>,
113 <3 RK_PD0 5 &pcfg_pull_none>,
115 <3 RK_PD1 5 &pcfg_pull_none>,
117 <3 RK_PD2 5 &pcfg_pull_none>,
119 <3 RK_PD3 5 &pcfg_pull_none>,
121 <3 RK_PD4 5 &pcfg_pull_none>,
123 <3 RK_PD5 5 &pcfg_pull_none>;
129 bt1120_pins: bt1120-pins {
132 <3 RK_PA6 2 &pcfg_pull_none>,
134 <3 RK_PA1 2 &pcfg_pull_none>,
136 <3 RK_PA2 2 &pcfg_pull_none>,
138 <3 RK_PA3 2 &pcfg_pull_none>,
140 <3 RK_PA4 2 &pcfg_pull_none>,
142 <3 RK_PA5 2 &pcfg_pull_none>,
144 <3 RK_PA7 2 &pcfg_pull_none>,
146 <3 RK_PB0 2 &pcfg_pull_none>,
148 <3 RK_PB1 2 &pcfg_pull_none>,
150 <3 RK_PB2 2 &pcfg_pull_none>,
152 <3 RK_PB3 2 &pcfg_pull_none>,
154 <3 RK_PB4 2 &pcfg_pull_none>,
156 <3 RK_PB5 2 &pcfg_pull_none>,
158 <3 RK_PB6 2 &pcfg_pull_none>,
160 <3 RK_PC1 2 &pcfg_pull_none>,
162 <3 RK_PC2 2 &pcfg_pull_none>,
164 <3 RK_PC3 2 &pcfg_pull_none>;
170 cam_clkout0: cam-clkout0 {
173 <4 RK_PA7 1 &pcfg_pull_none>;
177 cam_clkout1: cam-clkout1 {
180 <4 RK_PB0 1 &pcfg_pull_none>;
186 can0m0_pins: can0m0-pins {
189 <0 RK_PB4 2 &pcfg_pull_none>,
191 <0 RK_PB3 2 &pcfg_pull_none>;
195 can0m1_pins: can0m1-pins {
198 <2 RK_PA2 4 &pcfg_pull_none>,
200 <2 RK_PA1 4 &pcfg_pull_none>;
206 can1m0_pins: can1m0-pins {
209 <1 RK_PA0 3 &pcfg_pull_none>,
211 <1 RK_PA1 3 &pcfg_pull_none>;
215 can1m1_pins: can1m1-pins {
218 <4 RK_PC2 3 &pcfg_pull_none>,
220 <4 RK_PC3 3 &pcfg_pull_none>;
226 can2m0_pins: can2m0-pins {
229 <4 RK_PB4 3 &pcfg_pull_none>,
231 <4 RK_PB5 3 &pcfg_pull_none>;
235 can2m1_pins: can2m1-pins {
238 <2 RK_PB1 4 &pcfg_pull_none>,
240 <2 RK_PB2 4 &pcfg_pull_none>;
249 <4 RK_PC0 1 &pcfg_pull_none>;
253 cif_dvp_clk: cif-dvp-clk {
256 <4 RK_PC1 1 &pcfg_pull_none>,
258 <4 RK_PB6 1 &pcfg_pull_none>,
260 <4 RK_PB7 1 &pcfg_pull_none>;
264 cif_dvp_bus16: cif-dvp-bus16 {
267 <3 RK_PD6 1 &pcfg_pull_none>,
269 <3 RK_PD7 1 &pcfg_pull_none>,
271 <4 RK_PA0 1 &pcfg_pull_none>,
273 <4 RK_PA1 1 &pcfg_pull_none>,
275 <4 RK_PA2 1 &pcfg_pull_none>,
277 <4 RK_PA3 1 &pcfg_pull_none>,
279 <4 RK_PA4 1 &pcfg_pull_none>,
281 <4 RK_PA5 1 &pcfg_pull_none>;
285 cif_dvp_bus8: cif-dvp-bus8 {
288 <3 RK_PC6 1 &pcfg_pull_none>,
290 <3 RK_PC7 1 &pcfg_pull_none>,
292 <3 RK_PD0 1 &pcfg_pull_none>,
294 <3 RK_PD1 1 &pcfg_pull_none>,
296 <3 RK_PD2 1 &pcfg_pull_none>,
298 <3 RK_PD3 1 &pcfg_pull_none>,
300 <3 RK_PD4 1 &pcfg_pull_none>,
302 <3 RK_PD5 1 &pcfg_pull_none>;
308 clk32k_in: clk32k-in {
311 <0 RK_PB0 1 &pcfg_pull_none>;
315 clk32k_out0: clk32k-out0 {
318 <0 RK_PB0 2 &pcfg_pull_none>;
322 clk32k_out1: clk32k-out1 {
325 <2 RK_PC6 1 &pcfg_pull_none>;
334 <0 RK_PB7 2 &pcfg_pull_none>;
340 ebc_extern: ebc-extern {
343 <4 RK_PA7 2 &pcfg_pull_none>,
345 <4 RK_PB0 2 &pcfg_pull_none>,
347 <4 RK_PB1 2 &pcfg_pull_none>,
349 <4 RK_PB5 2 &pcfg_pull_none>,
351 <4 RK_PB2 2 &pcfg_pull_none>;
358 <4 RK_PC0 2 &pcfg_pull_none>,
360 <4 RK_PB3 2 &pcfg_pull_none>,
362 <4 RK_PB4 2 &pcfg_pull_none>,
364 <4 RK_PA6 2 &pcfg_pull_none>,
366 <4 RK_PC1 2 &pcfg_pull_none>,
368 <3 RK_PC6 2 &pcfg_pull_none>,
370 <3 RK_PC7 2 &pcfg_pull_none>,
372 <3 RK_PD0 2 &pcfg_pull_none>,
374 <3 RK_PD1 2 &pcfg_pull_none>,
376 <3 RK_PD2 2 &pcfg_pull_none>,
378 <3 RK_PD3 2 &pcfg_pull_none>,
380 <3 RK_PD4 2 &pcfg_pull_none>,
382 <3 RK_PD5 2 &pcfg_pull_none>,
384 <3 RK_PD6 2 &pcfg_pull_none>,
386 <3 RK_PD7 2 &pcfg_pull_none>,
388 <4 RK_PA0 2 &pcfg_pull_none>,
390 <4 RK_PA1 2 &pcfg_pull_none>,
392 <4 RK_PA2 2 &pcfg_pull_none>,
394 <4 RK_PA3 2 &pcfg_pull_none>,
396 <4 RK_PA4 2 &pcfg_pull_none>,
398 <4 RK_PA5 2 &pcfg_pull_none>,
400 <4 RK_PB6 2 &pcfg_pull_none>,
402 <4 RK_PB7 2 &pcfg_pull_none>;
408 edpdpm0_pins: edpdpm0-pins {
411 <4 RK_PC4 1 &pcfg_pull_none>;
415 edpdpm1_pins: edpdpm1-pins {
418 <0 RK_PC2 2 &pcfg_pull_none>;
424 emmc_rstnout: emmc-rstnout {
427 <1 RK_PC7 1 &pcfg_pull_none>;
431 emmc_bus8: emmc-bus8 {
434 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
436 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
438 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
440 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
442 <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
444 <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
446 <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
448 <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
455 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
462 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
466 emmc_datastrobe: emmc-datastrobe {
468 /* emmc_datastrobe */
469 <1 RK_PC6 1 &pcfg_pull_none>;
475 eth0_pins: eth0-pins {
477 /* eth0_refclko25m */
478 <2 RK_PC1 2 &pcfg_pull_none>;
484 eth1m0_pins: eth1m0-pins {
486 /* eth1_refclko25mm0 */
487 <3 RK_PB0 3 &pcfg_pull_none>;
491 eth1m1_pins: eth1m1-pins {
493 /* eth1_refclko25mm1 */
494 <4 RK_PB3 3 &pcfg_pull_none>;
500 flash_pins: flash-pins {
503 <1 RK_PD0 2 &pcfg_pull_none>,
505 <1 RK_PC6 3 &pcfg_pull_none>,
507 <1 RK_PD3 2 &pcfg_pull_none>,
509 <1 RK_PD4 2 &pcfg_pull_none>,
511 <1 RK_PB4 2 &pcfg_pull_none>,
513 <1 RK_PB5 2 &pcfg_pull_none>,
515 <1 RK_PB6 2 &pcfg_pull_none>,
517 <1 RK_PB7 2 &pcfg_pull_none>,
519 <1 RK_PC0 2 &pcfg_pull_none>,
521 <1 RK_PC1 2 &pcfg_pull_none>,
523 <1 RK_PC2 2 &pcfg_pull_none>,
525 <1 RK_PC3 2 &pcfg_pull_none>,
527 <1 RK_PC5 2 &pcfg_pull_none>,
529 <1 RK_PD2 2 &pcfg_pull_none>,
531 <1 RK_PD1 2 &pcfg_pull_none>,
533 <0 RK_PA7 1 &pcfg_pull_none>,
535 <1 RK_PC7 3 &pcfg_pull_none>,
537 <1 RK_PC4 2 &pcfg_pull_none>;
543 fspi_pins: fspi-pins {
546 <1 RK_PD0 1 &pcfg_pull_none>,
548 <1 RK_PD3 1 &pcfg_pull_none>,
550 <1 RK_PD1 1 &pcfg_pull_none>,
552 <1 RK_PD2 1 &pcfg_pull_none>,
554 <1 RK_PC7 2 &pcfg_pull_none>,
556 <1 RK_PD4 1 &pcfg_pull_none>;
563 <1 RK_PC6 2 &pcfg_pull_up>;
569 gmac0_miim: gmac0-miim {
572 <2 RK_PC3 2 &pcfg_pull_none>,
574 <2 RK_PC4 2 &pcfg_pull_none>;
578 gmac0_clkinout: gmac0-clkinout {
580 /* gmac0_mclkinout */
581 <2 RK_PC2 2 &pcfg_pull_none>;
585 gmac0_rx_er: gmac0-rx-er {
588 <2 RK_PC5 2 &pcfg_pull_none>;
592 gmac0_rx_bus2: gmac0-rx-bus2 {
595 <2 RK_PB6 1 &pcfg_pull_none>,
597 <2 RK_PB7 2 &pcfg_pull_none>,
599 <2 RK_PC0 2 &pcfg_pull_none>;
603 gmac0_tx_bus2: gmac0-tx-bus2 {
606 <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
608 <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
610 <2 RK_PB5 1 &pcfg_pull_none>;
614 gmac0_rgmii_clk: gmac0-rgmii-clk {
617 <2 RK_PA5 2 &pcfg_pull_none>,
619 <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>;
623 gmac0_rgmii_bus: gmac0-rgmii-bus {
626 <2 RK_PA3 2 &pcfg_pull_none>,
628 <2 RK_PA4 2 &pcfg_pull_none>,
630 <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
632 <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
638 gmac1m0_miim: gmac1m0-miim {
641 <3 RK_PC4 3 &pcfg_pull_none>,
643 <3 RK_PC5 3 &pcfg_pull_none>;
647 gmac1m0_clkinout: gmac1m0-clkinout {
649 /* gmac1_mclkinoutm0 */
650 <3 RK_PC0 3 &pcfg_pull_none>;
654 gmac1m0_rx_er: gmac1m0-rx-er {
657 <3 RK_PB4 3 &pcfg_pull_none>;
661 gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
664 <3 RK_PB1 3 &pcfg_pull_none>,
666 <3 RK_PB2 3 &pcfg_pull_none>,
667 /* gmac1_rxdvcrsm0 */
668 <3 RK_PB3 3 &pcfg_pull_none>;
672 gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
675 <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
677 <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
679 <3 RK_PB7 3 &pcfg_pull_none>;
683 gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
686 <3 RK_PA7 3 &pcfg_pull_none>,
688 <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
692 gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
695 <3 RK_PA4 3 &pcfg_pull_none>,
697 <3 RK_PA5 3 &pcfg_pull_none>,
699 <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
701 <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
705 gmac1m1_miim: gmac1m1-miim {
708 <4 RK_PB6 3 &pcfg_pull_none>,
710 <4 RK_PB7 3 &pcfg_pull_none>;
714 gmac1m1_clkinout: gmac1m1-clkinout {
716 /* gmac1_mclkinoutm1 */
717 <4 RK_PC1 3 &pcfg_pull_none>;
721 gmac1m1_rx_er: gmac1m1-rx-er {
724 <4 RK_PB2 3 &pcfg_pull_none>;
728 gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
731 <4 RK_PA7 3 &pcfg_pull_none>,
733 <4 RK_PB0 3 &pcfg_pull_none>,
734 /* gmac1_rxdvcrsm1 */
735 <4 RK_PB1 3 &pcfg_pull_none>;
739 gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
742 <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
744 <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
746 <4 RK_PA6 3 &pcfg_pull_none>;
750 gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
753 <4 RK_PA3 3 &pcfg_pull_none>,
755 <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
759 gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
762 <4 RK_PA1 3 &pcfg_pull_none>,
764 <4 RK_PA2 3 &pcfg_pull_none>,
766 <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
768 <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
777 <0 RK_PC0 2 &pcfg_pull_none>,
779 <0 RK_PA6 4 &pcfg_pull_none>;
785 hdmitxm0_cec: hdmitxm0-cec {
788 <4 RK_PD1 1 &pcfg_pull_none>;
792 hdmitxm1_cec: hdmitxm1-cec {
795 <0 RK_PC7 1 &pcfg_pull_none>;
799 hdmitx_scl: hdmitx-scl {
802 <4 RK_PC7 1 &pcfg_pull_none>;
806 hdmitx_sda: hdmitx-sda {
809 <4 RK_PD0 1 &pcfg_pull_none>;
815 i2c0_xfer: i2c0-xfer {
818 <0 RK_PB1 1 &pcfg_pull_none_smt>,
820 <0 RK_PB2 1 &pcfg_pull_none_smt>;
826 i2c1_xfer: i2c1-xfer {
829 <0 RK_PB3 1 &pcfg_pull_none_smt>,
831 <0 RK_PB4 1 &pcfg_pull_none_smt>;
837 i2c2m0_xfer: i2c2m0-xfer {
840 <0 RK_PB5 1 &pcfg_pull_none_smt>,
842 <0 RK_PB6 1 &pcfg_pull_none_smt>;
846 i2c2m1_xfer: i2c2m1-xfer {
849 <4 RK_PB5 1 &pcfg_pull_none_smt>,
851 <4 RK_PB4 1 &pcfg_pull_none_smt>;
857 i2c3m0_xfer: i2c3m0-xfer {
860 <1 RK_PA1 1 &pcfg_pull_none_smt>,
862 <1 RK_PA0 1 &pcfg_pull_none_smt>;
866 i2c3m1_xfer: i2c3m1-xfer {
869 <3 RK_PB5 4 &pcfg_pull_none_smt>,
871 <3 RK_PB6 4 &pcfg_pull_none_smt>;
877 i2c4m0_xfer: i2c4m0-xfer {
880 <4 RK_PB3 1 &pcfg_pull_none_smt>,
882 <4 RK_PB2 1 &pcfg_pull_none_smt>;
886 i2c4m1_xfer: i2c4m1-xfer {
889 <2 RK_PB2 2 &pcfg_pull_none_smt>,
891 <2 RK_PB1 2 &pcfg_pull_none_smt>;
897 i2c5m0_xfer: i2c5m0-xfer {
900 <3 RK_PB3 4 &pcfg_pull_none_smt>,
902 <3 RK_PB4 4 &pcfg_pull_none_smt>;
906 i2c5m1_xfer: i2c5m1-xfer {
909 <4 RK_PC7 2 &pcfg_pull_none_smt>,
911 <4 RK_PD0 2 &pcfg_pull_none_smt>;
917 i2s1m0_lrckrx: i2s1m0-lrckrx {
920 <1 RK_PA6 1 &pcfg_pull_none>;
924 i2s1m0_lrcktx: i2s1m0-lrcktx {
927 <1 RK_PA5 1 &pcfg_pull_none>;
931 i2s1m0_mclk: i2s1m0-mclk {
934 <1 RK_PA2 1 &pcfg_pull_none>;
938 i2s1m0_sclkrx: i2s1m0-sclkrx {
941 <1 RK_PA4 1 &pcfg_pull_none>;
945 i2s1m0_sclktx: i2s1m0-sclktx {
948 <1 RK_PA3 1 &pcfg_pull_none>;
952 i2s1m0_sdi0: i2s1m0-sdi0 {
955 <1 RK_PB3 1 &pcfg_pull_none>;
959 i2s1m0_sdi1: i2s1m0-sdi1 {
962 <1 RK_PB2 2 &pcfg_pull_none>;
966 i2s1m0_sdi2: i2s1m0-sdi2 {
969 <1 RK_PB1 2 &pcfg_pull_none>;
973 i2s1m0_sdi3: i2s1m0-sdi3 {
976 <1 RK_PB0 2 &pcfg_pull_none>;
980 i2s1m0_sdo0: i2s1m0-sdo0 {
983 <1 RK_PA7 1 &pcfg_pull_none>;
987 i2s1m0_sdo1: i2s1m0-sdo1 {
990 <1 RK_PB0 1 &pcfg_pull_none>;
994 i2s1m0_sdo2: i2s1m0-sdo2 {
997 <1 RK_PB1 1 &pcfg_pull_none>;
1001 i2s1m0_sdo3: i2s1m0-sdo3 {
1004 <1 RK_PB2 1 &pcfg_pull_none>;
1008 i2s1m1_lrckrx: i2s1m1-lrckrx {
1011 <4 RK_PA7 5 &pcfg_pull_none>;
1015 i2s1m1_lrcktx: i2s1m1-lrcktx {
1018 <3 RK_PD0 4 &pcfg_pull_none>;
1022 i2s1m1_mclk: i2s1m1-mclk {
1025 <3 RK_PC6 4 &pcfg_pull_none>;
1029 i2s1m1_sclkrx: i2s1m1-sclkrx {
1032 <4 RK_PA6 5 &pcfg_pull_none>;
1036 i2s1m1_sclktx: i2s1m1-sclktx {
1039 <3 RK_PC7 4 &pcfg_pull_none>;
1043 i2s1m1_sdi0: i2s1m1-sdi0 {
1046 <3 RK_PD2 4 &pcfg_pull_none>;
1050 i2s1m1_sdi1: i2s1m1-sdi1 {
1053 <3 RK_PD3 4 &pcfg_pull_none>;
1057 i2s1m1_sdi2: i2s1m1-sdi2 {
1060 <3 RK_PD4 4 &pcfg_pull_none>;
1064 i2s1m1_sdi3: i2s1m1-sdi3 {
1067 <3 RK_PD5 4 &pcfg_pull_none>;
1071 i2s1m1_sdo0: i2s1m1-sdo0 {
1074 <3 RK_PD1 4 &pcfg_pull_none>;
1078 i2s1m1_sdo1: i2s1m1-sdo1 {
1081 <4 RK_PB0 5 &pcfg_pull_none>;
1085 i2s1m1_sdo2: i2s1m1-sdo2 {
1088 <4 RK_PB1 4 &pcfg_pull_none>;
1092 i2s1m1_sdo3: i2s1m1-sdo3 {
1095 <4 RK_PB5 4 &pcfg_pull_none>;
1099 i2s1m2_lrckrx: i2s1m2-lrckrx {
1102 <3 RK_PC5 5 &pcfg_pull_none>;
1106 i2s1m2_lrcktx: i2s1m2-lrcktx {
1109 <2 RK_PD2 5 &pcfg_pull_none>;
1113 i2s1m2_mclk: i2s1m2-mclk {
1116 <2 RK_PD0 5 &pcfg_pull_none>;
1120 i2s1m2_sclkrx: i2s1m2-sclkrx {
1123 <3 RK_PC3 5 &pcfg_pull_none>;
1127 i2s1m2_sclktx: i2s1m2-sclktx {
1130 <2 RK_PD1 5 &pcfg_pull_none>;
1134 i2s1m2_sdi0: i2s1m2-sdi0 {
1137 <2 RK_PD3 5 &pcfg_pull_none>;
1141 i2s1m2_sdi1: i2s1m2-sdi1 {
1144 <2 RK_PD4 5 &pcfg_pull_none>;
1148 i2s1m2_sdi2: i2s1m2-sdi2 {
1151 <2 RK_PD5 5 &pcfg_pull_none>;
1155 i2s1m2_sdi3: i2s1m2-sdi3 {
1158 <2 RK_PD6 5 &pcfg_pull_none>;
1162 i2s1m2_sdo0: i2s1m2-sdo0 {
1165 <2 RK_PD7 5 &pcfg_pull_none>;
1169 i2s1m2_sdo1: i2s1m2-sdo1 {
1172 <3 RK_PA0 5 &pcfg_pull_none>;
1176 i2s1m2_sdo2: i2s1m2-sdo2 {
1179 <3 RK_PC1 5 &pcfg_pull_none>;
1183 i2s1m2_sdo3: i2s1m2-sdo3 {
1186 <3 RK_PC2 5 &pcfg_pull_none>;
1192 i2s2m0_lrckrx: i2s2m0-lrckrx {
1195 <2 RK_PC0 1 &pcfg_pull_none>;
1199 i2s2m0_lrcktx: i2s2m0-lrcktx {
1202 <2 RK_PC3 1 &pcfg_pull_none>;
1206 i2s2m0_mclk: i2s2m0-mclk {
1209 <2 RK_PC1 1 &pcfg_pull_none>;
1213 i2s2m0_sclkrx: i2s2m0-sclkrx {
1216 <2 RK_PB7 1 &pcfg_pull_none>;
1220 i2s2m0_sclktx: i2s2m0-sclktx {
1223 <2 RK_PC2 1 &pcfg_pull_none>;
1227 i2s2m0_sdi: i2s2m0-sdi {
1230 <2 RK_PC5 1 &pcfg_pull_none>;
1234 i2s2m0_sdo: i2s2m0-sdo {
1237 <2 RK_PC4 1 &pcfg_pull_none>;
1241 i2s2m1_lrckrx: i2s2m1-lrckrx {
1244 <4 RK_PA5 5 &pcfg_pull_none>;
1248 i2s2m1_lrcktx: i2s2m1-lrcktx {
1251 <4 RK_PA4 5 &pcfg_pull_none>;
1255 i2s2m1_mclk: i2s2m1-mclk {
1258 <4 RK_PB6 5 &pcfg_pull_none>;
1262 i2s2m1_sclkrx: i2s2m1-sclkrx {
1265 <4 RK_PC1 5 &pcfg_pull_none>;
1269 i2s2m1_sclktx: i2s2m1-sclktx {
1272 <4 RK_PB7 4 &pcfg_pull_none>;
1276 i2s2m1_sdi: i2s2m1-sdi {
1279 <4 RK_PB2 5 &pcfg_pull_none>;
1283 i2s2m1_sdo: i2s2m1-sdo {
1286 <4 RK_PB3 5 &pcfg_pull_none>;
1292 i2s3m0_lrck: i2s3m0-lrck {
1295 <3 RK_PA4 4 &pcfg_pull_none>;
1299 i2s3m0_mclk: i2s3m0-mclk {
1302 <3 RK_PA2 4 &pcfg_pull_none>;
1306 i2s3m0_sclk: i2s3m0-sclk {
1309 <3 RK_PA3 4 &pcfg_pull_none>;
1313 i2s3m0_sdi: i2s3m0-sdi {
1316 <3 RK_PA6 4 &pcfg_pull_none>;
1320 i2s3m0_sdo: i2s3m0-sdo {
1323 <3 RK_PA5 4 &pcfg_pull_none>;
1327 i2s3m1_lrck: i2s3m1-lrck {
1330 <4 RK_PC4 5 &pcfg_pull_none>;
1334 i2s3m1_mclk: i2s3m1-mclk {
1337 <4 RK_PC2 5 &pcfg_pull_none>;
1341 i2s3m1_sclk: i2s3m1-sclk {
1344 <4 RK_PC3 5 &pcfg_pull_none>;
1348 i2s3m1_sdi: i2s3m1-sdi {
1351 <4 RK_PC6 5 &pcfg_pull_none>;
1355 i2s3m1_sdo: i2s3m1-sdo {
1358 <4 RK_PC5 5 &pcfg_pull_none>;
1364 isp_pins: isp-pins {
1366 /* isp_flashtrigin */
1367 <4 RK_PB4 4 &pcfg_pull_none>,
1368 /* isp_flashtrigout */
1369 <4 RK_PA6 1 &pcfg_pull_none>,
1370 /* isp_prelighttrig */
1371 <4 RK_PB1 1 &pcfg_pull_none>;
1377 jtag_pins: jtag-pins {
1380 <1 RK_PD7 2 &pcfg_pull_none>,
1382 <2 RK_PA0 2 &pcfg_pull_none>;
1388 lcdc_ctl: lcdc-ctl {
1391 <3 RK_PA0 1 &pcfg_pull_none>,
1393 <2 RK_PD0 1 &pcfg_pull_none>,
1395 <2 RK_PD1 1 &pcfg_pull_none>,
1397 <2 RK_PD2 1 &pcfg_pull_none>,
1399 <2 RK_PD3 1 &pcfg_pull_none>,
1401 <2 RK_PD4 1 &pcfg_pull_none>,
1403 <2 RK_PD5 1 &pcfg_pull_none>,
1405 <2 RK_PD6 1 &pcfg_pull_none>,
1407 <2 RK_PD7 1 &pcfg_pull_none>,
1409 <3 RK_PA1 1 &pcfg_pull_none>,
1411 <3 RK_PA2 1 &pcfg_pull_none>,
1413 <3 RK_PA3 1 &pcfg_pull_none>,
1415 <3 RK_PA4 1 &pcfg_pull_none>,
1417 <3 RK_PA5 1 &pcfg_pull_none>,
1419 <3 RK_PA6 1 &pcfg_pull_none>,
1421 <3 RK_PA7 1 &pcfg_pull_none>,
1423 <3 RK_PB0 1 &pcfg_pull_none>,
1425 <3 RK_PB1 1 &pcfg_pull_none>,
1427 <3 RK_PB2 1 &pcfg_pull_none>,
1429 <3 RK_PB3 1 &pcfg_pull_none>,
1431 <3 RK_PB4 1 &pcfg_pull_none>,
1433 <3 RK_PB5 1 &pcfg_pull_none>,
1435 <3 RK_PB6 1 &pcfg_pull_none>,
1437 <3 RK_PB7 1 &pcfg_pull_none>,
1439 <3 RK_PC0 1 &pcfg_pull_none>,
1441 <3 RK_PC3 1 &pcfg_pull_none>,
1443 <3 RK_PC1 1 &pcfg_pull_none>,
1445 <3 RK_PC2 1 &pcfg_pull_none>;
1451 mcu_pins: mcu-pins {
1454 <0 RK_PB4 4 &pcfg_pull_none>,
1456 <0 RK_PC1 4 &pcfg_pull_none>,
1458 <0 RK_PB3 4 &pcfg_pull_none>,
1460 <0 RK_PC2 4 &pcfg_pull_none>,
1462 <0 RK_PC3 4 &pcfg_pull_none>;
1468 npu_pins: npu-pins {
1471 <0 RK_PC1 2 &pcfg_pull_none>;
1477 pcie20m0_pins: pcie20m0-pins {
1479 /* pcie20_clkreqnm0 */
1480 <0 RK_PA5 3 &pcfg_pull_none>,
1481 /* pcie20_perstnm0 */
1482 <0 RK_PB6 3 &pcfg_pull_none>,
1483 /* pcie20_wakenm0 */
1484 <0 RK_PB5 3 &pcfg_pull_none>;
1488 pcie20m1_pins: pcie20m1-pins {
1490 /* pcie20_clkreqnm1 */
1491 <2 RK_PD0 4 &pcfg_pull_none>,
1492 /* pcie20_perstnm1 */
1493 <3 RK_PC1 4 &pcfg_pull_none>,
1494 /* pcie20_wakenm1 */
1495 <2 RK_PD1 4 &pcfg_pull_none>;
1499 pcie20m2_pins: pcie20m2-pins {
1501 /* pcie20_clkreqnm2 */
1502 <1 RK_PB0 4 &pcfg_pull_none>,
1503 /* pcie20_perstnm2 */
1504 <1 RK_PB2 4 &pcfg_pull_none>,
1505 /* pcie20_wakenm2 */
1506 <1 RK_PB1 4 &pcfg_pull_none>;
1510 pcie20_buttonrstn: pcie20-buttonrstn {
1512 /* pcie20_buttonrstn */
1513 <0 RK_PB4 3 &pcfg_pull_none>;
1519 pcie30x1m0_pins: pcie30x1m0-pins {
1521 /* pcie30x1_clkreqnm0 */
1522 <0 RK_PA4 3 &pcfg_pull_none>,
1523 /* pcie30x1_perstnm0 */
1524 <0 RK_PC3 3 &pcfg_pull_none>,
1525 /* pcie30x1_wakenm0 */
1526 <0 RK_PC2 3 &pcfg_pull_none>;
1530 pcie30x1m1_pins: pcie30x1m1-pins {
1532 /* pcie30x1_clkreqnm1 */
1533 <2 RK_PD2 4 &pcfg_pull_none>,
1534 /* pcie30x1_perstnm1 */
1535 <3 RK_PA1 4 &pcfg_pull_none>,
1536 /* pcie30x1_wakenm1 */
1537 <2 RK_PD3 4 &pcfg_pull_none>;
1541 pcie30x1m2_pins: pcie30x1m2-pins {
1543 /* pcie30x1_clkreqnm2 */
1544 <1 RK_PA5 4 &pcfg_pull_none>,
1545 /* pcie30x1_perstnm2 */
1546 <1 RK_PA2 4 &pcfg_pull_none>,
1547 /* pcie30x1_wakenm2 */
1548 <1 RK_PA3 4 &pcfg_pull_none>;
1552 pcie30x1_buttonrstn: pcie30x1-buttonrstn {
1554 /* pcie30x1_buttonrstn */
1555 <0 RK_PB3 3 &pcfg_pull_none>;
1561 pcie30x2m0_pins: pcie30x2m0-pins {
1563 /* pcie30x2_clkreqnm0 */
1564 <0 RK_PA6 2 &pcfg_pull_none>,
1565 /* pcie30x2_perstnm0 */
1566 <0 RK_PC6 3 &pcfg_pull_none>,
1567 /* pcie30x2_wakenm0 */
1568 <0 RK_PC5 3 &pcfg_pull_none>;
1572 pcie30x2m1_pins: pcie30x2m1-pins {
1574 /* pcie30x2_clkreqnm1 */
1575 <2 RK_PD4 4 &pcfg_pull_none>,
1576 /* pcie30x2_perstnm1 */
1577 <2 RK_PD6 4 &pcfg_pull_none>,
1578 /* pcie30x2_wakenm1 */
1579 <2 RK_PD5 4 &pcfg_pull_none>;
1583 pcie30x2m2_pins: pcie30x2m2-pins {
1585 /* pcie30x2_clkreqnm2 */
1586 <4 RK_PC2 4 &pcfg_pull_none>,
1587 /* pcie30x2_perstnm2 */
1588 <4 RK_PC4 4 &pcfg_pull_none>,
1589 /* pcie30x2_wakenm2 */
1590 <4 RK_PC3 4 &pcfg_pull_none>;
1594 pcie30x2_buttonrstn: pcie30x2-buttonrstn {
1596 /* pcie30x2_buttonrstn */
1597 <0 RK_PB0 3 &pcfg_pull_none>;
1603 pdmm0_clk: pdmm0-clk {
1606 <1 RK_PA6 3 &pcfg_pull_none>;
1610 pdmm0_clk1: pdmm0-clk1 {
1613 <1 RK_PA4 3 &pcfg_pull_none>;
1617 pdmm0_sdi0: pdmm0-sdi0 {
1620 <1 RK_PB3 2 &pcfg_pull_none>;
1624 pdmm0_sdi1: pdmm0-sdi1 {
1627 <1 RK_PB2 3 &pcfg_pull_none>;
1631 pdmm0_sdi2: pdmm0-sdi2 {
1634 <1 RK_PB1 3 &pcfg_pull_none>;
1638 pdmm0_sdi3: pdmm0-sdi3 {
1641 <1 RK_PB0 3 &pcfg_pull_none>;
1645 pdmm1_clk: pdmm1-clk {
1648 <3 RK_PD6 5 &pcfg_pull_none>;
1652 pdmm1_clk1: pdmm1-clk1 {
1655 <4 RK_PA0 4 &pcfg_pull_none>;
1659 pdmm1_sdi0: pdmm1-sdi0 {
1662 <3 RK_PD7 5 &pcfg_pull_none>;
1666 pdmm1_sdi1: pdmm1-sdi1 {
1669 <4 RK_PA1 4 &pcfg_pull_none>;
1673 pdmm1_sdi2: pdmm1-sdi2 {
1676 <4 RK_PA2 5 &pcfg_pull_none>;
1680 pdmm1_sdi3: pdmm1-sdi3 {
1683 <4 RK_PA3 5 &pcfg_pull_none>;
1687 pdmm2_clk1: pdmm2-clk1 {
1690 <3 RK_PC4 5 &pcfg_pull_none>;
1694 pdmm2_sdi0: pdmm2-sdi0 {
1697 <3 RK_PB3 5 &pcfg_pull_none>;
1701 pdmm2_sdi1: pdmm2-sdi1 {
1704 <3 RK_PB4 5 &pcfg_pull_none>;
1708 pdmm2_sdi2: pdmm2-sdi2 {
1711 <3 RK_PB7 5 &pcfg_pull_none>;
1715 pdmm2_sdi3: pdmm2-sdi3 {
1718 <3 RK_PC0 5 &pcfg_pull_none>;
1724 pmic_pins: pmic-pins {
1727 <0 RK_PA2 1 &pcfg_pull_none>;
1733 pmu_pins: pmu-pins {
1736 <0 RK_PA5 4 &pcfg_pull_none>,
1738 <0 RK_PA6 3 &pcfg_pull_none>,
1740 <0 RK_PC4 4 &pcfg_pull_none>,
1742 <0 RK_PC5 4 &pcfg_pull_none>,
1744 <0 RK_PC6 4 &pcfg_pull_none>,
1746 <0 RK_PC7 4 &pcfg_pull_none>;
1752 pwm0m0_pins: pwm0m0-pins {
1755 <0 RK_PB7 1 &pcfg_pull_none>;
1759 pwm0m1_pins: pwm0m1-pins {
1762 <0 RK_PC7 2 &pcfg_pull_none>;
1768 pwm1m0_pins: pwm1m0-pins {
1771 <0 RK_PC0 1 &pcfg_pull_none>;
1775 pwm1m1_pins: pwm1m1-pins {
1778 <0 RK_PB5 4 &pcfg_pull_none>;
1784 pwm2m0_pins: pwm2m0-pins {
1787 <0 RK_PC1 1 &pcfg_pull_none>;
1791 pwm2m1_pins: pwm2m1-pins {
1794 <0 RK_PB6 4 &pcfg_pull_none>;
1800 pwm3_pins: pwm3-pins {
1803 <0 RK_PC2 1 &pcfg_pull_none>;
1809 pwm4_pins: pwm4-pins {
1812 <0 RK_PC3 1 &pcfg_pull_none>;
1818 pwm5_pins: pwm5-pins {
1821 <0 RK_PC4 1 &pcfg_pull_none>;
1827 pwm6_pins: pwm6-pins {
1830 <0 RK_PC5 1 &pcfg_pull_none>;
1836 pwm7_pins: pwm7-pins {
1839 <0 RK_PC6 1 &pcfg_pull_none>;
1845 pwm8m0_pins: pwm8m0-pins {
1848 <3 RK_PB1 5 &pcfg_pull_none>;
1852 pwm8m1_pins: pwm8m1-pins {
1855 <1 RK_PD5 4 &pcfg_pull_none>;
1861 pwm9m0_pins: pwm9m0-pins {
1864 <3 RK_PB2 5 &pcfg_pull_none>;
1868 pwm9m1_pins: pwm9m1-pins {
1871 <1 RK_PD6 4 &pcfg_pull_none>;
1877 pwm10m0_pins: pwm10m0-pins {
1880 <3 RK_PB5 5 &pcfg_pull_none>;
1884 pwm10m1_pins: pwm10m1-pins {
1887 <2 RK_PA1 2 &pcfg_pull_none>;
1893 pwm11m0_pins: pwm11m0-pins {
1896 <3 RK_PB6 5 &pcfg_pull_none>;
1900 pwm11m1_pins: pwm11m1-pins {
1903 <4 RK_PC0 3 &pcfg_pull_none>;
1909 pwm12m0_pins: pwm12m0-pins {
1912 <3 RK_PB7 2 &pcfg_pull_none>;
1916 pwm12m1_pins: pwm12m1-pins {
1919 <4 RK_PC5 1 &pcfg_pull_none>;
1925 pwm13m0_pins: pwm13m0-pins {
1928 <3 RK_PC0 2 &pcfg_pull_none>;
1932 pwm13m1_pins: pwm13m1-pins {
1935 <4 RK_PC6 1 &pcfg_pull_none>;
1941 pwm14m0_pins: pwm14m0-pins {
1944 <3 RK_PC4 1 &pcfg_pull_none>;
1948 pwm14m1_pins: pwm14m1-pins {
1951 <4 RK_PC2 1 &pcfg_pull_none>;
1957 pwm15m0_pins: pwm15m0-pins {
1960 <3 RK_PC5 1 &pcfg_pull_none>;
1964 pwm15m1_pins: pwm15m1-pins {
1967 <4 RK_PC3 1 &pcfg_pull_none>;
1973 refclk_pins: refclk-pins {
1976 <0 RK_PA0 1 &pcfg_pull_none>;
1982 sata_pins: sata-pins {
1985 <0 RK_PA4 2 &pcfg_pull_none>,
1987 <0 RK_PA6 1 &pcfg_pull_none>,
1989 <0 RK_PA5 2 &pcfg_pull_none>;
1995 sata0_pins: sata0-pins {
1998 <4 RK_PC6 3 &pcfg_pull_none>;
2004 sata1_pins: sata1-pins {
2007 <4 RK_PC5 3 &pcfg_pull_none>;
2013 sata2_pins: sata2-pins {
2016 <4 RK_PC4 3 &pcfg_pull_none>;
2022 scr_pins: scr-pins {
2025 <1 RK_PA2 3 &pcfg_pull_none>,
2027 <1 RK_PA7 3 &pcfg_pull_up>,
2029 <1 RK_PA3 3 &pcfg_pull_up>,
2031 <1 RK_PA5 3 &pcfg_pull_none>;
2037 sdmmc0_bus4: sdmmc0-bus4 {
2040 <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
2042 <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
2044 <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
2046 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
2050 sdmmc0_clk: sdmmc0-clk {
2053 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
2057 sdmmc0_cmd: sdmmc0-cmd {
2060 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
2064 sdmmc0_det: sdmmc0-det {
2067 <0 RK_PA4 1 &pcfg_pull_up>;
2071 sdmmc0_pwren: sdmmc0-pwren {
2074 <0 RK_PA5 1 &pcfg_pull_none>;
2080 sdmmc1_bus4: sdmmc1-bus4 {
2083 <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
2085 <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
2087 <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
2089 <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
2093 sdmmc1_clk: sdmmc1-clk {
2096 <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
2100 sdmmc1_cmd: sdmmc1-cmd {
2103 <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
2107 sdmmc1_det: sdmmc1-det {
2110 <2 RK_PB2 1 &pcfg_pull_up>;
2114 sdmmc1_pwren: sdmmc1-pwren {
2117 <2 RK_PB1 1 &pcfg_pull_none>;
2123 sdmmc2m0_bus4: sdmmc2m0-bus4 {
2126 <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
2128 <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
2130 <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
2132 <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
2136 sdmmc2m0_clk: sdmmc2m0-clk {
2139 <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
2143 sdmmc2m0_cmd: sdmmc2m0-cmd {
2146 <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
2150 sdmmc2m0_det: sdmmc2m0-det {
2153 <3 RK_PD4 3 &pcfg_pull_up>;
2157 sdmmc2m0_pwren: sdmmc2m0-pwren {
2159 /* sdmmc2m0_pwren */
2160 <3 RK_PD5 3 &pcfg_pull_none>;
2164 sdmmc2m1_bus4: sdmmc2m1-bus4 {
2167 <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
2169 <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
2171 <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
2173 <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
2177 sdmmc2m1_clk: sdmmc2m1-clk {
2180 <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
2184 sdmmc2m1_cmd: sdmmc2m1-cmd {
2187 <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
2191 sdmmc2m1_det: sdmmc2m1-det {
2194 <3 RK_PA7 4 &pcfg_pull_up>;
2198 sdmmc2m1_pwren: sdmmc2m1-pwren {
2200 /* sdmmc2m1_pwren */
2201 <3 RK_PB0 4 &pcfg_pull_none>;
2207 spdifm0_tx: spdifm0-tx {
2210 <1 RK_PA4 4 &pcfg_pull_none>;
2214 spdifm1_tx: spdifm1-tx {
2217 <3 RK_PC5 2 &pcfg_pull_none>;
2221 spdifm2_tx: spdifm2-tx {
2224 <4 RK_PC4 2 &pcfg_pull_none>;
2230 spi0m0_pins: spi0m0-pins {
2233 <0 RK_PB5 2 &pcfg_pull_none>,
2235 <0 RK_PC5 2 &pcfg_pull_none>,
2237 <0 RK_PB6 2 &pcfg_pull_none>;
2241 spi0m0_cs0: spi0m0-cs0 {
2244 <0 RK_PC6 2 &pcfg_pull_none>;
2248 spi0m0_cs1: spi0m0-cs1 {
2251 <0 RK_PC4 2 &pcfg_pull_none>;
2255 spi0m1_pins: spi0m1-pins {
2258 <2 RK_PD3 3 &pcfg_pull_none>,
2260 <2 RK_PD0 3 &pcfg_pull_none>,
2262 <2 RK_PD1 3 &pcfg_pull_none>;
2266 spi0m1_cs0: spi0m1-cs0 {
2269 <2 RK_PD2 3 &pcfg_pull_none>;
2275 spi1m0_pins: spi1m0-pins {
2278 <2 RK_PB5 3 &pcfg_pull_none>,
2280 <2 RK_PB6 3 &pcfg_pull_none>,
2282 <2 RK_PB7 4 &pcfg_pull_none>;
2286 spi1m0_cs0: spi1m0-cs0 {
2289 <2 RK_PC0 4 &pcfg_pull_none>;
2293 spi1m0_cs1: spi1m0-cs1 {
2296 <2 RK_PC6 3 &pcfg_pull_none>;
2300 spi1m1_pins: spi1m1-pins {
2303 <3 RK_PC3 3 &pcfg_pull_none>,
2305 <3 RK_PC2 3 &pcfg_pull_none>,
2307 <3 RK_PC1 3 &pcfg_pull_none>;
2311 spi1m1_cs0: spi1m1-cs0 {
2314 <3 RK_PA1 3 &pcfg_pull_none>;
2320 spi2m0_pins: spi2m0-pins {
2323 <2 RK_PC1 4 &pcfg_pull_none>,
2325 <2 RK_PC2 4 &pcfg_pull_none>,
2327 <2 RK_PC3 4 &pcfg_pull_none>;
2331 spi2m0_cs0: spi2m0-cs0 {
2334 <2 RK_PC4 4 &pcfg_pull_none>;
2338 spi2m0_cs1: spi2m0-cs1 {
2341 <2 RK_PC5 4 &pcfg_pull_none>;
2345 spi2m1_pins: spi2m1-pins {
2348 <3 RK_PA0 3 &pcfg_pull_none>,
2350 <2 RK_PD7 3 &pcfg_pull_none>,
2352 <2 RK_PD6 3 &pcfg_pull_none>;
2356 spi2m1_cs0: spi2m1-cs0 {
2359 <2 RK_PD5 3 &pcfg_pull_none>;
2363 spi2m1_cs1: spi2m1-cs1 {
2366 <2 RK_PD4 3 &pcfg_pull_none>;
2372 spi3m0_pins: spi3m0-pins {
2375 <4 RK_PB3 4 &pcfg_pull_none>,
2377 <4 RK_PB0 4 &pcfg_pull_none>,
2379 <4 RK_PB2 4 &pcfg_pull_none>;
2383 spi3m0_cs0: spi3m0-cs0 {
2386 <4 RK_PA6 4 &pcfg_pull_none>;
2390 spi3m0_cs1: spi3m0-cs1 {
2393 <4 RK_PA7 4 &pcfg_pull_none>;
2397 spi3m1_pins: spi3m1-pins {
2400 <4 RK_PC2 2 &pcfg_pull_none>,
2402 <4 RK_PC5 2 &pcfg_pull_none>,
2404 <4 RK_PC3 2 &pcfg_pull_none>;
2408 spi3m1_cs0: spi3m1-cs0 {
2411 <4 RK_PC6 2 &pcfg_pull_none>;
2415 spi3m1_cs1: spi3m1-cs1 {
2418 <4 RK_PD1 2 &pcfg_pull_none>;
2424 tsadcm0_shut: tsadcm0-shut {
2427 <0 RK_PA1 1 &pcfg_pull_none>;
2431 tsadcm1_shut: tsadcm1-shut {
2434 <0 RK_PA2 2 &pcfg_pull_none>;
2438 tsadc_shutorg: tsadc-shutorg {
2441 <0 RK_PA1 2 &pcfg_pull_none>;
2447 uart0_xfer: uart0-xfer {
2450 <0 RK_PC0 3 &pcfg_pull_up>,
2452 <0 RK_PC1 3 &pcfg_pull_up>;
2456 uart0_ctsn: uart0-ctsn {
2459 <0 RK_PC7 3 &pcfg_pull_none>;
2463 uart0_rtsn: uart0-rtsn {
2466 <0 RK_PC4 3 &pcfg_pull_none>;
2472 uart1m0_xfer: uart1m0-xfer {
2475 <2 RK_PB3 2 &pcfg_pull_up>,
2477 <2 RK_PB4 2 &pcfg_pull_up>;
2481 uart1m0_ctsn: uart1m0-ctsn {
2484 <2 RK_PB6 2 &pcfg_pull_none>;
2488 uart1m0_rtsn: uart1m0-rtsn {
2491 <2 RK_PB5 2 &pcfg_pull_none>;
2495 uart1m1_xfer: uart1m1-xfer {
2498 <3 RK_PD7 4 &pcfg_pull_up>,
2500 <3 RK_PD6 4 &pcfg_pull_up>;
2504 uart1m1_ctsn: uart1m1-ctsn {
2507 <4 RK_PC1 4 &pcfg_pull_none>;
2511 uart1m1_rtsn: uart1m1-rtsn {
2514 <4 RK_PB6 4 &pcfg_pull_none>;
2520 uart2m0_xfer: uart2m0-xfer {
2523 <0 RK_PD0 1 &pcfg_pull_up>,
2525 <0 RK_PD1 1 &pcfg_pull_up>;
2529 uart2m1_xfer: uart2m1-xfer {
2532 <1 RK_PD6 2 &pcfg_pull_up>,
2534 <1 RK_PD5 2 &pcfg_pull_up>;
2540 uart3m0_xfer: uart3m0-xfer {
2543 <1 RK_PA0 2 &pcfg_pull_up>,
2545 <1 RK_PA1 2 &pcfg_pull_up>;
2549 uart3m0_ctsn: uart3m0-ctsn {
2552 <1 RK_PA3 2 &pcfg_pull_none>;
2556 uart3m0_rtsn: uart3m0-rtsn {
2559 <1 RK_PA2 2 &pcfg_pull_none>;
2563 uart3m1_xfer: uart3m1-xfer {
2566 <3 RK_PC0 4 &pcfg_pull_up>,
2568 <3 RK_PB7 4 &pcfg_pull_up>;
2574 uart4m0_xfer: uart4m0-xfer {
2577 <1 RK_PA4 2 &pcfg_pull_up>,
2579 <1 RK_PA6 2 &pcfg_pull_up>;
2583 uart4m0_ctsn: uart4m0-ctsn {
2586 <1 RK_PA7 2 &pcfg_pull_none>;
2590 uart4m0_rtsn: uart4m0-rtsn {
2593 <1 RK_PA5 2 &pcfg_pull_none>;
2597 uart4m1_xfer: uart4m1-xfer {
2600 <3 RK_PB1 4 &pcfg_pull_up>,
2602 <3 RK_PB2 4 &pcfg_pull_up>;
2608 uart5m0_xfer: uart5m0-xfer {
2611 <2 RK_PA1 3 &pcfg_pull_up>,
2613 <2 RK_PA2 3 &pcfg_pull_up>;
2617 uart5m0_ctsn: uart5m0-ctsn {
2620 <1 RK_PD7 3 &pcfg_pull_none>;
2624 uart5m0_rtsn: uart5m0-rtsn {
2627 <2 RK_PA0 3 &pcfg_pull_none>;
2631 uart5m1_xfer: uart5m1-xfer {
2634 <3 RK_PC3 4 &pcfg_pull_up>,
2636 <3 RK_PC2 4 &pcfg_pull_up>;
2642 uart6m0_xfer: uart6m0-xfer {
2645 <2 RK_PA3 3 &pcfg_pull_up>,
2647 <2 RK_PA4 3 &pcfg_pull_up>;
2651 uart6m0_ctsn: uart6m0-ctsn {
2654 <2 RK_PC0 3 &pcfg_pull_none>;
2658 uart6m0_rtsn: uart6m0-rtsn {
2661 <2 RK_PB7 3 &pcfg_pull_none>;
2665 uart6m1_xfer: uart6m1-xfer {
2668 <1 RK_PD6 3 &pcfg_pull_up>,
2670 <1 RK_PD5 3 &pcfg_pull_up>;
2676 uart7m0_xfer: uart7m0-xfer {
2679 <2 RK_PA5 3 &pcfg_pull_up>,
2681 <2 RK_PA6 3 &pcfg_pull_up>;
2685 uart7m0_ctsn: uart7m0-ctsn {
2688 <2 RK_PC2 3 &pcfg_pull_none>;
2692 uart7m0_rtsn: uart7m0-rtsn {
2695 <2 RK_PC1 3 &pcfg_pull_none>;
2699 uart7m1_xfer: uart7m1-xfer {
2702 <3 RK_PC5 4 &pcfg_pull_up>,
2704 <3 RK_PC4 4 &pcfg_pull_up>;
2708 uart7m2_xfer: uart7m2-xfer {
2711 <4 RK_PA3 4 &pcfg_pull_up>,
2713 <4 RK_PA2 4 &pcfg_pull_up>;
2719 uart8m0_xfer: uart8m0-xfer {
2722 <2 RK_PC6 2 &pcfg_pull_up>,
2724 <2 RK_PC5 3 &pcfg_pull_up>;
2728 uart8m0_ctsn: uart8m0-ctsn {
2731 <2 RK_PB2 3 &pcfg_pull_none>;
2735 uart8m0_rtsn: uart8m0-rtsn {
2738 <2 RK_PB1 3 &pcfg_pull_none>;
2742 uart8m1_xfer: uart8m1-xfer {
2745 <3 RK_PA0 4 &pcfg_pull_up>,
2747 <2 RK_PD7 4 &pcfg_pull_up>;
2753 uart9m0_xfer: uart9m0-xfer {
2756 <2 RK_PA7 3 &pcfg_pull_up>,
2758 <2 RK_PB0 3 &pcfg_pull_up>;
2762 uart9m0_ctsn: uart9m0-ctsn {
2765 <2 RK_PC4 3 &pcfg_pull_none>;
2769 uart9m0_rtsn: uart9m0-rtsn {
2772 <2 RK_PC3 3 &pcfg_pull_none>;
2776 uart9m1_xfer: uart9m1-xfer {
2779 <4 RK_PC6 4 &pcfg_pull_up>,
2781 <4 RK_PC5 4 &pcfg_pull_up>;
2785 uart9m2_xfer: uart9m2-xfer {
2788 <4 RK_PA5 4 &pcfg_pull_up>,
2790 <4 RK_PA4 4 &pcfg_pull_up>;
2796 vopm0_pins: vopm0-pins {
2799 <0 RK_PC3 2 &pcfg_pull_none>;
2803 vopm1_pins: vopm1-pins {
2806 <3 RK_PC4 2 &pcfg_pull_none>;
2812 * This part is edited handly.
2817 spi0m0_pins_hs: spi0m0-pins {
2820 <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>,
2822 <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
2824 <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
2828 spi0m0_cs0_hs: spi0m0-cs0 {
2831 <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
2835 spi0m0_cs1_hs: spi0m0-cs1 {
2838 <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>;
2842 spi0m1_pins_hs: spi0m1-pins {
2845 <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>,
2847 <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>,
2849 <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
2853 spi0m1_cs0_hs: spi0m1-cs0 {
2856 <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>;
2862 spi1m0_pins_hs: spi1m0-pins {
2865 <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>,
2867 <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>,
2869 <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
2873 spi1m0_cs0_hs: spi1m0-cs0 {
2876 <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>;
2880 spi1m0_cs1_hs: spi1m0-cs1 {
2883 <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>;
2887 spi1m1_pins_hs: spi1m1-pins {
2890 <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>,
2892 <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>,
2894 <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
2898 spi1m1_cs0_hs: spi1m1-cs0 {
2901 <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>;
2907 spi2m0_pins_hs: spi2m0-pins {
2910 <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>,
2912 <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>,
2914 <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
2918 spi2m0_cs0_hs: spi2m0-cs0 {
2921 <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>;
2925 spi2m0_cs1_hs: spi2m0-cs1 {
2928 <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>;
2932 spi2m1_pins_hs: spi2m1-pins {
2935 <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>,
2937 <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>,
2939 <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
2943 spi2m1_cs0_hs: spi2m1-cs0 {
2946 <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>;
2950 spi2m1_cs1_hs: spi2m1-cs1 {
2953 <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>;
2959 spi3m0_pins_hs: spi3m0-pins {
2962 <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>,
2964 <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>,
2966 <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
2970 spi3m0_cs0_hs: spi3m0-cs0 {
2973 <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>;
2977 spi3m0_cs1_hs: spi3m0-cs1 {
2980 <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>;
2984 spi3m1_pins_hs: spi3m1-pins {
2987 <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>,
2989 <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
2991 <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
2995 spi3m1_cs0_hs: spi3m1-cs0 {
2998 <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
3002 spi3m1_cs1_hs: spi3m1-cs1 {
3005 <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>;
3011 gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
3014 <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
3016 <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
3018 <2 RK_PB5 1 &pcfg_pull_none>;
3022 gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
3025 <2 RK_PA3 2 &pcfg_pull_none>,
3027 <2 RK_PA4 2 &pcfg_pull_none>,
3029 <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>,
3031 <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
3035 gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
3038 <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
3040 <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
3042 <3 RK_PB7 3 &pcfg_pull_none>;
3046 gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
3049 <3 RK_PA4 3 &pcfg_pull_none>,
3051 <3 RK_PA5 3 &pcfg_pull_none>,
3053 <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
3055 <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
3059 gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
3062 <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
3064 <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
3066 <4 RK_PA6 3 &pcfg_pull_none>;
3070 gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
3073 <4 RK_PA1 3 &pcfg_pull_none>,
3075 <4 RK_PA2 3 &pcfg_pull_none>,
3077 <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
3079 <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
3085 gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
3088 <2 RK_PA5 2 &pcfg_pull_none>,
3090 <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
3094 gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
3097 <3 RK_PA7 3 &pcfg_pull_none>,
3099 <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
3103 gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
3106 <4 RK_PA3 3 &pcfg_pull_none>,
3108 <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
3114 tsadc_pin: tsadc-pin {
3117 <0 RK_PA1 0 &pcfg_pull_none>;
3123 lcdc_clock: lcdc-clock {
3126 <3 RK_PA0 1 &pcfg_pull_none>,
3128 <3 RK_PC3 1 &pcfg_pull_none>,
3130 <3 RK_PC1 1 &pcfg_pull_none>,
3132 <3 RK_PC2 1 &pcfg_pull_none>;
3136 lcdc_data16: lcdc-data16 {
3139 <2 RK_PD3 1 &pcfg_pull_none>,
3141 <2 RK_PD4 1 &pcfg_pull_none>,
3143 <2 RK_PD5 1 &pcfg_pull_none>,
3145 <2 RK_PD6 1 &pcfg_pull_none>,
3147 <2 RK_PD7 1 &pcfg_pull_none>,
3149 <3 RK_PA3 1 &pcfg_pull_none>,
3151 <3 RK_PA4 1 &pcfg_pull_none>,
3153 <3 RK_PA5 1 &pcfg_pull_none>,
3155 <3 RK_PA6 1 &pcfg_pull_none>,
3157 <3 RK_PA7 1 &pcfg_pull_none>,
3159 <3 RK_PB0 1 &pcfg_pull_none>,
3161 <3 RK_PB4 1 &pcfg_pull_none>,
3163 <3 RK_PB5 1 &pcfg_pull_none>,
3165 <3 RK_PB6 1 &pcfg_pull_none>,
3167 <3 RK_PB7 1 &pcfg_pull_none>,
3169 <3 RK_PC0 1 &pcfg_pull_none>;
3173 lcdc_data18: lcdc-data18 {
3176 <2 RK_PD2 1 &pcfg_pull_none>,
3178 <2 RK_PD3 1 &pcfg_pull_none>,
3180 <2 RK_PD4 1 &pcfg_pull_none>,
3182 <2 RK_PD5 1 &pcfg_pull_none>,
3184 <2 RK_PD6 1 &pcfg_pull_none>,
3186 <2 RK_PD7 1 &pcfg_pull_none>,
3188 <3 RK_PA3 1 &pcfg_pull_none>,
3190 <3 RK_PA4 1 &pcfg_pull_none>,
3192 <3 RK_PA5 1 &pcfg_pull_none>,
3194 <3 RK_PA6 1 &pcfg_pull_none>,
3196 <3 RK_PA7 1 &pcfg_pull_none>,
3198 <3 RK_PB0 1 &pcfg_pull_none>,
3200 <3 RK_PB3 1 &pcfg_pull_none>,
3202 <3 RK_PB4 1 &pcfg_pull_none>,
3204 <3 RK_PB5 1 &pcfg_pull_none>,
3206 <3 RK_PB6 1 &pcfg_pull_none>,
3208 <3 RK_PB7 1 &pcfg_pull_none>,
3210 <3 RK_PC0 1 &pcfg_pull_none>;