arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
   4  * (http://www.friendlyelec.com)
   5  *
   6  * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
   7  */
   8
   9 /dts-v1/;
  10 #include "rk3568-nanopi-r5s.dtsi"
  11
  12 / {
  13         model = "FriendlyElec NanoPi R5S";
  14         compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
  15
  16         aliases {
  17                 ethernet0 = &gmac0;
  18         };
  19
  20         gpio-leds {
  21                 compatible = "gpio-leds";
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
  24
  25                 led-lan1 {
  26                         color = <LED_COLOR_ID_GREEN>;
  27                         function = LED_FUNCTION_LAN;
  28                         function-enumerator = <1>;
  29                         gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
  30                 };
  31
  32                 led-lan2 {
  33                         color = <LED_COLOR_ID_GREEN>;
  34                         function = LED_FUNCTION_LAN;
  35                         function-enumerator = <2>;
  36                         gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
  37                 };
  38
  39                 power_led: led-power {
  40                         color = <LED_COLOR_ID_RED>;
  41                         function = LED_FUNCTION_POWER;
  42                         linux,default-trigger = "heartbeat";
  43                         gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
  44                 };
  45
  46                 led-wan {
  47                         color = <LED_COLOR_ID_GREEN>;
  48                         function = LED_FUNCTION_WAN;
  49                         gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
  50                 };
  51         };
  52 };
  53
  54 &gmac0 {
  55         assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
  56         assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
  57         assigned-clock-rates = <0>, <125000000>;
  58         clock_in_out = "output";
  59         phy-handle = <&rgmii_phy0>;
  60         phy-mode = "rgmii";
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&gmac0_miim
  63                      &gmac0_tx_bus2
  64                      &gmac0_rx_bus2
  65                      &gmac0_rgmii_clk
  66                      &gmac0_rgmii_bus>;
  67         snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
  68         snps,reset-active-low;
  69         /* Reset time is 15ms, 50ms for rtl8211f */
  70         snps,reset-delays-us = <0 15000 50000>;
  71         tx_delay = <0x3c>;
  72         rx_delay = <0x2f>;
  73         status = "okay";
  74 };
  75
  76 &mdio0 {
  77         rgmii_phy0: ethernet-phy@1 {
  78                 compatible = "ethernet-phy-ieee802.3-c22";
  79                 reg = <1>;
  80                 pinctrl-0 = <&eth_phy0_reset_pin>;
  81                 pinctrl-names = "default";
  82         };
  83 };
  84
  85 &pcie2x1 {
  86         num-lanes = <1>;
  87         reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
  88         status = "okay";
  89 };
  90
  91 &pcie30phy {
  92         data-lanes = <1 2>;
  93         status = "okay";
  94 };
  95
  96 &pcie3x1 {
  97         num-lanes = <1>;
  98         reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
  99         vpcie3v3-supply = <&vcc3v3_pcie>;
 100         status = "okay";
 101 };
 102
 103 &pcie3x2 {
 104         num-lanes = <1>;
 105         num-ib-windows = <8>;
 106         num-ob-windows = <8>;
 107         reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
 108         vpcie3v3-supply = <&vcc3v3_pcie>;
 109         status = "okay";
 110 };
 111
 112 &pinctrl {
 113         gmac0 {
 114                 eth_phy0_reset_pin: eth-phy0-reset-pin {
 115                         rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
 116                 };
 117         };
 118
 119         gpio-leds {
 120                 lan1_led_pin: lan1-led-pin {
 121                         rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
 122                 };
 123
 124                 lan2_led_pin: lan2-led-pin {
 125                         rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
 126                 };
 127
 128                 power_led_pin: power-led-pin {
 129                         rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 130                 };
 131
 132                 wan_led_pin: wan-led-pin {
 133                         rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
 134                 };
 135         };
 136 };