1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Author: Frank Wunderlich <frank-w@public-files.de>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
12 #include "rk3568.dtsi"
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
26 stdout-path = "serial2:1500000n8";
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&blue_led_pin &green_led_pin>;
35 color = <LED_COLOR_ID_BLUE>;
36 default-state = "off";
37 function = LED_FUNCTION_STATUS;
38 gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
42 color = <LED_COLOR_ID_GREEN>;
44 function = LED_FUNCTION_POWER;
45 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
49 dc_12v: dc-12v-regulator {
50 compatible = "regulator-fixed";
51 regulator-name = "dc_12v";
54 regulator-min-microvolt = <12000000>;
55 regulator-max-microvolt = <12000000>;
59 compatible = "hdmi-connector";
63 hdmi_con_in: endpoint {
64 remote-endpoint = <&hdmi_out_con>;
70 compatible = "gpio-ir-receiver";
71 gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&ir_receiver_pin>;
76 vcc3v3_sys: vcc3v3-sys-regulator {
77 compatible = "regulator-fixed";
78 regulator-name = "vcc3v3_sys";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 vin-supply = <&dc_12v>;
86 vcc5v0_sys: vcc5v0-sys-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "vcc5v0_sys";
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
93 vin-supply = <&dc_12v>;
96 pcie30_avdd0v9: pcie30-avdd0v9-regulator {
97 compatible = "regulator-fixed";
98 regulator-name = "pcie30_avdd0v9";
101 regulator-min-microvolt = <900000>;
102 regulator-max-microvolt = <900000>;
103 vin-supply = <&vcc3v3_sys>;
106 pcie30_avdd1v8: pcie30-avdd1v8-regulator {
107 compatible = "regulator-fixed";
108 regulator-name = "pcie30_avdd1v8";
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>;
113 vin-supply = <&vcc3v3_sys>;
116 /* pi6c pcie clock generator feeds both ports */
117 vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
118 compatible = "regulator-fixed";
119 regulator-name = "vcc3v3_pcie";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
123 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
124 startup-delay-us = <200000>;
125 vin-supply = <&vcc5v0_sys>;
128 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
129 vcc3v3_minipcie: vcc3v3-minipcie-regulator {
130 compatible = "regulator-fixed";
131 regulator-name = "vcc3v3_minipcie";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
135 gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&minipcie_enable_h>;
138 startup-delay-us = <50000>;
139 vin-supply = <&vcc3v3_pi6c_05>;
142 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
143 vcc3v3_ngff: vcc3v3-ngff-regulator {
144 compatible = "regulator-fixed";
145 regulator-name = "vcc3v3_ngff";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
149 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&ngffpcie_enable_h>;
152 startup-delay-us = <50000>;
153 vin-supply = <&vcc3v3_pi6c_05>;
156 vcc5v0_usb: vcc5v0-usb-regulator {
157 compatible = "regulator-fixed";
158 regulator-name = "vcc5v0_usb";
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
163 vin-supply = <&dc_12v>;
166 vcc5v0_usb_host: vcc5v0-usb-host-regulator {
167 compatible = "regulator-fixed";
169 gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&vcc5v0_usb_host_en>;
172 regulator-name = "vcc5v0_usb_host";
173 regulator-min-microvolt = <5000000>;
174 regulator-max-microvolt = <5000000>;
175 vin-supply = <&vcc5v0_usb>;
178 vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
179 compatible = "regulator-fixed";
181 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&vcc5v0_usb_otg_en>;
184 regulator-name = "vcc5v0_usb_otg";
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5000000>;
187 vin-supply = <&vcc5v0_usb>;
207 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
208 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
209 clock_in_out = "input";
211 pinctrl-names = "default";
212 pinctrl-0 = <&gmac0_miim
217 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
218 snps,reset-active-low;
219 /* Reset time is 20ms, 100ms for rtl8211f */
220 snps,reset-delays-us = <0 20000 100000>;
233 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
234 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
235 clock_in_out = "output";
236 phy-handle = <&rgmii_phy1>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&gmac1m1_miim
245 snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
246 snps,reset-active-low;
247 /* Reset time is 20ms, 100ms for rtl8211f */
248 snps,reset-delays-us = <0 20000 100000>;
257 mali-supply = <&vdd_gpu>;
262 avdd-0v9-supply = <&vdda0v9_image>;
263 avdd-1v8-supply = <&vcca1v8_image>;
268 hdmi_in_vp0: endpoint {
269 remote-endpoint = <&vp0_out_hdmi>;
274 hdmi_out_con: endpoint {
275 remote-endpoint = <&hdmi_con_in>;
287 compatible = "rockchip,rk809";
289 interrupt-parent = <&gpio0>;
290 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pmic_int>;
294 rockchip,system-power-controller;
295 vcc1-supply = <&vcc3v3_sys>;
296 vcc2-supply = <&vcc3v3_sys>;
297 vcc3-supply = <&vcc3v3_sys>;
298 vcc4-supply = <&vcc3v3_sys>;
299 vcc5-supply = <&vcc3v3_sys>;
300 vcc6-supply = <&vcc3v3_sys>;
301 vcc7-supply = <&vcc3v3_sys>;
302 vcc8-supply = <&vcc3v3_sys>;
303 vcc9-supply = <&vcc3v3_sys>;
307 vdd_logic: DCDC_REG1 {
308 regulator-name = "vdd_logic";
311 regulator-initial-mode = <0x2>;
312 regulator-min-microvolt = <500000>;
313 regulator-max-microvolt = <1350000>;
314 regulator-ramp-delay = <6001>;
316 regulator-state-mem {
317 regulator-off-in-suspend;
322 regulator-name = "vdd_gpu";
324 regulator-initial-mode = <0x2>;
325 regulator-min-microvolt = <500000>;
326 regulator-max-microvolt = <1350000>;
327 regulator-ramp-delay = <6001>;
329 regulator-state-mem {
330 regulator-off-in-suspend;
335 regulator-name = "vcc_ddr";
338 regulator-initial-mode = <0x2>;
340 regulator-state-mem {
341 regulator-on-in-suspend;
346 regulator-name = "vdd_npu";
347 regulator-initial-mode = <0x2>;
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1350000>;
350 regulator-ramp-delay = <6001>;
352 regulator-state-mem {
353 regulator-off-in-suspend;
358 regulator-name = "vcc_1v8";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
364 regulator-state-mem {
365 regulator-off-in-suspend;
369 vdda0v9_image: LDO_REG1 {
370 regulator-name = "vdda0v9_image";
372 regulator-min-microvolt = <900000>;
373 regulator-max-microvolt = <900000>;
375 regulator-state-mem {
376 regulator-off-in-suspend;
381 regulator-name = "vdda_0v9";
384 regulator-min-microvolt = <900000>;
385 regulator-max-microvolt = <900000>;
387 regulator-state-mem {
388 regulator-off-in-suspend;
392 vdda0v9_pmu: LDO_REG3 {
393 regulator-name = "vdda0v9_pmu";
396 regulator-min-microvolt = <900000>;
397 regulator-max-microvolt = <900000>;
399 regulator-state-mem {
400 regulator-on-in-suspend;
401 regulator-suspend-microvolt = <900000>;
405 vccio_acodec: LDO_REG4 {
406 regulator-name = "vccio_acodec";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
412 regulator-state-mem {
413 regulator-off-in-suspend;
418 regulator-name = "vccio_sd";
419 regulator-min-microvolt = <1800000>;
420 regulator-max-microvolt = <3300000>;
422 regulator-state-mem {
423 regulator-off-in-suspend;
427 vcc3v3_pmu: LDO_REG6 {
428 regulator-name = "vcc3v3_pmu";
431 regulator-min-microvolt = <3300000>;
432 regulator-max-microvolt = <3300000>;
434 regulator-state-mem {
435 regulator-on-in-suspend;
436 regulator-suspend-microvolt = <3300000>;
441 regulator-name = "vcca_1v8";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
447 regulator-state-mem {
448 regulator-off-in-suspend;
452 vcca1v8_pmu: LDO_REG8 {
453 regulator-name = "vcca1v8_pmu";
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
459 regulator-state-mem {
460 regulator-on-in-suspend;
461 regulator-suspend-microvolt = <1800000>;
465 vcca1v8_image: LDO_REG9 {
466 regulator-name = "vcca1v8_image";
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <1800000>;
471 regulator-state-mem {
472 regulator-off-in-suspend;
476 vcc_3v3: SWITCH_REG1 {
477 regulator-name = "vcc_3v3";
481 regulator-state-mem {
482 regulator-off-in-suspend;
486 vcc3v3_sd: SWITCH_REG2 {
487 regulator-name = "vcc3v3_sd";
490 regulator-state-mem {
491 regulator-off-in-suspend;
502 compatible = "haoyu,hym8563";
504 interrupt-parent = <&gpio0>;
505 interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
507 clock-output-names = "rtcic_32kout";
508 pinctrl-names = "default";
509 pinctrl-0 = <&hym8563_int>;
515 /* pin 3 (SDA) + 4 (SCL) of header con2 */
525 #address-cells = <1>;
529 compatible = "mediatek,mt7531";
533 #address-cells = <1>;
573 rgmii_phy1: ethernet-phy@0 {
574 compatible = "ethernet-phy-ieee802.3-c22";
581 phy-supply = <&vcc3v3_pi6c_05>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&ngffpcie_reset_h>;
590 reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
591 vpcie3v3-supply = <&vcc3v3_ngff>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&minipcie_reset_h>;
600 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
601 vpcie3v3-supply = <&vcc3v3_minipcie>;
607 blue_led_pin: blue-led-pin {
608 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
610 green_led_pin: green-led-pin {
611 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
616 hym8563_int: hym8563-int {
617 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
622 ir_receiver_pin: ir-receiver-pin {
623 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
628 minipcie_enable_h: minipcie-enable-h {
629 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
632 ngffpcie_enable_h: ngffpcie-enable-h {
633 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
636 minipcie_reset_h: minipcie-reset-h {
637 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
640 ngffpcie_reset_h: ngffpcie-reset-h {
641 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
648 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
653 vcc5v0_usb_host_en: vcc5v0_usb_host_en {
654 rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
657 vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
658 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
664 pmuio1-supply = <&vcc3v3_pmu>;
665 pmuio2-supply = <&vcc3v3_pmu>;
666 vccio1-supply = <&vccio_acodec>;
667 vccio3-supply = <&vccio_sd>;
668 vccio4-supply = <&vcc_3v3>;
669 vccio5-supply = <&vcc_3v3>;
670 vccio6-supply = <&vcc_1v8>;
671 vccio7-supply = <&vcc_3v3>;
676 /* fan 5v - gnd - pwm */
681 /* pin 7 of header con2 */
686 /* pin 15 of header con2 */
691 /* pin 21 of header con2 */
692 /* shared with uart9 + spi3 */
693 pinctrl-0 = <&pwm12m1_pins>;
698 /* pin 24 of header con2 */
699 /* shared with uart9 */
700 pinctrl-0 = <&pwm13m1_pins>;
705 /* pin 23 of header con2 */
706 /* shared with spi3 */
707 pinctrl-0 = <&pwm14m1_pins>;
712 /* pin 19 of header con2 */
713 /* shared with spi3 */
714 pinctrl-0 = <&pwm15m1_pins>;
719 vref-supply = <&vcca_1v8>;
729 max-frequency = <200000000>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
739 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
744 vmmc-supply = <&vcc3v3_sd>;
745 vqmmc-supply = <&vccio_sd>;
750 /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
751 /* shared with pwm12/14/15 and uart9 */
752 pinctrl-0 = <&spi3m1_pins>;
757 rockchip,hw-tshut-mode = <1>;
758 rockchip,hw-tshut-polarity = <0>;
763 /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
773 /* pin 11 (TX) + 13 (RX) of header con2 */
774 pinctrl-0 = <&uart7m1_xfer>;
779 /* pin 21 (TX) + 24 (RX) of header con2 */
780 /* shared with pwm13 and pwm12/spi3 */
781 pinctrl-0 = <&uart9m1_xfer>;
815 phy-supply = <&vcc5v0_usb_host>;
820 phy-supply = <&vcc5v0_usb_otg>;
825 /* USB for PCIe/M2 */
838 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
839 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
848 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
849 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
850 remote-endpoint = <&hdmi_in_vp0>;