1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Author: Frank Wunderlich <frank-w@public-files.de>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
12 #include "rk3568.dtsi"
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
26 stdout-path = "serial2:1500000n8";
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&blue_led_pin &green_led_pin>;
35 color = <LED_COLOR_ID_BLUE>;
36 default-state = "off";
37 function = LED_FUNCTION_STATUS;
38 gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
42 color = <LED_COLOR_ID_GREEN>;
44 function = LED_FUNCTION_POWER;
45 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
49 dc_12v: dc-12v-regulator {
50 compatible = "regulator-fixed";
51 regulator-name = "dc_12v";
54 regulator-min-microvolt = <12000000>;
55 regulator-max-microvolt = <12000000>;
59 compatible = "hdmi-connector";
63 hdmi_con_in: endpoint {
64 remote-endpoint = <&hdmi_out_con>;
69 vcc3v3_sys: vcc3v3-sys-regulator {
70 compatible = "regulator-fixed";
71 regulator-name = "vcc3v3_sys";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 vin-supply = <&dc_12v>;
79 vcc5v0_sys: vcc5v0-sys-regulator {
80 compatible = "regulator-fixed";
81 regulator-name = "vcc5v0_sys";
84 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <5000000>;
86 vin-supply = <&dc_12v>;
89 pcie30_avdd0v9: pcie30-avdd0v9-regulator {
90 compatible = "regulator-fixed";
91 regulator-name = "pcie30_avdd0v9";
94 regulator-min-microvolt = <900000>;
95 regulator-max-microvolt = <900000>;
96 vin-supply = <&vcc3v3_sys>;
99 pcie30_avdd1v8: pcie30-avdd1v8-regulator {
100 compatible = "regulator-fixed";
101 regulator-name = "pcie30_avdd1v8";
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <1800000>;
106 vin-supply = <&vcc3v3_sys>;
109 /* pi6c pcie clock generator feeds both ports */
110 vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
111 compatible = "regulator-fixed";
112 regulator-name = "vcc3v3_pcie";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
116 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
117 startup-delay-us = <200000>;
118 vin-supply = <&vcc5v0_sys>;
121 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
122 vcc3v3_minipcie: vcc3v3-minipcie-regulator {
123 compatible = "regulator-fixed";
124 regulator-name = "vcc3v3_minipcie";
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
128 gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&minipcie_enable_h>;
131 startup-delay-us = <50000>;
132 vin-supply = <&vcc3v3_pi6c_05>;
135 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
136 vcc3v3_ngff: vcc3v3-ngff-regulator {
137 compatible = "regulator-fixed";
138 regulator-name = "vcc3v3_ngff";
139 regulator-min-microvolt = <3300000>;
140 regulator-max-microvolt = <3300000>;
142 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&ngffpcie_enable_h>;
145 startup-delay-us = <50000>;
146 vin-supply = <&vcc3v3_pi6c_05>;
149 vcc5v0_usb: vcc5v0-usb-regulator {
150 compatible = "regulator-fixed";
151 regulator-name = "vcc5v0_usb";
154 regulator-min-microvolt = <5000000>;
155 regulator-max-microvolt = <5000000>;
156 vin-supply = <&dc_12v>;
159 vcc5v0_usb_host: vcc5v0-usb-host-regulator {
160 compatible = "regulator-fixed";
162 gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&vcc5v0_usb_host_en>;
165 regulator-name = "vcc5v0_usb_host";
166 regulator-min-microvolt = <5000000>;
167 regulator-max-microvolt = <5000000>;
168 vin-supply = <&vcc5v0_usb>;
171 vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
172 compatible = "regulator-fixed";
174 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&vcc5v0_usb_otg_en>;
177 regulator-name = "vcc5v0_usb_otg";
178 regulator-min-microvolt = <5000000>;
179 regulator-max-microvolt = <5000000>;
180 vin-supply = <&vcc5v0_usb>;
200 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
201 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
202 clock_in_out = "input";
204 pinctrl-names = "default";
205 pinctrl-0 = <&gmac0_miim
210 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
211 snps,reset-active-low;
212 /* Reset time is 20ms, 100ms for rtl8211f */
213 snps,reset-delays-us = <0 20000 100000>;
226 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
227 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
228 clock_in_out = "output";
229 phy-handle = <&rgmii_phy1>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&gmac1m1_miim
238 snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
239 snps,reset-active-low;
240 /* Reset time is 20ms, 100ms for rtl8211f */
241 snps,reset-delays-us = <0 20000 100000>;
250 mali-supply = <&vdd_gpu>;
255 avdd-0v9-supply = <&vdda0v9_image>;
256 avdd-1v8-supply = <&vcca1v8_image>;
261 hdmi_in_vp0: endpoint {
262 remote-endpoint = <&vp0_out_hdmi>;
267 hdmi_out_con: endpoint {
268 remote-endpoint = <&hdmi_con_in>;
280 compatible = "rockchip,rk809";
282 interrupt-parent = <&gpio0>;
283 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pmic_int>;
287 rockchip,system-power-controller;
288 vcc1-supply = <&vcc3v3_sys>;
289 vcc2-supply = <&vcc3v3_sys>;
290 vcc3-supply = <&vcc3v3_sys>;
291 vcc4-supply = <&vcc3v3_sys>;
292 vcc5-supply = <&vcc3v3_sys>;
293 vcc6-supply = <&vcc3v3_sys>;
294 vcc7-supply = <&vcc3v3_sys>;
295 vcc8-supply = <&vcc3v3_sys>;
296 vcc9-supply = <&vcc3v3_sys>;
300 vdd_logic: DCDC_REG1 {
301 regulator-name = "vdd_logic";
304 regulator-init-microvolt = <900000>;
305 regulator-initial-mode = <0x2>;
306 regulator-min-microvolt = <500000>;
307 regulator-max-microvolt = <1350000>;
308 regulator-ramp-delay = <6001>;
310 regulator-state-mem {
311 regulator-off-in-suspend;
316 regulator-name = "vdd_gpu";
318 regulator-init-microvolt = <900000>;
319 regulator-initial-mode = <0x2>;
320 regulator-min-microvolt = <500000>;
321 regulator-max-microvolt = <1350000>;
322 regulator-ramp-delay = <6001>;
324 regulator-state-mem {
325 regulator-off-in-suspend;
330 regulator-name = "vcc_ddr";
333 regulator-initial-mode = <0x2>;
335 regulator-state-mem {
336 regulator-on-in-suspend;
341 regulator-name = "vdd_npu";
342 regulator-init-microvolt = <900000>;
343 regulator-initial-mode = <0x2>;
344 regulator-min-microvolt = <500000>;
345 regulator-max-microvolt = <1350000>;
346 regulator-ramp-delay = <6001>;
348 regulator-state-mem {
349 regulator-off-in-suspend;
354 regulator-name = "vcc_1v8";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
360 regulator-state-mem {
361 regulator-off-in-suspend;
365 vdda0v9_image: LDO_REG1 {
366 regulator-name = "vdda0v9_image";
368 regulator-min-microvolt = <900000>;
369 regulator-max-microvolt = <900000>;
371 regulator-state-mem {
372 regulator-off-in-suspend;
377 regulator-name = "vdda_0v9";
380 regulator-min-microvolt = <900000>;
381 regulator-max-microvolt = <900000>;
383 regulator-state-mem {
384 regulator-off-in-suspend;
388 vdda0v9_pmu: LDO_REG3 {
389 regulator-name = "vdda0v9_pmu";
392 regulator-min-microvolt = <900000>;
393 regulator-max-microvolt = <900000>;
395 regulator-state-mem {
396 regulator-on-in-suspend;
397 regulator-suspend-microvolt = <900000>;
401 vccio_acodec: LDO_REG4 {
402 regulator-name = "vccio_acodec";
405 regulator-min-microvolt = <3300000>;
406 regulator-max-microvolt = <3300000>;
408 regulator-state-mem {
409 regulator-off-in-suspend;
414 regulator-name = "vccio_sd";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <3300000>;
420 regulator-state-mem {
421 regulator-off-in-suspend;
425 vcc3v3_pmu: LDO_REG6 {
426 regulator-name = "vcc3v3_pmu";
429 regulator-min-microvolt = <3300000>;
430 regulator-max-microvolt = <3300000>;
432 regulator-state-mem {
433 regulator-on-in-suspend;
434 regulator-suspend-microvolt = <3300000>;
439 regulator-name = "vcca_1v8";
442 regulator-min-microvolt = <1800000>;
443 regulator-max-microvolt = <1800000>;
445 regulator-state-mem {
446 regulator-off-in-suspend;
450 vcca1v8_pmu: LDO_REG8 {
451 regulator-name = "vcca1v8_pmu";
454 regulator-min-microvolt = <1800000>;
455 regulator-max-microvolt = <1800000>;
457 regulator-state-mem {
458 regulator-on-in-suspend;
459 regulator-suspend-microvolt = <1800000>;
463 vcca1v8_image: LDO_REG9 {
464 regulator-name = "vcca1v8_image";
466 regulator-min-microvolt = <1800000>;
467 regulator-max-microvolt = <1800000>;
469 regulator-state-mem {
470 regulator-off-in-suspend;
474 vcc_3v3: SWITCH_REG1 {
475 regulator-name = "vcc_3v3";
479 regulator-state-mem {
480 regulator-off-in-suspend;
484 vcc3v3_sd: SWITCH_REG2 {
485 regulator-name = "vcc3v3_sd";
488 regulator-state-mem {
489 regulator-off-in-suspend;
500 compatible = "haoyu,hym8563";
502 interrupt-parent = <&gpio0>;
503 interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
505 clock-output-names = "rtcic_32kout";
506 pinctrl-names = "default";
507 pinctrl-0 = <&hym8563_int>;
513 /* pin 3 (SDA) + 4 (SCL) of header con2 */
523 #address-cells = <1>;
527 compatible = "mediatek,mt7531";
531 #address-cells = <1>;
571 rgmii_phy1: ethernet-phy@0 {
572 compatible = "ethernet-phy-ieee802.3-c22";
579 phy-supply = <&vcc3v3_pi6c_05>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&ngffpcie_reset_h>;
588 reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
589 vpcie3v3-supply = <&vcc3v3_ngff>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&minipcie_reset_h>;
598 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
599 vpcie3v3-supply = <&vcc3v3_minipcie>;
605 blue_led_pin: blue-led-pin {
606 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
608 green_led_pin: green-led-pin {
609 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
614 hym8563_int: hym8563-int {
615 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
620 minipcie_enable_h: minipcie-enable-h {
621 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
624 ngffpcie_enable_h: ngffpcie-enable-h {
625 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
628 minipcie_reset_h: minipcie-reset-h {
629 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
632 ngffpcie_reset_h: ngffpcie-reset-h {
633 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
640 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
645 vcc5v0_usb_host_en: vcc5v0_usb_host_en {
646 rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
649 vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
650 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
656 pmuio1-supply = <&vcc3v3_pmu>;
657 pmuio2-supply = <&vcc3v3_pmu>;
658 vccio1-supply = <&vccio_acodec>;
659 vccio3-supply = <&vccio_sd>;
660 vccio4-supply = <&vcc_3v3>;
661 vccio5-supply = <&vcc_3v3>;
662 vccio6-supply = <&vcc_1v8>;
663 vccio7-supply = <&vcc_3v3>;
668 /* fan 5v - gnd - pwm */
673 /* pin 7 of header con2 */
678 /* pin 15 of header con2 */
683 /* pin 21 of header con2 */
684 /* shared with uart9 + spi3 */
685 pinctrl-0 = <&pwm12m1_pins>;
690 /* pin 24 of header con2 */
691 /* shared with uart9 */
692 pinctrl-0 = <&pwm13m1_pins>;
697 /* pin 23 of header con2 */
698 /* shared with spi3 */
699 pinctrl-0 = <&pwm14m1_pins>;
704 /* pin 19 of header con2 */
705 /* shared with spi3 */
706 pinctrl-0 = <&pwm15m1_pins>;
711 vref-supply = <&vcca_1v8>;
721 max-frequency = <200000000>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
731 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
733 pinctrl-names = "default";
734 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
736 vmmc-supply = <&vcc3v3_sd>;
737 vqmmc-supply = <&vccio_sd>;
742 /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
743 /* shared with pwm12/14/15 and uart9 */
744 pinctrl-0 = <&spi3m1_pins>;
749 rockchip,hw-tshut-mode = <1>;
750 rockchip,hw-tshut-polarity = <0>;
755 /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
765 /* pin 11 (TX) + 13 (RX) of header con2 */
766 pinctrl-0 = <&uart7m1_xfer>;
771 /* pin 21 (TX) + 24 (RX) of header con2 */
772 /* shared with pwm13 and pwm12/spi3 */
773 pinctrl-0 = <&uart9m1_xfer>;
807 phy-supply = <&vcc5v0_usb_host>;
812 phy-supply = <&vcc5v0_usb_otg>;
817 /* USB for PCIe/M2 */
830 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
831 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
840 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
841 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
842 remote-endpoint = <&hdmi_in_vp0>;