1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 capacity-dmips-mhz = <485>;
78 clocks = <&cru ARMCLKL>;
79 #cooling-cells = <2>; /* min followed by max */
80 dynamic-power-coefficient = <100>;
81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
89 capacity-dmips-mhz = <485>;
90 clocks = <&cru ARMCLKL>;
91 #cooling-cells = <2>; /* min followed by max */
92 dynamic-power-coefficient = <100>;
93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
98 compatible = "arm,cortex-a53";
100 enable-method = "psci";
101 capacity-dmips-mhz = <485>;
102 clocks = <&cru ARMCLKL>;
103 #cooling-cells = <2>; /* min followed by max */
104 dynamic-power-coefficient = <100>;
105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
114 clocks = <&cru ARMCLKL>;
115 #cooling-cells = <2>; /* min followed by max */
116 dynamic-power-coefficient = <100>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 compatible = "arm,cortex-a72";
124 enable-method = "psci";
125 capacity-dmips-mhz = <1024>;
126 clocks = <&cru ARMCLKB>;
127 #cooling-cells = <2>; /* min followed by max */
128 dynamic-power-coefficient = <436>;
129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
134 compatible = "arm,cortex-a72";
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 clocks = <&cru ARMCLKB>;
139 #cooling-cells = <2>; /* min followed by max */
140 dynamic-power-coefficient = <436>;
141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
145 entry-method = "psci";
147 CPU_SLEEP: cpu-sleep {
148 compatible = "arm,idle-state";
150 arm,psci-suspend-param = <0x0010000>;
151 entry-latency-us = <120>;
152 exit-latency-us = <250>;
153 min-residency-us = <900>;
156 CLUSTER_SLEEP: cluster-sleep {
157 compatible = "arm,idle-state";
159 arm,psci-suspend-param = <0x1010000>;
160 entry-latency-us = <400>;
161 exit-latency-us = <500>;
162 min-residency-us = <2000>;
168 compatible = "rockchip,display-subsystem";
169 ports = <&vopl_out>, <&vopb_out>;
173 compatible = "arm,cortex-a53-pmu";
174 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
178 compatible = "arm,cortex-a72-pmu";
179 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
183 compatible = "arm,psci-1.0";
188 compatible = "arm,armv8-timer";
189 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
190 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
191 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
192 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
193 arm,no-tick-in-suspend;
197 compatible = "fixed-clock";
198 clock-frequency = <24000000>;
199 clock-output-names = "xin24m";
204 compatible = "simple-bus";
205 #address-cells = <2>;
209 dmac_bus: dma-controller@ff6d0000 {
210 compatible = "arm,pl330", "arm,primecell";
211 reg = <0x0 0xff6d0000 0x0 0x4000>;
212 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
215 clocks = <&cru ACLK_DMAC0_PERILP>;
216 clock-names = "apb_pclk";
219 dmac_peri: dma-controller@ff6e0000 {
220 compatible = "arm,pl330", "arm,primecell";
221 reg = <0x0 0xff6e0000 0x0 0x4000>;
222 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
223 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
225 clocks = <&cru ACLK_DMAC1_PERILP>;
226 clock-names = "apb_pclk";
230 pcie0: pcie@f8000000 {
231 compatible = "rockchip,rk3399-pcie";
232 reg = <0x0 0xf8000000 0x0 0x2000000>,
233 <0x0 0xfd000000 0x0 0x1000000>;
234 reg-names = "axi-base", "apb-base";
236 #address-cells = <3>;
238 #interrupt-cells = <1>;
240 bus-range = <0x0 0x1f>;
241 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
242 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
243 clock-names = "aclk", "aclk-perf",
245 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
246 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
247 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
248 interrupt-names = "sys", "legacy", "client";
249 interrupt-map-mask = <0 0 0 7>;
250 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
251 <0 0 0 2 &pcie0_intc 1>,
252 <0 0 0 3 &pcie0_intc 2>,
253 <0 0 0 4 &pcie0_intc 3>;
254 max-link-speed = <1>;
255 msi-map = <0x0 &its 0x0 0x1000>;
256 phys = <&pcie_phy 0>, <&pcie_phy 1>,
257 <&pcie_phy 2>, <&pcie_phy 3>;
258 phy-names = "pcie-phy-0", "pcie-phy-1",
259 "pcie-phy-2", "pcie-phy-3";
260 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
261 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
262 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
263 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
264 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
266 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
267 "pm", "pclk", "aclk";
270 pcie0_intc: interrupt-controller {
271 interrupt-controller;
272 #address-cells = <0>;
273 #interrupt-cells = <1>;
277 gmac: ethernet@fe300000 {
278 compatible = "rockchip,rk3399-gmac";
279 reg = <0x0 0xfe300000 0x0 0x10000>;
280 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
281 interrupt-names = "macirq";
282 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
283 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
284 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
286 clock-names = "stmmaceth", "mac_clk_rx",
287 "mac_clk_tx", "clk_mac_ref",
288 "clk_mac_refout", "aclk_mac",
290 power-domains = <&power RK3399_PD_GMAC>;
291 resets = <&cru SRST_A_GMAC>;
292 reset-names = "stmmaceth";
293 rockchip,grf = <&grf>;
297 sdio0: dwmmc@fe310000 {
298 compatible = "rockchip,rk3399-dw-mshc",
299 "rockchip,rk3288-dw-mshc";
300 reg = <0x0 0xfe310000 0x0 0x4000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
302 max-frequency = <150000000>;
303 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
304 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
305 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
306 fifo-depth = <0x100>;
307 power-domains = <&power RK3399_PD_SDIOAUDIO>;
308 resets = <&cru SRST_SDIO0>;
309 reset-names = "reset";
313 sdmmc: dwmmc@fe320000 {
314 compatible = "rockchip,rk3399-dw-mshc",
315 "rockchip,rk3288-dw-mshc";
316 reg = <0x0 0xfe320000 0x0 0x4000>;
317 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
318 max-frequency = <150000000>;
319 assigned-clocks = <&cru HCLK_SD>;
320 assigned-clock-rates = <200000000>;
321 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
322 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
323 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
324 fifo-depth = <0x100>;
325 power-domains = <&power RK3399_PD_SD>;
326 resets = <&cru SRST_SDMMC>;
327 reset-names = "reset";
331 sdhci: sdhci@fe330000 {
332 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
333 reg = <0x0 0xfe330000 0x0 0x10000>;
334 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
335 arasan,soc-ctl-syscon = <&grf>;
336 assigned-clocks = <&cru SCLK_EMMC>;
337 assigned-clock-rates = <200000000>;
338 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
339 clock-names = "clk_xin", "clk_ahb";
340 clock-output-names = "emmc_cardclock";
343 phy-names = "phy_arasan";
344 power-domains = <&power RK3399_PD_EMMC>;
349 usb_host0_ehci: usb@fe380000 {
350 compatible = "generic-ehci";
351 reg = <0x0 0xfe380000 0x0 0x20000>;
352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
353 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
355 clock-names = "usbhost", "arbiter",
357 phys = <&u2phy0_host>;
362 usb_host0_ohci: usb@fe3a0000 {
363 compatible = "generic-ohci";
364 reg = <0x0 0xfe3a0000 0x0 0x20000>;
365 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
366 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
368 clock-names = "usbhost", "arbiter",
370 phys = <&u2phy0_host>;
375 usb_host1_ehci: usb@fe3c0000 {
376 compatible = "generic-ehci";
377 reg = <0x0 0xfe3c0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
379 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
381 clock-names = "usbhost", "arbiter",
383 phys = <&u2phy1_host>;
388 usb_host1_ohci: usb@fe3e0000 {
389 compatible = "generic-ohci";
390 reg = <0x0 0xfe3e0000 0x0 0x20000>;
391 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
392 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
394 clock-names = "usbhost", "arbiter",
396 phys = <&u2phy1_host>;
401 usbdrd3_0: usb@fe800000 {
402 compatible = "rockchip,rk3399-dwc3";
403 #address-cells = <2>;
406 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
407 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
408 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
409 clock-names = "ref_clk", "suspend_clk",
410 "bus_clk", "aclk_usb3_rksoc_axi_perf",
411 "aclk_usb3", "grf_clk";
412 resets = <&cru SRST_A_USB3_OTG0>;
413 reset-names = "usb3-otg";
416 usbdrd_dwc3_0: usb@fe800000 {
417 compatible = "snps,dwc3";
418 reg = <0x0 0xfe800000 0x0 0x100000>;
419 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
420 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
421 <&cru SCLK_USB3OTG0_SUSPEND>;
422 clock-names = "ref", "bus_early", "suspend";
424 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
425 phy-names = "usb2-phy", "usb3-phy";
426 phy_type = "utmi_wide";
427 snps,dis_enblslpm_quirk;
428 snps,dis-u2-freeclk-exists-quirk;
429 snps,dis_u2_susphy_quirk;
430 snps,dis-del-phy-power-chg-quirk;
431 snps,dis-tx-ipgap-linecheck-quirk;
432 power-domains = <&power RK3399_PD_USB3>;
437 usbdrd3_1: usb@fe900000 {
438 compatible = "rockchip,rk3399-dwc3";
439 #address-cells = <2>;
442 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
443 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
444 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
445 clock-names = "ref_clk", "suspend_clk",
446 "bus_clk", "aclk_usb3_rksoc_axi_perf",
447 "aclk_usb3", "grf_clk";
448 resets = <&cru SRST_A_USB3_OTG1>;
449 reset-names = "usb3-otg";
452 usbdrd_dwc3_1: usb@fe900000 {
453 compatible = "snps,dwc3";
454 reg = <0x0 0xfe900000 0x0 0x100000>;
455 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
456 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
457 <&cru SCLK_USB3OTG1_SUSPEND>;
458 clock-names = "ref", "bus_early", "suspend";
460 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
461 phy-names = "usb2-phy", "usb3-phy";
462 phy_type = "utmi_wide";
463 snps,dis_enblslpm_quirk;
464 snps,dis-u2-freeclk-exists-quirk;
465 snps,dis_u2_susphy_quirk;
466 snps,dis-del-phy-power-chg-quirk;
467 snps,dis-tx-ipgap-linecheck-quirk;
468 power-domains = <&power RK3399_PD_USB3>;
473 cdn_dp: dp@fec00000 {
474 compatible = "rockchip,rk3399-cdn-dp";
475 reg = <0x0 0xfec00000 0x0 0x100000>;
476 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
477 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
478 assigned-clock-rates = <100000000>, <200000000>;
479 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
480 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
481 clock-names = "core-clk", "pclk", "spdif", "grf";
482 phys = <&tcphy0_dp>, <&tcphy1_dp>;
483 power-domains = <&power RK3399_PD_HDCP>;
484 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
485 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
486 reset-names = "spdif", "dptx", "apb", "core";
487 rockchip,grf = <&grf>;
488 #sound-dai-cells = <1>;
493 #address-cells = <1>;
496 dp_in_vopb: endpoint@0 {
498 remote-endpoint = <&vopb_out_dp>;
501 dp_in_vopl: endpoint@1 {
503 remote-endpoint = <&vopl_out_dp>;
509 gic: interrupt-controller@fee00000 {
510 compatible = "arm,gic-v3";
511 #interrupt-cells = <4>;
512 #address-cells = <2>;
515 interrupt-controller;
517 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
518 <0x0 0xfef00000 0 0xc0000>, /* GICR */
519 <0x0 0xfff00000 0 0x10000>, /* GICC */
520 <0x0 0xfff10000 0 0x10000>, /* GICH */
521 <0x0 0xfff20000 0 0x10000>; /* GICV */
522 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
523 its: interrupt-controller@fee20000 {
524 compatible = "arm,gic-v3-its";
526 reg = <0x0 0xfee20000 0x0 0x20000>;
530 ppi_cluster0: interrupt-partition-0 {
531 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
534 ppi_cluster1: interrupt-partition-1 {
535 affinity = <&cpu_b0 &cpu_b1>;
540 saradc: saradc@ff100000 {
541 compatible = "rockchip,rk3399-saradc";
542 reg = <0x0 0xff100000 0x0 0x100>;
543 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
544 #io-channel-cells = <1>;
545 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
546 clock-names = "saradc", "apb_pclk";
547 resets = <&cru SRST_P_SARADC>;
548 reset-names = "saradc-apb";
553 compatible = "rockchip,rk3399-i2c";
554 reg = <0x0 0xff110000 0x0 0x1000>;
555 assigned-clocks = <&cru SCLK_I2C1>;
556 assigned-clock-rates = <200000000>;
557 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
558 clock-names = "i2c", "pclk";
559 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c1_xfer>;
562 #address-cells = <1>;
568 compatible = "rockchip,rk3399-i2c";
569 reg = <0x0 0xff120000 0x0 0x1000>;
570 assigned-clocks = <&cru SCLK_I2C2>;
571 assigned-clock-rates = <200000000>;
572 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
573 clock-names = "i2c", "pclk";
574 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&i2c2_xfer>;
577 #address-cells = <1>;
583 compatible = "rockchip,rk3399-i2c";
584 reg = <0x0 0xff130000 0x0 0x1000>;
585 assigned-clocks = <&cru SCLK_I2C3>;
586 assigned-clock-rates = <200000000>;
587 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
588 clock-names = "i2c", "pclk";
589 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c3_xfer>;
592 #address-cells = <1>;
598 compatible = "rockchip,rk3399-i2c";
599 reg = <0x0 0xff140000 0x0 0x1000>;
600 assigned-clocks = <&cru SCLK_I2C5>;
601 assigned-clock-rates = <200000000>;
602 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
603 clock-names = "i2c", "pclk";
604 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c5_xfer>;
607 #address-cells = <1>;
613 compatible = "rockchip,rk3399-i2c";
614 reg = <0x0 0xff150000 0x0 0x1000>;
615 assigned-clocks = <&cru SCLK_I2C6>;
616 assigned-clock-rates = <200000000>;
617 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
618 clock-names = "i2c", "pclk";
619 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c6_xfer>;
622 #address-cells = <1>;
628 compatible = "rockchip,rk3399-i2c";
629 reg = <0x0 0xff160000 0x0 0x1000>;
630 assigned-clocks = <&cru SCLK_I2C7>;
631 assigned-clock-rates = <200000000>;
632 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
633 clock-names = "i2c", "pclk";
634 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&i2c7_xfer>;
637 #address-cells = <1>;
642 uart0: serial@ff180000 {
643 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
644 reg = <0x0 0xff180000 0x0 0x100>;
645 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
646 clock-names = "baudclk", "apb_pclk";
647 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&uart0_xfer>;
655 uart1: serial@ff190000 {
656 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
657 reg = <0x0 0xff190000 0x0 0x100>;
658 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
659 clock-names = "baudclk", "apb_pclk";
660 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&uart1_xfer>;
668 uart2: serial@ff1a0000 {
669 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
670 reg = <0x0 0xff1a0000 0x0 0x100>;
671 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
672 clock-names = "baudclk", "apb_pclk";
673 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&uart2c_xfer>;
681 uart3: serial@ff1b0000 {
682 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
683 reg = <0x0 0xff1b0000 0x0 0x100>;
684 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
685 clock-names = "baudclk", "apb_pclk";
686 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&uart3_xfer>;
695 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
696 reg = <0x0 0xff1c0000 0x0 0x1000>;
697 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
698 clock-names = "spiclk", "apb_pclk";
699 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
700 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
701 dma-names = "tx", "rx";
702 pinctrl-names = "default";
703 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
704 #address-cells = <1>;
710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711 reg = <0x0 0xff1d0000 0x0 0x1000>;
712 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
713 clock-names = "spiclk", "apb_pclk";
714 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
715 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
716 dma-names = "tx", "rx";
717 pinctrl-names = "default";
718 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
719 #address-cells = <1>;
725 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
726 reg = <0x0 0xff1e0000 0x0 0x1000>;
727 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
728 clock-names = "spiclk", "apb_pclk";
729 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
730 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
731 dma-names = "tx", "rx";
732 pinctrl-names = "default";
733 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
734 #address-cells = <1>;
740 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
741 reg = <0x0 0xff1f0000 0x0 0x1000>;
742 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
743 clock-names = "spiclk", "apb_pclk";
744 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
745 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
746 dma-names = "tx", "rx";
747 pinctrl-names = "default";
748 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
749 #address-cells = <1>;
755 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
756 reg = <0x0 0xff200000 0x0 0x1000>;
757 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
758 clock-names = "spiclk", "apb_pclk";
759 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
760 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
761 dma-names = "tx", "rx";
762 pinctrl-names = "default";
763 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
764 power-domains = <&power RK3399_PD_SDIOAUDIO>;
765 #address-cells = <1>;
770 thermal_zones: thermal-zones {
772 polling-delay-passive = <100>;
773 polling-delay = <1000>;
775 thermal-sensors = <&tsadc 0>;
778 cpu_alert0: cpu_alert0 {
779 temperature = <70000>;
783 cpu_alert1: cpu_alert1 {
784 temperature = <75000>;
789 temperature = <95000>;
797 trip = <&cpu_alert0>;
799 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
800 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
803 trip = <&cpu_alert1>;
805 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
806 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
807 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
808 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
809 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
810 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
816 polling-delay-passive = <100>;
817 polling-delay = <1000>;
819 thermal-sensors = <&tsadc 1>;
822 gpu_alert0: gpu_alert0 {
823 temperature = <75000>;
828 temperature = <95000>;
836 tsadc: tsadc@ff260000 {
837 compatible = "rockchip,rk3399-tsadc";
838 reg = <0x0 0xff260000 0x0 0x100>;
839 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
840 assigned-clocks = <&cru SCLK_TSADC>;
841 assigned-clock-rates = <750000>;
842 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
843 clock-names = "tsadc", "apb_pclk";
844 resets = <&cru SRST_TSADC>;
845 reset-names = "tsadc-apb";
846 rockchip,grf = <&grf>;
847 rockchip,hw-tshut-temp = <95000>;
848 pinctrl-names = "init", "default", "sleep";
849 pinctrl-0 = <&otp_gpio>;
850 pinctrl-1 = <&otp_out>;
851 pinctrl-2 = <&otp_gpio>;
852 #thermal-sensor-cells = <1>;
856 qos_emmc: qos@ffa58000 {
857 compatible = "syscon";
858 reg = <0x0 0xffa58000 0x0 0x20>;
861 qos_gmac: qos@ffa5c000 {
862 compatible = "syscon";
863 reg = <0x0 0xffa5c000 0x0 0x20>;
866 qos_pcie: qos@ffa60080 {
867 compatible = "syscon";
868 reg = <0x0 0xffa60080 0x0 0x20>;
871 qos_usb_host0: qos@ffa60100 {
872 compatible = "syscon";
873 reg = <0x0 0xffa60100 0x0 0x20>;
876 qos_usb_host1: qos@ffa60180 {
877 compatible = "syscon";
878 reg = <0x0 0xffa60180 0x0 0x20>;
881 qos_usb_otg0: qos@ffa70000 {
882 compatible = "syscon";
883 reg = <0x0 0xffa70000 0x0 0x20>;
886 qos_usb_otg1: qos@ffa70080 {
887 compatible = "syscon";
888 reg = <0x0 0xffa70080 0x0 0x20>;
891 qos_sd: qos@ffa74000 {
892 compatible = "syscon";
893 reg = <0x0 0xffa74000 0x0 0x20>;
896 qos_sdioaudio: qos@ffa76000 {
897 compatible = "syscon";
898 reg = <0x0 0xffa76000 0x0 0x20>;
901 qos_hdcp: qos@ffa90000 {
902 compatible = "syscon";
903 reg = <0x0 0xffa90000 0x0 0x20>;
906 qos_iep: qos@ffa98000 {
907 compatible = "syscon";
908 reg = <0x0 0xffa98000 0x0 0x20>;
911 qos_isp0_m0: qos@ffaa0000 {
912 compatible = "syscon";
913 reg = <0x0 0xffaa0000 0x0 0x20>;
916 qos_isp0_m1: qos@ffaa0080 {
917 compatible = "syscon";
918 reg = <0x0 0xffaa0080 0x0 0x20>;
921 qos_isp1_m0: qos@ffaa8000 {
922 compatible = "syscon";
923 reg = <0x0 0xffaa8000 0x0 0x20>;
926 qos_isp1_m1: qos@ffaa8080 {
927 compatible = "syscon";
928 reg = <0x0 0xffaa8080 0x0 0x20>;
931 qos_rga_r: qos@ffab0000 {
932 compatible = "syscon";
933 reg = <0x0 0xffab0000 0x0 0x20>;
936 qos_rga_w: qos@ffab0080 {
937 compatible = "syscon";
938 reg = <0x0 0xffab0080 0x0 0x20>;
941 qos_video_m0: qos@ffab8000 {
942 compatible = "syscon";
943 reg = <0x0 0xffab8000 0x0 0x20>;
946 qos_video_m1_r: qos@ffac0000 {
947 compatible = "syscon";
948 reg = <0x0 0xffac0000 0x0 0x20>;
951 qos_video_m1_w: qos@ffac0080 {
952 compatible = "syscon";
953 reg = <0x0 0xffac0080 0x0 0x20>;
956 qos_vop_big_r: qos@ffac8000 {
957 compatible = "syscon";
958 reg = <0x0 0xffac8000 0x0 0x20>;
961 qos_vop_big_w: qos@ffac8080 {
962 compatible = "syscon";
963 reg = <0x0 0xffac8080 0x0 0x20>;
966 qos_vop_little: qos@ffad0000 {
967 compatible = "syscon";
968 reg = <0x0 0xffad0000 0x0 0x20>;
971 qos_perihp: qos@ffad8080 {
972 compatible = "syscon";
973 reg = <0x0 0xffad8080 0x0 0x20>;
976 qos_gpu: qos@ffae0000 {
977 compatible = "syscon";
978 reg = <0x0 0xffae0000 0x0 0x20>;
981 pmu: power-management@ff310000 {
982 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
983 reg = <0x0 0xff310000 0x0 0x1000>;
986 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
987 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
988 * Some of the power domains are grouped together for every
990 * The detail contents as below.
992 power: power-controller {
993 compatible = "rockchip,rk3399-power-controller";
994 #power-domain-cells = <1>;
995 #address-cells = <1>;
998 /* These power domains are grouped by VD_CENTER */
999 pd_iep@RK3399_PD_IEP {
1000 reg = <RK3399_PD_IEP>;
1001 clocks = <&cru ACLK_IEP>,
1003 pm_qos = <&qos_iep>;
1005 pd_rga@RK3399_PD_RGA {
1006 reg = <RK3399_PD_RGA>;
1007 clocks = <&cru ACLK_RGA>,
1009 pm_qos = <&qos_rga_r>,
1012 pd_vcodec@RK3399_PD_VCODEC {
1013 reg = <RK3399_PD_VCODEC>;
1014 clocks = <&cru ACLK_VCODEC>,
1016 pm_qos = <&qos_video_m0>;
1018 pd_vdu@RK3399_PD_VDU {
1019 reg = <RK3399_PD_VDU>;
1020 clocks = <&cru ACLK_VDU>,
1022 pm_qos = <&qos_video_m1_r>,
1026 /* These power domains are grouped by VD_GPU */
1027 pd_gpu@RK3399_PD_GPU {
1028 reg = <RK3399_PD_GPU>;
1029 clocks = <&cru ACLK_GPU>;
1030 pm_qos = <&qos_gpu>;
1033 /* These power domains are grouped by VD_LOGIC */
1034 pd_edp@RK3399_PD_EDP {
1035 reg = <RK3399_PD_EDP>;
1036 clocks = <&cru PCLK_EDP_CTRL>;
1038 pd_emmc@RK3399_PD_EMMC {
1039 reg = <RK3399_PD_EMMC>;
1040 clocks = <&cru ACLK_EMMC>;
1041 pm_qos = <&qos_emmc>;
1043 pd_gmac@RK3399_PD_GMAC {
1044 reg = <RK3399_PD_GMAC>;
1045 clocks = <&cru ACLK_GMAC>,
1047 pm_qos = <&qos_gmac>;
1049 pd_sd@RK3399_PD_SD {
1050 reg = <RK3399_PD_SD>;
1051 clocks = <&cru HCLK_SDMMC>,
1055 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1056 reg = <RK3399_PD_SDIOAUDIO>;
1057 clocks = <&cru HCLK_SDIO>;
1058 pm_qos = <&qos_sdioaudio>;
1060 pd_usb3@RK3399_PD_USB3 {
1061 reg = <RK3399_PD_USB3>;
1062 clocks = <&cru ACLK_USB3>;
1063 pm_qos = <&qos_usb_otg0>,
1066 pd_vio@RK3399_PD_VIO {
1067 reg = <RK3399_PD_VIO>;
1068 #address-cells = <1>;
1071 pd_hdcp@RK3399_PD_HDCP {
1072 reg = <RK3399_PD_HDCP>;
1073 clocks = <&cru ACLK_HDCP>,
1076 pm_qos = <&qos_hdcp>;
1078 pd_isp0@RK3399_PD_ISP0 {
1079 reg = <RK3399_PD_ISP0>;
1080 clocks = <&cru ACLK_ISP0>,
1082 pm_qos = <&qos_isp0_m0>,
1085 pd_isp1@RK3399_PD_ISP1 {
1086 reg = <RK3399_PD_ISP1>;
1087 clocks = <&cru ACLK_ISP1>,
1089 pm_qos = <&qos_isp1_m0>,
1092 pd_tcpc0@RK3399_PD_TCPC0 {
1093 reg = <RK3399_PD_TCPD0>;
1094 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1095 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1097 pd_tcpc1@RK3399_PD_TCPC1 {
1098 reg = <RK3399_PD_TCPD1>;
1099 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1100 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1102 pd_vo@RK3399_PD_VO {
1103 reg = <RK3399_PD_VO>;
1104 #address-cells = <1>;
1107 pd_vopb@RK3399_PD_VOPB {
1108 reg = <RK3399_PD_VOPB>;
1109 clocks = <&cru ACLK_VOP0>,
1111 pm_qos = <&qos_vop_big_r>,
1114 pd_vopl@RK3399_PD_VOPL {
1115 reg = <RK3399_PD_VOPL>;
1116 clocks = <&cru ACLK_VOP1>,
1118 pm_qos = <&qos_vop_little>;
1125 pmugrf: syscon@ff320000 {
1126 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1127 reg = <0x0 0xff320000 0x0 0x1000>;
1128 #address-cells = <1>;
1131 pmu_io_domains: io-domains {
1132 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1133 status = "disabled";
1137 spi3: spi@ff350000 {
1138 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1139 reg = <0x0 0xff350000 0x0 0x1000>;
1140 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1141 clock-names = "spiclk", "apb_pclk";
1142 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1145 #address-cells = <1>;
1147 status = "disabled";
1150 uart4: serial@ff370000 {
1151 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1152 reg = <0x0 0xff370000 0x0 0x100>;
1153 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1154 clock-names = "baudclk", "apb_pclk";
1155 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&uart4_xfer>;
1160 status = "disabled";
1163 i2c0: i2c@ff3c0000 {
1164 compatible = "rockchip,rk3399-i2c";
1165 reg = <0x0 0xff3c0000 0x0 0x1000>;
1166 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1167 assigned-clock-rates = <200000000>;
1168 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1169 clock-names = "i2c", "pclk";
1170 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c0_xfer>;
1173 #address-cells = <1>;
1175 status = "disabled";
1178 i2c4: i2c@ff3d0000 {
1179 compatible = "rockchip,rk3399-i2c";
1180 reg = <0x0 0xff3d0000 0x0 0x1000>;
1181 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1182 assigned-clock-rates = <200000000>;
1183 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1184 clock-names = "i2c", "pclk";
1185 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1186 pinctrl-names = "default";
1187 pinctrl-0 = <&i2c4_xfer>;
1188 #address-cells = <1>;
1190 status = "disabled";
1193 i2c8: i2c@ff3e0000 {
1194 compatible = "rockchip,rk3399-i2c";
1195 reg = <0x0 0xff3e0000 0x0 0x1000>;
1196 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1197 assigned-clock-rates = <200000000>;
1198 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1199 clock-names = "i2c", "pclk";
1200 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1201 pinctrl-names = "default";
1202 pinctrl-0 = <&i2c8_xfer>;
1203 #address-cells = <1>;
1205 status = "disabled";
1208 pwm0: pwm@ff420000 {
1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1210 reg = <0x0 0xff420000 0x0 0x10>;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pwm0_pin>;
1214 clocks = <&pmucru PCLK_RKPWM_PMU>;
1215 clock-names = "pwm";
1216 status = "disabled";
1219 pwm1: pwm@ff420010 {
1220 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1221 reg = <0x0 0xff420010 0x0 0x10>;
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&pwm1_pin>;
1225 clocks = <&pmucru PCLK_RKPWM_PMU>;
1226 clock-names = "pwm";
1227 status = "disabled";
1230 pwm2: pwm@ff420020 {
1231 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1232 reg = <0x0 0xff420020 0x0 0x10>;
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&pwm2_pin>;
1236 clocks = <&pmucru PCLK_RKPWM_PMU>;
1237 clock-names = "pwm";
1238 status = "disabled";
1241 pwm3: pwm@ff420030 {
1242 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1243 reg = <0x0 0xff420030 0x0 0x10>;
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&pwm3a_pin>;
1247 clocks = <&pmucru PCLK_RKPWM_PMU>;
1248 clock-names = "pwm";
1249 status = "disabled";
1252 vpu: video-codec@ff650000 {
1253 compatible = "rockchip,rk3399-vpu";
1254 reg = <0x0 0xff650000 0x0 0x800>;
1255 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1256 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1257 interrupt-names = "vepu", "vdpu";
1258 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1259 clock-names = "aclk", "hclk";
1260 iommus = <&vpu_mmu>;
1261 power-domains = <&power RK3399_PD_VCODEC>;
1264 vpu_mmu: iommu@ff650800 {
1265 compatible = "rockchip,iommu";
1266 reg = <0x0 0xff650800 0x0 0x40>;
1267 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1268 interrupt-names = "vpu_mmu";
1269 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1270 clock-names = "aclk", "iface";
1272 power-domains = <&power RK3399_PD_VCODEC>;
1275 vdec_mmu: iommu@ff660480 {
1276 compatible = "rockchip,iommu";
1277 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1278 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1279 interrupt-names = "vdec_mmu";
1280 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1281 clock-names = "aclk", "iface";
1283 status = "disabled";
1286 iep_mmu: iommu@ff670800 {
1287 compatible = "rockchip,iommu";
1288 reg = <0x0 0xff670800 0x0 0x40>;
1289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1290 interrupt-names = "iep_mmu";
1291 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1292 clock-names = "aclk", "iface";
1294 status = "disabled";
1298 compatible = "rockchip,rk3399-rga";
1299 reg = <0x0 0xff680000 0x0 0x10000>;
1300 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1301 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1302 clock-names = "aclk", "hclk", "sclk";
1303 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1304 reset-names = "core", "axi", "ahb";
1305 power-domains = <&power RK3399_PD_RGA>;
1308 efuse0: efuse@ff690000 {
1309 compatible = "rockchip,rk3399-efuse";
1310 reg = <0x0 0xff690000 0x0 0x80>;
1311 #address-cells = <1>;
1313 clocks = <&cru PCLK_EFUSE1024NS>;
1314 clock-names = "pclk_efuse";
1320 cpub_leakage: cpu-leakage@17 {
1323 gpu_leakage: gpu-leakage@18 {
1326 center_leakage: center-leakage@19 {
1329 cpul_leakage: cpu-leakage@1a {
1332 logic_leakage: logic-leakage@1b {
1335 wafer_info: wafer-info@1c {
1340 pmucru: pmu-clock-controller@ff750000 {
1341 compatible = "rockchip,rk3399-pmucru";
1342 reg = <0x0 0xff750000 0x0 0x1000>;
1343 rockchip,grf = <&pmugrf>;
1346 assigned-clocks = <&pmucru PLL_PPLL>;
1347 assigned-clock-rates = <676000000>;
1350 cru: clock-controller@ff760000 {
1351 compatible = "rockchip,rk3399-cru";
1352 reg = <0x0 0xff760000 0x0 0x1000>;
1353 rockchip,grf = <&grf>;
1357 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1359 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1361 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1362 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1363 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1364 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1365 <&cru ACLK_GIC_PRE>,
1367 assigned-clock-rates =
1368 <594000000>, <800000000>,
1370 <150000000>, <75000000>,
1372 <100000000>, <100000000>,
1373 <50000000>, <600000000>,
1374 <100000000>, <50000000>,
1375 <400000000>, <400000000>,
1380 grf: syscon@ff770000 {
1381 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1382 reg = <0x0 0xff770000 0x0 0x10000>;
1383 #address-cells = <1>;
1386 io_domains: io-domains {
1387 compatible = "rockchip,rk3399-io-voltage-domain";
1388 status = "disabled";
1391 u2phy0: usb2-phy@e450 {
1392 compatible = "rockchip,rk3399-usb2phy";
1393 reg = <0xe450 0x10>;
1394 clocks = <&cru SCLK_USB2PHY0_REF>;
1395 clock-names = "phyclk";
1397 clock-output-names = "clk_usbphy0_480m";
1398 status = "disabled";
1400 u2phy0_host: host-port {
1402 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1403 interrupt-names = "linestate";
1404 status = "disabled";
1407 u2phy0_otg: otg-port {
1409 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1410 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1411 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1412 interrupt-names = "otg-bvalid", "otg-id",
1414 status = "disabled";
1418 u2phy1: usb2-phy@e460 {
1419 compatible = "rockchip,rk3399-usb2phy";
1420 reg = <0xe460 0x10>;
1421 clocks = <&cru SCLK_USB2PHY1_REF>;
1422 clock-names = "phyclk";
1424 clock-output-names = "clk_usbphy1_480m";
1425 status = "disabled";
1427 u2phy1_host: host-port {
1429 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1430 interrupt-names = "linestate";
1431 status = "disabled";
1434 u2phy1_otg: otg-port {
1436 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1437 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1439 interrupt-names = "otg-bvalid", "otg-id",
1441 status = "disabled";
1445 emmc_phy: phy@f780 {
1446 compatible = "rockchip,rk3399-emmc-phy";
1447 reg = <0xf780 0x24>;
1449 clock-names = "emmcclk";
1450 drive-impedance-ohm = <50>;
1452 status = "disabled";
1455 pcie_phy: pcie-phy {
1456 compatible = "rockchip,rk3399-pcie-phy";
1457 clocks = <&cru SCLK_PCIEPHY_REF>;
1458 clock-names = "refclk";
1460 resets = <&cru SRST_PCIEPHY>;
1461 reset-names = "phy";
1462 status = "disabled";
1466 tcphy0: phy@ff7c0000 {
1467 compatible = "rockchip,rk3399-typec-phy";
1468 reg = <0x0 0xff7c0000 0x0 0x40000>;
1469 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1470 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1471 clock-names = "tcpdcore", "tcpdphy-ref";
1472 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1473 assigned-clock-rates = <50000000>;
1474 power-domains = <&power RK3399_PD_TCPD0>;
1475 resets = <&cru SRST_UPHY0>,
1476 <&cru SRST_UPHY0_PIPE_L00>,
1477 <&cru SRST_P_UPHY0_TCPHY>;
1478 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1479 rockchip,grf = <&grf>;
1480 status = "disabled";
1482 tcphy0_dp: dp-port {
1486 tcphy0_usb3: usb3-port {
1491 tcphy1: phy@ff800000 {
1492 compatible = "rockchip,rk3399-typec-phy";
1493 reg = <0x0 0xff800000 0x0 0x40000>;
1494 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1495 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1496 clock-names = "tcpdcore", "tcpdphy-ref";
1497 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1498 assigned-clock-rates = <50000000>;
1499 power-domains = <&power RK3399_PD_TCPD1>;
1500 resets = <&cru SRST_UPHY1>,
1501 <&cru SRST_UPHY1_PIPE_L00>,
1502 <&cru SRST_P_UPHY1_TCPHY>;
1503 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1504 rockchip,grf = <&grf>;
1505 status = "disabled";
1507 tcphy1_dp: dp-port {
1511 tcphy1_usb3: usb3-port {
1517 compatible = "snps,dw-wdt";
1518 reg = <0x0 0xff848000 0x0 0x100>;
1519 clocks = <&cru PCLK_WDT>;
1520 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1523 rktimer: rktimer@ff850000 {
1524 compatible = "rockchip,rk3399-timer";
1525 reg = <0x0 0xff850000 0x0 0x1000>;
1526 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1527 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1528 clock-names = "pclk", "timer";
1531 spdif: spdif@ff870000 {
1532 compatible = "rockchip,rk3399-spdif";
1533 reg = <0x0 0xff870000 0x0 0x1000>;
1534 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1535 dmas = <&dmac_bus 7>;
1537 clock-names = "mclk", "hclk";
1538 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&spdif_bus>;
1541 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1542 #sound-dai-cells = <0>;
1543 status = "disabled";
1546 i2s0: i2s@ff880000 {
1547 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1548 reg = <0x0 0xff880000 0x0 0x1000>;
1549 rockchip,grf = <&grf>;
1550 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1551 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1552 dma-names = "tx", "rx";
1553 clock-names = "i2s_clk", "i2s_hclk";
1554 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1555 pinctrl-names = "default";
1556 pinctrl-0 = <&i2s0_8ch_bus>;
1557 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1558 #sound-dai-cells = <0>;
1559 status = "disabled";
1562 i2s1: i2s@ff890000 {
1563 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1564 reg = <0x0 0xff890000 0x0 0x1000>;
1565 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1566 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1567 dma-names = "tx", "rx";
1568 clock-names = "i2s_clk", "i2s_hclk";
1569 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&i2s1_2ch_bus>;
1572 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1573 #sound-dai-cells = <0>;
1574 status = "disabled";
1577 i2s2: i2s@ff8a0000 {
1578 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1579 reg = <0x0 0xff8a0000 0x0 0x1000>;
1580 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1581 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1582 dma-names = "tx", "rx";
1583 clock-names = "i2s_clk", "i2s_hclk";
1584 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1585 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1586 #sound-dai-cells = <0>;
1587 status = "disabled";
1590 vopl: vop@ff8f0000 {
1591 compatible = "rockchip,rk3399-vop-lit";
1592 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1593 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1594 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1595 assigned-clock-rates = <400000000>, <100000000>;
1596 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1597 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1598 iommus = <&vopl_mmu>;
1599 power-domains = <&power RK3399_PD_VOPL>;
1600 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1601 reset-names = "axi", "ahb", "dclk";
1602 status = "disabled";
1605 #address-cells = <1>;
1608 vopl_out_mipi: endpoint@0 {
1610 remote-endpoint = <&mipi_in_vopl>;
1613 vopl_out_edp: endpoint@1 {
1615 remote-endpoint = <&edp_in_vopl>;
1618 vopl_out_hdmi: endpoint@2 {
1620 remote-endpoint = <&hdmi_in_vopl>;
1623 vopl_out_mipi1: endpoint@3 {
1625 remote-endpoint = <&mipi1_in_vopl>;
1628 vopl_out_dp: endpoint@4 {
1630 remote-endpoint = <&dp_in_vopl>;
1635 vopl_mmu: iommu@ff8f3f00 {
1636 compatible = "rockchip,iommu";
1637 reg = <0x0 0xff8f3f00 0x0 0x100>;
1638 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1639 interrupt-names = "vopl_mmu";
1640 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1641 clock-names = "aclk", "iface";
1642 power-domains = <&power RK3399_PD_VOPL>;
1644 status = "disabled";
1647 vopb: vop@ff900000 {
1648 compatible = "rockchip,rk3399-vop-big";
1649 reg = <0x0 0xff900000 0x0 0x3efc>;
1650 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1651 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1652 assigned-clock-rates = <400000000>, <100000000>;
1653 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1654 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1655 iommus = <&vopb_mmu>;
1656 power-domains = <&power RK3399_PD_VOPB>;
1657 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1658 reset-names = "axi", "ahb", "dclk";
1659 status = "disabled";
1662 #address-cells = <1>;
1665 vopb_out_edp: endpoint@0 {
1667 remote-endpoint = <&edp_in_vopb>;
1670 vopb_out_mipi: endpoint@1 {
1672 remote-endpoint = <&mipi_in_vopb>;
1675 vopb_out_hdmi: endpoint@2 {
1677 remote-endpoint = <&hdmi_in_vopb>;
1680 vopb_out_mipi1: endpoint@3 {
1682 remote-endpoint = <&mipi1_in_vopb>;
1685 vopb_out_dp: endpoint@4 {
1687 remote-endpoint = <&dp_in_vopb>;
1692 vopb_mmu: iommu@ff903f00 {
1693 compatible = "rockchip,iommu";
1694 reg = <0x0 0xff903f00 0x0 0x100>;
1695 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1696 interrupt-names = "vopb_mmu";
1697 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1698 clock-names = "aclk", "iface";
1699 power-domains = <&power RK3399_PD_VOPB>;
1701 status = "disabled";
1704 isp0_mmu: iommu@ff914000 {
1705 compatible = "rockchip,iommu";
1706 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1707 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1708 interrupt-names = "isp0_mmu";
1709 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1710 clock-names = "aclk", "iface";
1712 power-domains = <&power RK3399_PD_ISP0>;
1713 rockchip,disable-mmu-reset;
1716 isp1_mmu: iommu@ff924000 {
1717 compatible = "rockchip,iommu";
1718 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1719 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1720 interrupt-names = "isp1_mmu";
1721 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1722 clock-names = "aclk", "iface";
1724 power-domains = <&power RK3399_PD_ISP1>;
1725 rockchip,disable-mmu-reset;
1728 hdmi_sound: hdmi-sound {
1729 compatible = "simple-audio-card";
1730 simple-audio-card,format = "i2s";
1731 simple-audio-card,mclk-fs = <256>;
1732 simple-audio-card,name = "hdmi-sound";
1733 status = "disabled";
1735 simple-audio-card,cpu {
1736 sound-dai = <&i2s2>;
1738 simple-audio-card,codec {
1739 sound-dai = <&hdmi>;
1743 hdmi: hdmi@ff940000 {
1744 compatible = "rockchip,rk3399-dw-hdmi";
1745 reg = <0x0 0xff940000 0x0 0x20000>;
1747 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1748 clocks = <&cru PCLK_HDMI_CTRL>,
1749 <&cru SCLK_HDMI_SFR>,
1750 <&cru SCLK_HDMI_CEC>,
1751 <&cru PCLK_VIO_GRF>,
1753 clock-names = "iahb", "isfr", "cec", "grf", "vpll";
1754 power-domains = <&power RK3399_PD_HDCP>;
1755 rockchip,grf = <&grf>;
1756 #sound-dai-cells = <0>;
1757 status = "disabled";
1760 #address-cells = <1>;
1765 #address-cells = <1>;
1768 hdmi_in_vopb: endpoint@0 {
1770 remote-endpoint = <&vopb_out_hdmi>;
1772 hdmi_in_vopl: endpoint@1 {
1774 remote-endpoint = <&vopl_out_hdmi>;
1784 mipi_dsi: mipi@ff960000 {
1785 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1786 reg = <0x0 0xff960000 0x0 0x8000>;
1787 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1788 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1789 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1790 clock-names = "ref", "pclk", "phy_cfg", "grf";
1791 power-domains = <&power RK3399_PD_VIO>;
1792 resets = <&cru SRST_P_MIPI_DSI0>;
1793 reset-names = "apb";
1794 rockchip,grf = <&grf>;
1795 #address-cells = <1>;
1797 status = "disabled";
1800 #address-cells = <1>;
1805 #address-cells = <1>;
1808 mipi_in_vopb: endpoint@0 {
1810 remote-endpoint = <&vopb_out_mipi>;
1812 mipi_in_vopl: endpoint@1 {
1814 remote-endpoint = <&vopl_out_mipi>;
1820 mipi_dsi1: mipi@ff968000 {
1821 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1822 reg = <0x0 0xff968000 0x0 0x8000>;
1823 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1824 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1825 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1826 clock-names = "ref", "pclk", "phy_cfg", "grf";
1827 power-domains = <&power RK3399_PD_VIO>;
1828 resets = <&cru SRST_P_MIPI_DSI1>;
1829 reset-names = "apb";
1830 rockchip,grf = <&grf>;
1831 #address-cells = <1>;
1833 status = "disabled";
1836 #address-cells = <1>;
1841 #address-cells = <1>;
1844 mipi1_in_vopb: endpoint@0 {
1846 remote-endpoint = <&vopb_out_mipi1>;
1849 mipi1_in_vopl: endpoint@1 {
1851 remote-endpoint = <&vopl_out_mipi1>;
1858 compatible = "rockchip,rk3399-edp";
1859 reg = <0x0 0xff970000 0x0 0x8000>;
1860 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1861 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1862 clock-names = "dp", "pclk", "grf";
1863 pinctrl-names = "default";
1864 pinctrl-0 = <&edp_hpd>;
1865 power-domains = <&power RK3399_PD_EDP>;
1866 resets = <&cru SRST_P_EDP_CTRL>;
1868 rockchip,grf = <&grf>;
1869 status = "disabled";
1872 #address-cells = <1>;
1876 #address-cells = <1>;
1879 edp_in_vopb: endpoint@0 {
1881 remote-endpoint = <&vopb_out_edp>;
1884 edp_in_vopl: endpoint@1 {
1886 remote-endpoint = <&vopl_out_edp>;
1893 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1894 reg = <0x0 0xff9a0000 0x0 0x10000>;
1895 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1896 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1897 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1898 interrupt-names = "job", "mmu", "gpu";
1899 clocks = <&cru ACLK_GPU>;
1900 power-domains = <&power RK3399_PD_GPU>;
1901 status = "disabled";
1905 compatible = "rockchip,rk3399-pinctrl";
1906 rockchip,grf = <&grf>;
1907 rockchip,pmu = <&pmugrf>;
1908 #address-cells = <2>;
1912 gpio0: gpio0@ff720000 {
1913 compatible = "rockchip,gpio-bank";
1914 reg = <0x0 0xff720000 0x0 0x100>;
1915 clocks = <&pmucru PCLK_GPIO0_PMU>;
1916 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1919 #gpio-cells = <0x2>;
1921 interrupt-controller;
1922 #interrupt-cells = <0x2>;
1925 gpio1: gpio1@ff730000 {
1926 compatible = "rockchip,gpio-bank";
1927 reg = <0x0 0xff730000 0x0 0x100>;
1928 clocks = <&pmucru PCLK_GPIO1_PMU>;
1929 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1932 #gpio-cells = <0x2>;
1934 interrupt-controller;
1935 #interrupt-cells = <0x2>;
1938 gpio2: gpio2@ff780000 {
1939 compatible = "rockchip,gpio-bank";
1940 reg = <0x0 0xff780000 0x0 0x100>;
1941 clocks = <&cru PCLK_GPIO2>;
1942 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1945 #gpio-cells = <0x2>;
1947 interrupt-controller;
1948 #interrupt-cells = <0x2>;
1951 gpio3: gpio3@ff788000 {
1952 compatible = "rockchip,gpio-bank";
1953 reg = <0x0 0xff788000 0x0 0x100>;
1954 clocks = <&cru PCLK_GPIO3>;
1955 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1958 #gpio-cells = <0x2>;
1960 interrupt-controller;
1961 #interrupt-cells = <0x2>;
1964 gpio4: gpio4@ff790000 {
1965 compatible = "rockchip,gpio-bank";
1966 reg = <0x0 0xff790000 0x0 0x100>;
1967 clocks = <&cru PCLK_GPIO4>;
1968 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1971 #gpio-cells = <0x2>;
1973 interrupt-controller;
1974 #interrupt-cells = <0x2>;
1977 pcfg_pull_up: pcfg-pull-up {
1981 pcfg_pull_down: pcfg-pull-down {
1985 pcfg_pull_none: pcfg-pull-none {
1989 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1991 drive-strength = <12>;
1994 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1996 drive-strength = <13>;
1999 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2001 drive-strength = <18>;
2004 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2006 drive-strength = <20>;
2009 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2011 drive-strength = <2>;
2014 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2016 drive-strength = <8>;
2019 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2021 drive-strength = <18>;
2024 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2026 drive-strength = <20>;
2029 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2031 drive-strength = <4>;
2034 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2036 drive-strength = <8>;
2039 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2041 drive-strength = <12>;
2044 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2046 drive-strength = <18>;
2049 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2051 drive-strength = <20>;
2054 pcfg_output_high: pcfg-output-high {
2058 pcfg_output_low: pcfg-output-low {
2064 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2071 <4 RK_PC7 2 &pcfg_pull_none>;
2076 rgmii_pins: rgmii-pins {
2079 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2081 <3 RK_PB6 1 &pcfg_pull_none>,
2083 <3 RK_PB5 1 &pcfg_pull_none>,
2085 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2087 <3 RK_PB3 1 &pcfg_pull_none>,
2089 <3 RK_PB1 1 &pcfg_pull_none>,
2091 <3 RK_PB0 1 &pcfg_pull_none>,
2093 <3 RK_PA7 1 &pcfg_pull_none>,
2095 <3 RK_PA6 1 &pcfg_pull_none>,
2097 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2099 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2101 <3 RK_PA3 1 &pcfg_pull_none>,
2103 <3 RK_PA2 1 &pcfg_pull_none>,
2105 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2107 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2110 rmii_pins: rmii-pins {
2113 <3 RK_PB5 1 &pcfg_pull_none>,
2115 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2117 <3 RK_PB3 1 &pcfg_pull_none>,
2119 <3 RK_PB2 1 &pcfg_pull_none>,
2121 <3 RK_PB1 1 &pcfg_pull_none>,
2123 <3 RK_PB0 1 &pcfg_pull_none>,
2125 <3 RK_PA7 1 &pcfg_pull_none>,
2127 <3 RK_PA6 1 &pcfg_pull_none>,
2129 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2131 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2136 i2c0_xfer: i2c0-xfer {
2138 <1 RK_PB7 2 &pcfg_pull_none>,
2139 <1 RK_PC0 2 &pcfg_pull_none>;
2144 i2c1_xfer: i2c1-xfer {
2146 <4 RK_PA2 1 &pcfg_pull_none>,
2147 <4 RK_PA1 1 &pcfg_pull_none>;
2152 i2c2_xfer: i2c2-xfer {
2154 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2155 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2160 i2c3_xfer: i2c3-xfer {
2162 <4 RK_PC1 1 &pcfg_pull_none>,
2163 <4 RK_PC0 1 &pcfg_pull_none>;
2168 i2c4_xfer: i2c4-xfer {
2170 <1 RK_PB4 1 &pcfg_pull_none>,
2171 <1 RK_PB3 1 &pcfg_pull_none>;
2176 i2c5_xfer: i2c5-xfer {
2178 <3 RK_PB3 2 &pcfg_pull_none>,
2179 <3 RK_PB2 2 &pcfg_pull_none>;
2184 i2c6_xfer: i2c6-xfer {
2186 <2 RK_PB2 2 &pcfg_pull_none>,
2187 <2 RK_PB1 2 &pcfg_pull_none>;
2192 i2c7_xfer: i2c7-xfer {
2194 <2 RK_PB0 2 &pcfg_pull_none>,
2195 <2 RK_PA7 2 &pcfg_pull_none>;
2200 i2c8_xfer: i2c8-xfer {
2202 <1 RK_PC5 1 &pcfg_pull_none>,
2203 <1 RK_PC4 1 &pcfg_pull_none>;
2208 i2s0_2ch_bus: i2s0-2ch-bus {
2210 <3 RK_PD0 1 &pcfg_pull_none>,
2211 <3 RK_PD1 1 &pcfg_pull_none>,
2212 <3 RK_PD2 1 &pcfg_pull_none>,
2213 <3 RK_PD3 1 &pcfg_pull_none>,
2214 <3 RK_PD7 1 &pcfg_pull_none>,
2215 <4 RK_PA0 1 &pcfg_pull_none>;
2218 i2s0_8ch_bus: i2s0-8ch-bus {
2220 <3 RK_PD0 1 &pcfg_pull_none>,
2221 <3 RK_PD1 1 &pcfg_pull_none>,
2222 <3 RK_PD2 1 &pcfg_pull_none>,
2223 <3 RK_PD3 1 &pcfg_pull_none>,
2224 <3 RK_PD4 1 &pcfg_pull_none>,
2225 <3 RK_PD5 1 &pcfg_pull_none>,
2226 <3 RK_PD6 1 &pcfg_pull_none>,
2227 <3 RK_PD7 1 &pcfg_pull_none>,
2228 <4 RK_PA0 1 &pcfg_pull_none>;
2233 i2s1_2ch_bus: i2s1-2ch-bus {
2235 <4 RK_PA3 1 &pcfg_pull_none>,
2236 <4 RK_PA4 1 &pcfg_pull_none>,
2237 <4 RK_PA5 1 &pcfg_pull_none>,
2238 <4 RK_PA6 1 &pcfg_pull_none>,
2239 <4 RK_PA7 1 &pcfg_pull_none>;
2244 sdio0_bus1: sdio0-bus1 {
2246 <2 RK_PC4 1 &pcfg_pull_up>;
2249 sdio0_bus4: sdio0-bus4 {
2251 <2 RK_PC4 1 &pcfg_pull_up>,
2252 <2 RK_PC5 1 &pcfg_pull_up>,
2253 <2 RK_PC6 1 &pcfg_pull_up>,
2254 <2 RK_PC7 1 &pcfg_pull_up>;
2257 sdio0_cmd: sdio0-cmd {
2259 <2 RK_PD0 1 &pcfg_pull_up>;
2262 sdio0_clk: sdio0-clk {
2264 <2 RK_PD1 1 &pcfg_pull_none>;
2267 sdio0_cd: sdio0-cd {
2269 <2 RK_PD2 1 &pcfg_pull_up>;
2272 sdio0_pwr: sdio0-pwr {
2274 <2 RK_PD3 1 &pcfg_pull_up>;
2277 sdio0_bkpwr: sdio0-bkpwr {
2279 <2 RK_PD4 1 &pcfg_pull_up>;
2282 sdio0_wp: sdio0-wp {
2284 <0 RK_PA3 1 &pcfg_pull_up>;
2287 sdio0_int: sdio0-int {
2289 <0 RK_PA4 1 &pcfg_pull_up>;
2294 sdmmc_bus1: sdmmc-bus1 {
2296 <4 RK_PB0 1 &pcfg_pull_up>;
2299 sdmmc_bus4: sdmmc-bus4 {
2301 <4 RK_PB0 1 &pcfg_pull_up>,
2302 <4 RK_PB1 1 &pcfg_pull_up>,
2303 <4 RK_PB2 1 &pcfg_pull_up>,
2304 <4 RK_PB3 1 &pcfg_pull_up>;
2307 sdmmc_clk: sdmmc-clk {
2309 <4 RK_PB4 1 &pcfg_pull_none>;
2312 sdmmc_cmd: sdmmc-cmd {
2314 <4 RK_PB5 1 &pcfg_pull_up>;
2317 sdmmc_cd: sdmmc-cd {
2319 <0 RK_PA7 1 &pcfg_pull_up>;
2322 sdmmc_wp: sdmmc-wp {
2324 <0 RK_PB0 1 &pcfg_pull_up>;
2329 ap_pwroff: ap-pwroff {
2330 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2333 ddrio_pwroff: ddrio-pwroff {
2334 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2339 spdif_bus: spdif-bus {
2341 <4 RK_PC5 1 &pcfg_pull_none>;
2344 spdif_bus_1: spdif-bus-1 {
2346 <3 RK_PC0 3 &pcfg_pull_none>;
2351 spi0_clk: spi0-clk {
2353 <3 RK_PA6 2 &pcfg_pull_up>;
2355 spi0_cs0: spi0-cs0 {
2357 <3 RK_PA7 2 &pcfg_pull_up>;
2359 spi0_cs1: spi0-cs1 {
2361 <3 RK_PB0 2 &pcfg_pull_up>;
2365 <3 RK_PA5 2 &pcfg_pull_up>;
2369 <3 RK_PA4 2 &pcfg_pull_up>;
2374 spi1_clk: spi1-clk {
2376 <1 RK_PB1 2 &pcfg_pull_up>;
2378 spi1_cs0: spi1-cs0 {
2380 <1 RK_PB2 2 &pcfg_pull_up>;
2384 <1 RK_PA7 2 &pcfg_pull_up>;
2388 <1 RK_PB0 2 &pcfg_pull_up>;
2393 spi2_clk: spi2-clk {
2395 <2 RK_PB3 1 &pcfg_pull_up>;
2397 spi2_cs0: spi2-cs0 {
2399 <2 RK_PB4 1 &pcfg_pull_up>;
2403 <2 RK_PB1 1 &pcfg_pull_up>;
2407 <2 RK_PB2 1 &pcfg_pull_up>;
2412 spi3_clk: spi3-clk {
2414 <1 RK_PC1 1 &pcfg_pull_up>;
2416 spi3_cs0: spi3-cs0 {
2418 <1 RK_PC2 1 &pcfg_pull_up>;
2422 <1 RK_PB7 1 &pcfg_pull_up>;
2426 <1 RK_PC0 1 &pcfg_pull_up>;
2431 spi4_clk: spi4-clk {
2433 <3 RK_PA2 2 &pcfg_pull_up>;
2435 spi4_cs0: spi4-cs0 {
2437 <3 RK_PA3 2 &pcfg_pull_up>;
2441 <3 RK_PA0 2 &pcfg_pull_up>;
2445 <3 RK_PA1 2 &pcfg_pull_up>;
2450 spi5_clk: spi5-clk {
2452 <2 RK_PC6 2 &pcfg_pull_up>;
2454 spi5_cs0: spi5-cs0 {
2456 <2 RK_PC7 2 &pcfg_pull_up>;
2460 <2 RK_PC4 2 &pcfg_pull_up>;
2464 <2 RK_PC5 2 &pcfg_pull_up>;
2469 test_clkout0: test-clkout0 {
2471 <0 RK_PA0 1 &pcfg_pull_none>;
2474 test_clkout1: test-clkout1 {
2476 <2 RK_PD1 2 &pcfg_pull_none>;
2479 test_clkout2: test-clkout2 {
2481 <0 RK_PB0 3 &pcfg_pull_none>;
2486 otp_gpio: otp-gpio {
2487 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2491 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2496 uart0_xfer: uart0-xfer {
2498 <2 RK_PC0 1 &pcfg_pull_up>,
2499 <2 RK_PC1 1 &pcfg_pull_none>;
2502 uart0_cts: uart0-cts {
2504 <2 RK_PC2 1 &pcfg_pull_none>;
2507 uart0_rts: uart0-rts {
2509 <2 RK_PC3 1 &pcfg_pull_none>;
2514 uart1_xfer: uart1-xfer {
2516 <3 RK_PB4 2 &pcfg_pull_up>,
2517 <3 RK_PB5 2 &pcfg_pull_none>;
2522 uart2a_xfer: uart2a-xfer {
2524 <4 RK_PB0 2 &pcfg_pull_up>,
2525 <4 RK_PB1 2 &pcfg_pull_none>;
2530 uart2b_xfer: uart2b-xfer {
2532 <4 RK_PC0 2 &pcfg_pull_up>,
2533 <4 RK_PC1 2 &pcfg_pull_none>;
2538 uart2c_xfer: uart2c-xfer {
2540 <4 RK_PC3 1 &pcfg_pull_up>,
2541 <4 RK_PC4 1 &pcfg_pull_none>;
2546 uart3_xfer: uart3-xfer {
2548 <3 RK_PB6 2 &pcfg_pull_up>,
2549 <3 RK_PB7 2 &pcfg_pull_none>;
2552 uart3_cts: uart3-cts {
2554 <3 RK_PC0 2 &pcfg_pull_none>;
2557 uart3_rts: uart3-rts {
2559 <3 RK_PC1 2 &pcfg_pull_none>;
2564 uart4_xfer: uart4-xfer {
2566 <1 RK_PA7 1 &pcfg_pull_up>,
2567 <1 RK_PB0 1 &pcfg_pull_none>;
2572 uarthdcp_xfer: uarthdcp-xfer {
2574 <4 RK_PC5 2 &pcfg_pull_up>,
2575 <4 RK_PC6 2 &pcfg_pull_none>;
2580 pwm0_pin: pwm0-pin {
2582 <4 RK_PC2 1 &pcfg_pull_none>;
2585 pwm0_pin_pull_down: pwm0-pin-pull-down {
2587 <4 RK_PC2 1 &pcfg_pull_down>;
2590 vop0_pwm_pin: vop0-pwm-pin {
2592 <4 RK_PC2 2 &pcfg_pull_none>;
2595 vop1_pwm_pin: vop1-pwm-pin {
2597 <4 RK_PC2 3 &pcfg_pull_none>;
2602 pwm1_pin: pwm1-pin {
2604 <4 RK_PC6 1 &pcfg_pull_none>;
2607 pwm1_pin_pull_down: pwm1-pin-pull-down {
2609 <4 RK_PC6 1 &pcfg_pull_down>;
2614 pwm2_pin: pwm2-pin {
2616 <1 RK_PC3 1 &pcfg_pull_none>;
2619 pwm2_pin_pull_down: pwm2-pin-pull-down {
2621 <1 RK_PC3 1 &pcfg_pull_down>;
2626 pwm3a_pin: pwm3a-pin {
2628 <0 RK_PA6 1 &pcfg_pull_none>;
2633 pwm3b_pin: pwm3b-pin {
2635 <1 RK_PB6 1 &pcfg_pull_none>;
2640 hdmi_i2c_xfer: hdmi-i2c-xfer {
2642 <4 RK_PC1 3 &pcfg_pull_none>,
2643 <4 RK_PC0 3 &pcfg_pull_none>;
2646 hdmi_cec: hdmi-cec {
2648 <4 RK_PC7 1 &pcfg_pull_none>;
2653 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2655 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2658 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2660 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;