2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
54 interrupt-parent = <&gic>;
110 compatible = "arm,cortex-a53", "arm,armv8";
112 enable-method = "psci";
113 #cooling-cells = <2>; /* min followed by max */
114 clocks = <&cru ARMCLKL>;
119 compatible = "arm,cortex-a53", "arm,armv8";
121 enable-method = "psci";
122 clocks = <&cru ARMCLKL>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
135 compatible = "arm,cortex-a53", "arm,armv8";
137 enable-method = "psci";
138 clocks = <&cru ARMCLKL>;
143 compatible = "arm,cortex-a72", "arm,armv8";
145 enable-method = "psci";
146 #cooling-cells = <2>; /* min followed by max */
147 clocks = <&cru ARMCLKB>;
152 compatible = "arm,cortex-a72", "arm,armv8";
154 enable-method = "psci";
155 clocks = <&cru ARMCLKB>;
160 compatible = "arm,cortex-a53-pmu";
161 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
165 compatible = "arm,cortex-a72-pmu";
166 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
170 compatible = "arm,psci-1.0";
175 compatible = "arm,armv8-timer";
176 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
177 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
178 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
179 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
183 compatible = "fixed-clock";
184 clock-frequency = <24000000>;
185 clock-output-names = "xin24m";
190 compatible = "simple-bus";
191 #address-cells = <2>;
195 dmac_bus: dma-controller@ff6d0000 {
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0x0 0xff6d0000 0x0 0x4000>;
198 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
199 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
201 clocks = <&cru ACLK_DMAC0_PERILP>;
202 clock-names = "apb_pclk";
205 dmac_peri: dma-controller@ff6e0000 {
206 compatible = "arm,pl330", "arm,primecell";
207 reg = <0x0 0xff6e0000 0x0 0x4000>;
208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
209 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
211 clocks = <&cru ACLK_DMAC1_PERILP>;
212 clock-names = "apb_pclk";
216 gmac: ethernet@fe300000 {
217 compatible = "rockchip,rk3399-gmac";
218 reg = <0x0 0xfe300000 0x0 0x10000>;
219 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
220 interrupt-names = "macirq";
221 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
222 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
223 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
225 clock-names = "stmmaceth", "mac_clk_rx",
226 "mac_clk_tx", "clk_mac_ref",
227 "clk_mac_refout", "aclk_mac",
229 power-domains = <&power RK3399_PD_GMAC>;
230 resets = <&cru SRST_A_GMAC>;
231 reset-names = "stmmaceth";
232 rockchip,grf = <&grf>;
236 sdio0: dwmmc@fe310000 {
237 compatible = "rockchip,rk3399-dw-mshc",
238 "rockchip,rk3288-dw-mshc";
239 reg = <0x0 0xfe310000 0x0 0x4000>;
240 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
241 clock-freq-min-max = <400000 150000000>;
242 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
243 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
244 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
245 fifo-depth = <0x100>;
249 sdmmc: dwmmc@fe320000 {
250 compatible = "rockchip,rk3399-dw-mshc",
251 "rockchip,rk3288-dw-mshc";
252 reg = <0x0 0xfe320000 0x0 0x4000>;
253 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
254 clock-freq-min-max = <400000 150000000>;
255 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
256 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
257 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
258 fifo-depth = <0x100>;
262 sdhci: sdhci@fe330000 {
263 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
264 reg = <0x0 0xfe330000 0x0 0x10000>;
265 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
266 arasan,soc-ctl-syscon = <&grf>;
267 assigned-clocks = <&cru SCLK_EMMC>;
268 assigned-clock-rates = <200000000>;
269 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
270 clock-names = "clk_xin", "clk_ahb";
271 clock-output-names = "emmc_cardclock";
274 phy-names = "phy_arasan";
278 pcie0: pcie@f8000000 {
279 compatible = "rockchip,rk3399-pcie";
280 reg = <0x0 0xf8000000 0x0 0x2000000>,
281 <0x0 0xfd000000 0x0 0x1000000>;
282 reg-names = "axi-base", "apb-base";
283 #address-cells = <3>;
285 #interrupt-cells = <1>;
286 bus-range = <0x0 0x1>;
287 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
288 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
289 clock-names = "aclk", "aclk-perf",
291 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
292 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
293 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
294 interrupt-names = "sys", "legacy", "client";
295 interrupt-map-mask = <0 0 0 7>;
296 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
297 <0 0 0 2 &pcie0_intc 1>,
298 <0 0 0 3 &pcie0_intc 2>,
299 <0 0 0 4 &pcie0_intc 3>;
300 msi-map = <0x0 &its 0x0 0x1000>;
302 phy-names = "pcie-phy";
303 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
304 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
305 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
306 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
307 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
309 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
310 "pm", "pclk", "aclk";
313 pcie0_intc: interrupt-controller {
314 interrupt-controller;
315 #address-cells = <0>;
316 #interrupt-cells = <1>;
320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
325 clock-names = "hclk_host0", "hclk_host0_arb";
326 phys = <&u2phy0_host>;
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
336 clock-names = "hclk_host0", "hclk_host0_arb";
340 usb_host1_ehci: usb@fe3c0000 {
341 compatible = "generic-ehci";
342 reg = <0x0 0xfe3c0000 0x0 0x20000>;
343 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
344 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
345 clock-names = "hclk_host1", "hclk_host1_arb";
346 phys = <&u2phy1_host>;
351 usb_host1_ohci: usb@fe3e0000 {
352 compatible = "generic-ohci";
353 reg = <0x0 0xfe3e0000 0x0 0x20000>;
354 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
355 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
356 clock-names = "hclk_host1", "hclk_host1_arb";
360 gic: interrupt-controller@fee00000 {
361 compatible = "arm,gic-v3";
362 #interrupt-cells = <4>;
363 #address-cells = <2>;
366 interrupt-controller;
368 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
369 <0x0 0xfef00000 0 0xc0000>, /* GICR */
370 <0x0 0xfff00000 0 0x10000>, /* GICC */
371 <0x0 0xfff10000 0 0x10000>, /* GICH */
372 <0x0 0xfff20000 0 0x10000>; /* GICV */
373 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
374 its: interrupt-controller@fee20000 {
375 compatible = "arm,gic-v3-its";
377 reg = <0x0 0xfee20000 0x0 0x20000>;
381 ppi_cluster0: interrupt-partition-0 {
382 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
385 ppi_cluster1: interrupt-partition-1 {
386 affinity = <&cpu_b0 &cpu_b1>;
391 saradc: saradc@ff100000 {
392 compatible = "rockchip,rk3399-saradc";
393 reg = <0x0 0xff100000 0x0 0x100>;
394 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
395 #io-channel-cells = <1>;
396 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
397 clock-names = "saradc", "apb_pclk";
398 resets = <&cru SRST_P_SARADC>;
399 reset-names = "saradc-apb";
404 compatible = "rockchip,rk3399-i2c";
405 reg = <0x0 0xff110000 0x0 0x1000>;
406 assigned-clocks = <&cru SCLK_I2C1>;
407 assigned-clock-rates = <200000000>;
408 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
409 clock-names = "i2c", "pclk";
410 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c1_xfer>;
413 #address-cells = <1>;
419 compatible = "rockchip,rk3399-i2c";
420 reg = <0x0 0xff120000 0x0 0x1000>;
421 assigned-clocks = <&cru SCLK_I2C2>;
422 assigned-clock-rates = <200000000>;
423 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
424 clock-names = "i2c", "pclk";
425 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c2_xfer>;
428 #address-cells = <1>;
434 compatible = "rockchip,rk3399-i2c";
435 reg = <0x0 0xff130000 0x0 0x1000>;
436 assigned-clocks = <&cru SCLK_I2C3>;
437 assigned-clock-rates = <200000000>;
438 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
439 clock-names = "i2c", "pclk";
440 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&i2c3_xfer>;
443 #address-cells = <1>;
449 compatible = "rockchip,rk3399-i2c";
450 reg = <0x0 0xff140000 0x0 0x1000>;
451 assigned-clocks = <&cru SCLK_I2C5>;
452 assigned-clock-rates = <200000000>;
453 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
454 clock-names = "i2c", "pclk";
455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&i2c5_xfer>;
458 #address-cells = <1>;
464 compatible = "rockchip,rk3399-i2c";
465 reg = <0x0 0xff150000 0x0 0x1000>;
466 assigned-clocks = <&cru SCLK_I2C6>;
467 assigned-clock-rates = <200000000>;
468 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
469 clock-names = "i2c", "pclk";
470 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c6_xfer>;
473 #address-cells = <1>;
479 compatible = "rockchip,rk3399-i2c";
480 reg = <0x0 0xff160000 0x0 0x1000>;
481 assigned-clocks = <&cru SCLK_I2C7>;
482 assigned-clock-rates = <200000000>;
483 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
484 clock-names = "i2c", "pclk";
485 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c7_xfer>;
488 #address-cells = <1>;
493 uart0: serial@ff180000 {
494 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
495 reg = <0x0 0xff180000 0x0 0x100>;
496 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
497 clock-names = "baudclk", "apb_pclk";
498 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&uart0_xfer>;
506 uart1: serial@ff190000 {
507 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
508 reg = <0x0 0xff190000 0x0 0x100>;
509 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
510 clock-names = "baudclk", "apb_pclk";
511 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&uart1_xfer>;
519 uart2: serial@ff1a0000 {
520 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
521 reg = <0x0 0xff1a0000 0x0 0x100>;
522 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
523 clock-names = "baudclk", "apb_pclk";
524 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&uart2c_xfer>;
532 uart3: serial@ff1b0000 {
533 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
534 reg = <0x0 0xff1b0000 0x0 0x100>;
535 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
536 clock-names = "baudclk", "apb_pclk";
537 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart3_xfer>;
546 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
547 reg = <0x0 0xff1c0000 0x0 0x1000>;
548 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
549 clock-names = "spiclk", "apb_pclk";
550 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
553 #address-cells = <1>;
559 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
560 reg = <0x0 0xff1d0000 0x0 0x1000>;
561 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
562 clock-names = "spiclk", "apb_pclk";
563 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
566 #address-cells = <1>;
572 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
573 reg = <0x0 0xff1e0000 0x0 0x1000>;
574 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
575 clock-names = "spiclk", "apb_pclk";
576 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
579 #address-cells = <1>;
585 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
586 reg = <0x0 0xff1f0000 0x0 0x1000>;
587 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
588 clock-names = "spiclk", "apb_pclk";
589 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
592 #address-cells = <1>;
598 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
599 reg = <0x0 0xff200000 0x0 0x1000>;
600 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
601 clock-names = "spiclk", "apb_pclk";
602 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
605 #address-cells = <1>;
612 polling-delay-passive = <100>;
613 polling-delay = <1000>;
615 thermal-sensors = <&tsadc 0>;
618 cpu_alert0: cpu_alert0 {
619 temperature = <70000>;
623 cpu_alert1: cpu_alert1 {
624 temperature = <75000>;
629 temperature = <95000>;
637 trip = <&cpu_alert0>;
639 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
642 trip = <&cpu_alert1>;
644 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
645 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
651 polling-delay-passive = <100>;
652 polling-delay = <1000>;
654 thermal-sensors = <&tsadc 1>;
657 gpu_alert0: gpu_alert0 {
658 temperature = <75000>;
663 temperature = <95000>;
671 trip = <&gpu_alert0>;
673 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
679 tsadc: tsadc@ff260000 {
680 compatible = "rockchip,rk3399-tsadc";
681 reg = <0x0 0xff260000 0x0 0x100>;
682 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
683 assigned-clocks = <&cru SCLK_TSADC>;
684 assigned-clock-rates = <750000>;
685 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
686 clock-names = "tsadc", "apb_pclk";
687 resets = <&cru SRST_TSADC>;
688 reset-names = "tsadc-apb";
689 rockchip,grf = <&grf>;
690 rockchip,hw-tshut-temp = <95000>;
691 pinctrl-names = "init", "default", "sleep";
692 pinctrl-0 = <&otp_gpio>;
693 pinctrl-1 = <&otp_out>;
694 pinctrl-2 = <&otp_gpio>;
695 #thermal-sensor-cells = <1>;
699 qos_gmac: qos@ffa5c000 {
700 compatible = "syscon";
701 reg = <0x0 0xffa5c000 0x0 0x20>;
704 qos_hdcp: qos@ffa90000 {
705 compatible = "syscon";
706 reg = <0x0 0xffa90000 0x0 0x20>;
709 qos_iep: qos@ffa98000 {
710 compatible = "syscon";
711 reg = <0x0 0xffa98000 0x0 0x20>;
714 qos_isp0_m0: qos@ffaa0000 {
715 compatible = "syscon";
716 reg = <0x0 0xffaa0000 0x0 0x20>;
719 qos_isp0_m1: qos@ffaa0080 {
720 compatible = "syscon";
721 reg = <0x0 0xffaa0080 0x0 0x20>;
724 qos_isp1_m0: qos@ffaa8000 {
725 compatible = "syscon";
726 reg = <0x0 0xffaa8000 0x0 0x20>;
729 qos_isp1_m1: qos@ffaa8080 {
730 compatible = "syscon";
731 reg = <0x0 0xffaa8080 0x0 0x20>;
734 qos_rga_r: qos@ffab0000 {
735 compatible = "syscon";
736 reg = <0x0 0xffab0000 0x0 0x20>;
739 qos_rga_w: qos@ffab0080 {
740 compatible = "syscon";
741 reg = <0x0 0xffab0080 0x0 0x20>;
744 qos_video_m0: qos@ffab8000 {
745 compatible = "syscon";
746 reg = <0x0 0xffab8000 0x0 0x20>;
749 qos_video_m1_r: qos@ffac0000 {
750 compatible = "syscon";
751 reg = <0x0 0xffac0000 0x0 0x20>;
754 qos_video_m1_w: qos@ffac0080 {
755 compatible = "syscon";
756 reg = <0x0 0xffac0080 0x0 0x20>;
759 qos_vop_big_r: qos@ffac8000 {
760 compatible = "syscon";
761 reg = <0x0 0xffac8000 0x0 0x20>;
764 qos_vop_big_w: qos@ffac8080 {
765 compatible = "syscon";
766 reg = <0x0 0xffac8080 0x0 0x20>;
769 qos_vop_little: qos@ffad0000 {
770 compatible = "syscon";
771 reg = <0x0 0xffad0000 0x0 0x20>;
774 qos_gpu: qos@ffae0000 {
775 compatible = "syscon";
776 reg = <0x0 0xffae0000 0x0 0x20>;
779 pmu: power-management@ff310000 {
780 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
781 reg = <0x0 0xff310000 0x0 0x1000>;
784 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
785 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
786 * Some of the power domains are grouped together for every
788 * The detail contents as below.
790 power: power-controller {
791 compatible = "rockchip,rk3399-power-controller";
792 #power-domain-cells = <1>;
793 #address-cells = <1>;
796 /* These power domains are grouped by VD_CENTER */
797 pd_iep@RK3399_PD_IEP {
798 reg = <RK3399_PD_IEP>;
799 clocks = <&cru ACLK_IEP>,
803 pd_rga@RK3399_PD_RGA {
804 reg = <RK3399_PD_RGA>;
805 clocks = <&cru ACLK_RGA>,
807 pm_qos = <&qos_rga_r>,
810 pd_vcodec@RK3399_PD_VCODEC {
811 reg = <RK3399_PD_VCODEC>;
812 clocks = <&cru ACLK_VCODEC>,
814 pm_qos = <&qos_video_m0>;
816 pd_vdu@RK3399_PD_VDU {
817 reg = <RK3399_PD_VDU>;
818 clocks = <&cru ACLK_VDU>,
820 pm_qos = <&qos_video_m1_r>,
824 /* These power domains are grouped by VD_GPU */
825 pd_gpu@RK3399_PD_GPU {
826 reg = <RK3399_PD_GPU>;
827 clocks = <&cru ACLK_GPU>;
831 /* These power domains are grouped by VD_LOGIC */
832 pd_gmac@RK3399_PD_GMAC {
833 reg = <RK3399_PD_GMAC>;
834 clocks = <&cru ACLK_GMAC>;
835 pm_qos = <&qos_gmac>;
837 pd_vio@RK3399_PD_VIO {
838 reg = <RK3399_PD_VIO>;
839 #address-cells = <1>;
842 pd_hdcp@RK3399_PD_HDCP {
843 reg = <RK3399_PD_HDCP>;
844 clocks = <&cru ACLK_HDCP>,
847 pm_qos = <&qos_hdcp>;
849 pd_isp0@RK3399_PD_ISP0 {
850 reg = <RK3399_PD_ISP0>;
851 clocks = <&cru ACLK_ISP0>,
853 pm_qos = <&qos_isp0_m0>,
856 pd_isp1@RK3399_PD_ISP1 {
857 reg = <RK3399_PD_ISP1>;
858 clocks = <&cru ACLK_ISP1>,
860 pm_qos = <&qos_isp1_m0>,
863 pd_tcpc0@RK3399_PD_TCPC0 {
864 reg = <RK3399_PD_TCPD0>;
865 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
866 <&cru SCLK_UPHY0_TCPDPHY_REF>;
868 pd_tcpc1@RK3399_PD_TCPC1 {
869 reg = <RK3399_PD_TCPD1>;
870 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
871 <&cru SCLK_UPHY1_TCPDPHY_REF>;
874 reg = <RK3399_PD_VO>;
875 #address-cells = <1>;
878 pd_vopb@RK3399_PD_VOPB {
879 reg = <RK3399_PD_VOPB>;
880 clocks = <&cru ACLK_VOP0>,
882 pm_qos = <&qos_vop_big_r>,
885 pd_vopl@RK3399_PD_VOPL {
886 reg = <RK3399_PD_VOPL>;
887 clocks = <&cru ACLK_VOP1>,
889 pm_qos = <&qos_vop_little>;
896 pmugrf: syscon@ff320000 {
897 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
898 reg = <0x0 0xff320000 0x0 0x1000>;
899 #address-cells = <1>;
902 pmu_io_domains: io-domains {
903 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
909 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
910 reg = <0x0 0xff350000 0x0 0x1000>;
911 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
912 clock-names = "spiclk", "apb_pclk";
913 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
916 #address-cells = <1>;
921 uart4: serial@ff370000 {
922 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
923 reg = <0x0 0xff370000 0x0 0x100>;
924 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
925 clock-names = "baudclk", "apb_pclk";
926 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
929 pinctrl-names = "default";
930 pinctrl-0 = <&uart4_xfer>;
935 compatible = "rockchip,rk3399-i2c";
936 reg = <0x0 0xff3c0000 0x0 0x1000>;
937 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
938 assigned-clock-rates = <200000000>;
939 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
940 clock-names = "i2c", "pclk";
941 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
942 pinctrl-names = "default";
943 pinctrl-0 = <&i2c0_xfer>;
944 #address-cells = <1>;
950 compatible = "rockchip,rk3399-i2c";
951 reg = <0x0 0xff3d0000 0x0 0x1000>;
952 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
953 assigned-clock-rates = <200000000>;
954 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
955 clock-names = "i2c", "pclk";
956 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
957 pinctrl-names = "default";
958 pinctrl-0 = <&i2c4_xfer>;
959 #address-cells = <1>;
965 compatible = "rockchip,rk3399-i2c";
966 reg = <0x0 0xff3e0000 0x0 0x1000>;
967 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
968 assigned-clock-rates = <200000000>;
969 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
970 clock-names = "i2c", "pclk";
971 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
972 pinctrl-names = "default";
973 pinctrl-0 = <&i2c8_xfer>;
974 #address-cells = <1>;
980 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
981 reg = <0x0 0xff420000 0x0 0x10>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&pwm0_pin>;
985 clocks = <&pmucru PCLK_RKPWM_PMU>;
991 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
992 reg = <0x0 0xff420010 0x0 0x10>;
994 pinctrl-names = "default";
995 pinctrl-0 = <&pwm1_pin>;
996 clocks = <&pmucru PCLK_RKPWM_PMU>;
1001 pwm2: pwm@ff420020 {
1002 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1003 reg = <0x0 0xff420020 0x0 0x10>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&pwm2_pin>;
1007 clocks = <&pmucru PCLK_RKPWM_PMU>;
1008 clock-names = "pwm";
1009 status = "disabled";
1012 pwm3: pwm@ff420030 {
1013 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1014 reg = <0x0 0xff420030 0x0 0x10>;
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&pwm3a_pin>;
1018 clocks = <&pmucru PCLK_RKPWM_PMU>;
1019 clock-names = "pwm";
1020 status = "disabled";
1023 efuse0: efuse@ff690000 {
1024 compatible = "rockchip,rk3399-efuse";
1025 reg = <0x0 0xff690000 0x0 0x80>;
1026 #address-cells = <1>;
1028 clocks = <&cru PCLK_EFUSE1024NS>;
1029 clock-names = "pclk_efuse";
1032 cpub_leakage: cpu-leakage@17 {
1035 gpu_leakage: gpu-leakage@18 {
1038 center_leakage: center-leakage@19 {
1041 cpul_leakage: cpu-leakage@1a {
1044 logic_leakage: logic-leakage@1b {
1047 wafer_info: wafer-info@1c {
1052 pmucru: pmu-clock-controller@ff750000 {
1053 compatible = "rockchip,rk3399-pmucru";
1054 reg = <0x0 0xff750000 0x0 0x1000>;
1057 assigned-clocks = <&pmucru PLL_PPLL>;
1058 assigned-clock-rates = <676000000>;
1061 cru: clock-controller@ff760000 {
1062 compatible = "rockchip,rk3399-cru";
1063 reg = <0x0 0xff760000 0x0 0x1000>;
1067 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1069 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1071 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1072 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1073 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1074 assigned-clock-rates =
1075 <594000000>, <800000000>,
1077 <150000000>, <75000000>,
1079 <100000000>, <100000000>,
1080 <50000000>, <600000000>,
1081 <100000000>, <50000000>;
1084 grf: syscon@ff770000 {
1085 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1086 reg = <0x0 0xff770000 0x0 0x10000>;
1087 #address-cells = <1>;
1090 io_domains: io-domains {
1091 compatible = "rockchip,rk3399-io-voltage-domain";
1092 status = "disabled";
1095 u2phy0: usb2-phy@e450 {
1096 compatible = "rockchip,rk3399-usb2phy";
1097 reg = <0xe450 0x10>;
1098 clocks = <&cru SCLK_USB2PHY0_REF>;
1099 clock-names = "phyclk";
1101 clock-output-names = "clk_usbphy0_480m";
1102 status = "disabled";
1104 u2phy0_host: host-port {
1106 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1107 interrupt-names = "linestate";
1108 status = "disabled";
1112 u2phy1: usb2-phy@e460 {
1113 compatible = "rockchip,rk3399-usb2phy";
1114 reg = <0xe460 0x10>;
1115 clocks = <&cru SCLK_USB2PHY1_REF>;
1116 clock-names = "phyclk";
1118 clock-output-names = "clk_usbphy1_480m";
1119 status = "disabled";
1121 u2phy1_host: host-port {
1123 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1124 interrupt-names = "linestate";
1125 status = "disabled";
1129 emmc_phy: phy@f780 {
1130 compatible = "rockchip,rk3399-emmc-phy";
1131 reg = <0xf780 0x24>;
1133 clock-names = "emmcclk";
1135 status = "disabled";
1138 pcie_phy: pcie-phy {
1139 compatible = "rockchip,rk3399-pcie-phy";
1140 clocks = <&cru SCLK_PCIEPHY_REF>;
1141 clock-names = "refclk";
1143 resets = <&cru SRST_PCIEPHY>;
1144 reset-names = "phy";
1145 status = "disabled";
1149 tcphy0: phy@ff7c0000 {
1150 compatible = "rockchip,rk3399-typec-phy";
1151 reg = <0x0 0xff7c0000 0x0 0x40000>;
1152 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1153 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1154 clock-names = "tcpdcore", "tcpdphy-ref";
1155 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1156 assigned-clock-rates = <50000000>;
1157 resets = <&cru SRST_UPHY0>,
1158 <&cru SRST_UPHY0_PIPE_L00>,
1159 <&cru SRST_P_UPHY0_TCPHY>;
1160 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1161 rockchip,grf = <&grf>;
1162 rockchip,typec-conn-dir = <0xe580 0 16>;
1163 rockchip,usb3tousb2-en = <0xe580 3 19>;
1164 rockchip,external-psm = <0xe588 14 30>;
1165 rockchip,pipe-status = <0xe5c0 0 0>;
1166 status = "disabled";
1168 tcphy0_dp: dp-port {
1172 tcphy0_usb3: usb3-port {
1177 tcphy1: phy@ff800000 {
1178 compatible = "rockchip,rk3399-typec-phy";
1179 reg = <0x0 0xff800000 0x0 0x40000>;
1180 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1181 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1182 clock-names = "tcpdcore", "tcpdphy-ref";
1183 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1184 assigned-clock-rates = <50000000>;
1185 resets = <&cru SRST_UPHY1>,
1186 <&cru SRST_UPHY1_PIPE_L00>,
1187 <&cru SRST_P_UPHY1_TCPHY>;
1188 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1189 rockchip,grf = <&grf>;
1190 rockchip,typec-conn-dir = <0xe58c 0 16>;
1191 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1192 rockchip,external-psm = <0xe594 14 30>;
1193 rockchip,pipe-status = <0xe5c0 16 16>;
1194 status = "disabled";
1196 tcphy1_dp: dp-port {
1200 tcphy1_usb3: usb3-port {
1206 compatible = "snps,dw-wdt";
1207 reg = <0x0 0xff848000 0x0 0x100>;
1208 clocks = <&cru PCLK_WDT>;
1209 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1212 rktimer: rktimer@ff850000 {
1213 compatible = "rockchip,rk3399-timer";
1214 reg = <0x0 0xff850000 0x0 0x1000>;
1215 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1216 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1217 clock-names = "pclk", "timer";
1220 spdif: spdif@ff870000 {
1221 compatible = "rockchip,rk3399-spdif";
1222 reg = <0x0 0xff870000 0x0 0x1000>;
1223 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1224 dmas = <&dmac_bus 7>;
1226 clock-names = "mclk", "hclk";
1227 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1228 pinctrl-names = "default";
1229 pinctrl-0 = <&spdif_bus>;
1230 status = "disabled";
1233 i2s0: i2s@ff880000 {
1234 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1235 reg = <0x0 0xff880000 0x0 0x1000>;
1236 rockchip,grf = <&grf>;
1237 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1238 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1239 dma-names = "tx", "rx";
1240 clock-names = "i2s_clk", "i2s_hclk";
1241 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&i2s0_8ch_bus>;
1244 status = "disabled";
1247 i2s1: i2s@ff890000 {
1248 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1249 reg = <0x0 0xff890000 0x0 0x1000>;
1250 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1251 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1252 dma-names = "tx", "rx";
1253 clock-names = "i2s_clk", "i2s_hclk";
1254 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&i2s1_2ch_bus>;
1257 status = "disabled";
1260 i2s2: i2s@ff8a0000 {
1261 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1262 reg = <0x0 0xff8a0000 0x0 0x1000>;
1263 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1264 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1265 dma-names = "tx", "rx";
1266 clock-names = "i2s_clk", "i2s_hclk";
1267 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1268 status = "disabled";
1272 compatible = "rockchip,rk3399-pinctrl";
1273 rockchip,grf = <&grf>;
1274 rockchip,pmu = <&pmugrf>;
1275 #address-cells = <2>;
1279 gpio0: gpio0@ff720000 {
1280 compatible = "rockchip,gpio-bank";
1281 reg = <0x0 0xff720000 0x0 0x100>;
1282 clocks = <&pmucru PCLK_GPIO0_PMU>;
1283 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1286 #gpio-cells = <0x2>;
1288 interrupt-controller;
1289 #interrupt-cells = <0x2>;
1292 gpio1: gpio1@ff730000 {
1293 compatible = "rockchip,gpio-bank";
1294 reg = <0x0 0xff730000 0x0 0x100>;
1295 clocks = <&pmucru PCLK_GPIO1_PMU>;
1296 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1299 #gpio-cells = <0x2>;
1301 interrupt-controller;
1302 #interrupt-cells = <0x2>;
1305 gpio2: gpio2@ff780000 {
1306 compatible = "rockchip,gpio-bank";
1307 reg = <0x0 0xff780000 0x0 0x100>;
1308 clocks = <&cru PCLK_GPIO2>;
1309 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1312 #gpio-cells = <0x2>;
1314 interrupt-controller;
1315 #interrupt-cells = <0x2>;
1318 gpio3: gpio3@ff788000 {
1319 compatible = "rockchip,gpio-bank";
1320 reg = <0x0 0xff788000 0x0 0x100>;
1321 clocks = <&cru PCLK_GPIO3>;
1322 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1325 #gpio-cells = <0x2>;
1327 interrupt-controller;
1328 #interrupt-cells = <0x2>;
1331 gpio4: gpio4@ff790000 {
1332 compatible = "rockchip,gpio-bank";
1333 reg = <0x0 0xff790000 0x0 0x100>;
1334 clocks = <&cru PCLK_GPIO4>;
1335 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1338 #gpio-cells = <0x2>;
1340 interrupt-controller;
1341 #interrupt-cells = <0x2>;
1344 pcfg_pull_up: pcfg-pull-up {
1348 pcfg_pull_down: pcfg-pull-down {
1352 pcfg_pull_none: pcfg-pull-none {
1356 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1358 drive-strength = <12>;
1361 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1363 drive-strength = <8>;
1366 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1368 drive-strength = <4>;
1371 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1373 drive-strength = <2>;
1376 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1378 drive-strength = <12>;
1381 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1383 drive-strength = <13>;
1388 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1393 rgmii_pins: rgmii-pins {
1396 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1398 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1400 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1402 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1404 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1406 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1408 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1410 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1412 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1414 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1416 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1418 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1420 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1422 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1424 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1427 rmii_pins: rmii-pins {
1430 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1432 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1434 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1436 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1438 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1440 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1442 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1444 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1446 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1448 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1453 i2c0_xfer: i2c0-xfer {
1455 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1456 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1461 i2c1_xfer: i2c1-xfer {
1463 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1464 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1469 i2c2_xfer: i2c2-xfer {
1471 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1472 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1477 i2c3_xfer: i2c3-xfer {
1479 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1480 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1485 i2c4_xfer: i2c4-xfer {
1487 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1488 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1493 i2c5_xfer: i2c5-xfer {
1495 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1496 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1501 i2c6_xfer: i2c6-xfer {
1503 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1504 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1509 i2c7_xfer: i2c7-xfer {
1511 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1512 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1517 i2c8_xfer: i2c8-xfer {
1519 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1520 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1525 i2s0_8ch_bus: i2s0-8ch-bus {
1527 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1528 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1529 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1530 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1531 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1532 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1533 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1534 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1535 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1540 i2s1_2ch_bus: i2s1-2ch-bus {
1542 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1543 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1544 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1545 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1546 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1551 ap_pwroff: ap-pwroff {
1552 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1555 ddrio_pwroff: ddrio-pwroff {
1556 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1561 spdif_bus: spdif-bus {
1563 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1568 spi0_clk: spi0-clk {
1570 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1572 spi0_cs0: spi0-cs0 {
1574 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1576 spi0_cs1: spi0-cs1 {
1578 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1582 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1586 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1591 spi1_clk: spi1-clk {
1593 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1595 spi1_cs0: spi1-cs0 {
1597 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1601 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1605 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1610 spi2_clk: spi2-clk {
1612 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1614 spi2_cs0: spi2-cs0 {
1616 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1620 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1624 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1629 spi3_clk: spi3-clk {
1631 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1633 spi3_cs0: spi3-cs0 {
1635 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1639 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1643 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1648 spi4_clk: spi4-clk {
1650 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1652 spi4_cs0: spi4-cs0 {
1654 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1658 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1662 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1667 spi5_clk: spi5-clk {
1669 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1671 spi5_cs0: spi5-cs0 {
1673 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1677 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1681 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1686 otp_gpio: otp-gpio {
1687 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1691 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1696 uart0_xfer: uart0-xfer {
1698 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1699 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1702 uart0_cts: uart0-cts {
1704 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1707 uart0_rts: uart0-rts {
1709 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1714 uart1_xfer: uart1-xfer {
1716 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1717 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1722 uart2a_xfer: uart2a-xfer {
1724 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1725 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1730 uart2b_xfer: uart2b-xfer {
1732 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1733 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1738 uart2c_xfer: uart2c-xfer {
1740 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1741 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1746 uart3_xfer: uart3-xfer {
1748 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1749 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1752 uart3_cts: uart3-cts {
1754 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1757 uart3_rts: uart3-rts {
1759 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1764 uart4_xfer: uart4-xfer {
1766 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1767 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1772 uarthdcp_xfer: uarthdcp-xfer {
1774 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1775 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1780 pwm0_pin: pwm0-pin {
1782 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1785 vop0_pwm_pin: vop0-pwm-pin {
1787 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1792 pwm1_pin: pwm1-pin {
1794 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1797 vop1_pwm_pin: vop1-pwm-pin {
1799 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1804 pwm2_pin: pwm2-pin {
1806 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1811 pwm3a_pin: pwm3a-pin {
1813 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1818 pwm3b_pin: pwm3b-pin {
1820 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1825 pcie_clkreqn: pci-clkreqn {
1827 <2 26 RK_FUNC_2 &pcfg_pull_none>;
1830 pcie_clkreqnb: pci-clkreqnb {
1832 <4 24 RK_FUNC_1 &pcfg_pull_none>;