arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_l0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_l1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_l2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_l3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_b0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_b1>;
  65                                 };
  66                         };
  67                 };
  68
  69                 cpu_l0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         capacity-dmips-mhz = <485>;
  75                         clocks = <&cru ARMCLKL>;
  76                         #cooling-cells = <2>; /* min followed by max */
  77                         dynamic-power-coefficient = <100>;
  78                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  79                 };
  80
  81                 cpu_l1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                         capacity-dmips-mhz = <485>;
  87                         clocks = <&cru ARMCLKL>;
  88                         #cooling-cells = <2>; /* min followed by max */
  89                         dynamic-power-coefficient = <100>;
  90                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  91                 };
  92
  93                 cpu_l2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         capacity-dmips-mhz = <485>;
  99                         clocks = <&cru ARMCLKL>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <100>;
 102                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 103                 };
 104
 105                 cpu_l3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53";
 108                         reg = <0x0 0x3>;
 109                         enable-method = "psci";
 110                         capacity-dmips-mhz = <485>;
 111                         clocks = <&cru ARMCLKL>;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         dynamic-power-coefficient = <100>;
 114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 115                 };
 116
 117                 cpu_b0: cpu@100 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a72";
 120                         reg = <0x0 0x100>;
 121                         enable-method = "psci";
 122                         capacity-dmips-mhz = <1024>;
 123                         clocks = <&cru ARMCLKB>;
 124                         #cooling-cells = <2>; /* min followed by max */
 125                         dynamic-power-coefficient = <436>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127
 128                         thermal-idle {
 129                                 #cooling-cells = <2>;
 130                                 duration-us = <10000>;
 131                                 exit-latency-us = <500>;
 132                         };
 133                 };
 134
 135                 cpu_b1: cpu@101 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72";
 138                         reg = <0x0 0x101>;
 139                         enable-method = "psci";
 140                         capacity-dmips-mhz = <1024>;
 141                         clocks = <&cru ARMCLKB>;
 142                         #cooling-cells = <2>; /* min followed by max */
 143                         dynamic-power-coefficient = <436>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145
 146                         thermal-idle {
 147                                 #cooling-cells = <2>;
 148                                 duration-us = <10000>;
 149                                 exit-latency-us = <500>;
 150                         };
 151                 };
 152
 153                 idle-states {
 154                         entry-method = "psci";
 155
 156                         CPU_SLEEP: cpu-sleep {
 157                                 compatible = "arm,idle-state";
 158                                 local-timer-stop;
 159                                 arm,psci-suspend-param = <0x0010000>;
 160                                 entry-latency-us = <120>;
 161                                 exit-latency-us = <250>;
 162                                 min-residency-us = <900>;
 163                         };
 164
 165                         CLUSTER_SLEEP: cluster-sleep {
 166                                 compatible = "arm,idle-state";
 167                                 local-timer-stop;
 168                                 arm,psci-suspend-param = <0x1010000>;
 169                                 entry-latency-us = <400>;
 170                                 exit-latency-us = <500>;
 171                                 min-residency-us = <2000>;
 172                         };
 173                 };
 174         };
 175
 176         display-subsystem {
 177                 compatible = "rockchip,display-subsystem";
 178                 ports = <&vopl_out>, <&vopb_out>;
 179         };
 180
 181         dmc: memory-controller {
 182                 compatible = "rockchip,rk3399-dmc";
 183                 rockchip,pmu = <&pmugrf>;
 184                 devfreq-events = <&dfi>;
 185                 clocks = <&cru SCLK_DDRC>;
 186                 clock-names = "dmc_clk";
 187                 status = "disabled";
 188         };
 189
 190         pmu_a53 {
 191                 compatible = "arm,cortex-a53-pmu";
 192                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 193         };
 194
 195         pmu_a72 {
 196                 compatible = "arm,cortex-a72-pmu";
 197                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-1.0";
 202                 method = "smc";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv8-timer";
 207                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 208                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 209                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 210                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 211                 arm,no-tick-in-suspend;
 212         };
 213
 214         xin24m: xin24m {
 215                 compatible = "fixed-clock";
 216                 clock-frequency = <24000000>;
 217                 clock-output-names = "xin24m";
 218                 #clock-cells = <0>;
 219         };
 220
 221         pcie0: pcie@f8000000 {
 222                 compatible = "rockchip,rk3399-pcie";
 223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 224                       <0x0 0xfd000000 0x0 0x1000000>;
 225                 reg-names = "axi-base", "apb-base";
 226                 device_type = "pci";
 227                 #address-cells = <3>;
 228                 #size-cells = <2>;
 229                 #interrupt-cells = <1>;
 230                 aspm-no-l0s;
 231                 bus-range = <0x0 0x1f>;
 232                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 233                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 234                 clock-names = "aclk", "aclk-perf",
 235                               "hclk", "pm";
 236                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 237                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 238                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 interrupt-names = "sys", "legacy", "client";
 240                 interrupt-map-mask = <0 0 0 7>;
 241                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 242                                 <0 0 0 2 &pcie0_intc 1>,
 243                                 <0 0 0 3 &pcie0_intc 2>,
 244                                 <0 0 0 4 &pcie0_intc 3>;
 245                 max-link-speed = <1>;
 246                 msi-map = <0x0 &its 0x0 0x1000>;
 247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 248                        <&pcie_phy 2>, <&pcie_phy 3>;
 249                 phy-names = "pcie-phy-0", "pcie-phy-1",
 250                             "pcie-phy-2", "pcie-phy-3";
 251                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
 252                          <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 256                          <&cru SRST_A_PCIE>;
 257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 258                               "pm", "pclk", "aclk";
 259                 status = "disabled";
 260
 261                 pcie0_intc: interrupt-controller {
 262                         interrupt-controller;
 263                         #address-cells = <0>;
 264                         #interrupt-cells = <1>;
 265                 };
 266         };
 267
 268         pcie0_ep: pcie-ep@f8000000 {
 269                 compatible = "rockchip,rk3399-pcie-ep";
 270                 reg = <0x0 0xfd000000 0x0 0x1000000>,
 271                       <0x0 0xfa000000 0x0 0x2000000>;
 272                 reg-names = "apb-base", "mem-base";
 273                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 274                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 275                 clock-names = "aclk", "aclk-perf",
 276                               "hclk", "pm";
 277                 max-functions = /bits/ 8 <8>;
 278                 num-lanes = <4>;
 279                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 280                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 281                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 282                          <&cru SRST_A_PCIE>;
 283                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 284                               "pm", "pclk", "aclk";
 285                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 286                        <&pcie_phy 2>, <&pcie_phy 3>;
 287                 phy-names = "pcie-phy-0", "pcie-phy-1",
 288                             "pcie-phy-2", "pcie-phy-3";
 289                 rockchip,max-outbound-regions = <32>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&pcie_clkreqnb_cpm>;
 292                 status = "disabled";
 293         };
 294
 295         gmac: ethernet@fe300000 {
 296                 compatible = "rockchip,rk3399-gmac";
 297                 reg = <0x0 0xfe300000 0x0 0x10000>;
 298                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 299                 interrupt-names = "macirq";
 300                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 301                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 302                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 303                          <&cru PCLK_GMAC>;
 304                 clock-names = "stmmaceth", "mac_clk_rx",
 305                               "mac_clk_tx", "clk_mac_ref",
 306                               "clk_mac_refout", "aclk_mac",
 307                               "pclk_mac";
 308                 power-domains = <&power RK3399_PD_GMAC>;
 309                 resets = <&cru SRST_A_GMAC>;
 310                 reset-names = "stmmaceth";
 311                 rockchip,grf = <&grf>;
 312                 snps,txpbl = <0x4>;
 313                 status = "disabled";
 314         };
 315
 316         sdio0: mmc@fe310000 {
 317                 compatible = "rockchip,rk3399-dw-mshc",
 318                              "rockchip,rk3288-dw-mshc";
 319                 reg = <0x0 0xfe310000 0x0 0x4000>;
 320                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 321                 max-frequency = <150000000>;
 322                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 323                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 324                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 325                 fifo-depth = <0x100>;
 326                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 327                 resets = <&cru SRST_SDIO0>;
 328                 reset-names = "reset";
 329                 status = "disabled";
 330         };
 331
 332         sdmmc: mmc@fe320000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe320000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 337                 max-frequency = <150000000>;
 338                 assigned-clocks = <&cru HCLK_SD>;
 339                 assigned-clock-rates = <200000000>;
 340                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 341                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 342                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 343                 fifo-depth = <0x100>;
 344                 power-domains = <&power RK3399_PD_SD>;
 345                 resets = <&cru SRST_SDMMC>;
 346                 reset-names = "reset";
 347                 status = "disabled";
 348         };
 349
 350         sdhci: mmc@fe330000 {
 351                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 352                 reg = <0x0 0xfe330000 0x0 0x10000>;
 353                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 354                 arasan,soc-ctl-syscon = <&grf>;
 355                 assigned-clocks = <&cru SCLK_EMMC>;
 356                 assigned-clock-rates = <200000000>;
 357                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 358                 clock-names = "clk_xin", "clk_ahb";
 359                 clock-output-names = "emmc_cardclock";
 360                 #clock-cells = <0>;
 361                 phys = <&emmc_phy>;
 362                 phy-names = "phy_arasan";
 363                 power-domains = <&power RK3399_PD_EMMC>;
 364                 disable-cqe-dcmd;
 365                 status = "disabled";
 366         };
 367
 368         usb_host0_ehci: usb@fe380000 {
 369                 compatible = "generic-ehci";
 370                 reg = <0x0 0xfe380000 0x0 0x20000>;
 371                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 373                          <&u2phy0>;
 374                 phys = <&u2phy0_host>;
 375                 phy-names = "usb";
 376                 status = "disabled";
 377         };
 378
 379         usb_host0_ohci: usb@fe3a0000 {
 380                 compatible = "generic-ohci";
 381                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 382                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 383                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 384                          <&u2phy0>;
 385                 phys = <&u2phy0_host>;
 386                 phy-names = "usb";
 387                 status = "disabled";
 388         };
 389
 390         usb_host1_ehci: usb@fe3c0000 {
 391                 compatible = "generic-ehci";
 392                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 393                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 394                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 395                          <&u2phy1>;
 396                 phys = <&u2phy1_host>;
 397                 phy-names = "usb";
 398                 status = "disabled";
 399         };
 400
 401         usb_host1_ohci: usb@fe3e0000 {
 402                 compatible = "generic-ohci";
 403                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 404                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 405                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 406                          <&u2phy1>;
 407                 phys = <&u2phy1_host>;
 408                 phy-names = "usb";
 409                 status = "disabled";
 410         };
 411
 412         debug@fe430000 {
 413                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 414                 reg = <0 0xfe430000 0 0x1000>;
 415                 clocks = <&cru PCLK_COREDBG_L>;
 416                 clock-names = "apb_pclk";
 417                 cpu = <&cpu_l0>;
 418         };
 419
 420         debug@fe432000 {
 421                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 422                 reg = <0 0xfe432000 0 0x1000>;
 423                 clocks = <&cru PCLK_COREDBG_L>;
 424                 clock-names = "apb_pclk";
 425                 cpu = <&cpu_l1>;
 426         };
 427
 428         debug@fe434000 {
 429                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 430                 reg = <0 0xfe434000 0 0x1000>;
 431                 clocks = <&cru PCLK_COREDBG_L>;
 432                 clock-names = "apb_pclk";
 433                 cpu = <&cpu_l2>;
 434         };
 435
 436         debug@fe436000 {
 437                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 438                 reg = <0 0xfe436000 0 0x1000>;
 439                 clocks = <&cru PCLK_COREDBG_L>;
 440                 clock-names = "apb_pclk";
 441                 cpu = <&cpu_l3>;
 442         };
 443
 444         debug@fe610000 {
 445                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 446                 reg = <0 0xfe610000 0 0x1000>;
 447                 clocks = <&cru PCLK_COREDBG_B>;
 448                 clock-names = "apb_pclk";
 449                 cpu = <&cpu_b0>;
 450         };
 451
 452         debug@fe710000 {
 453                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 454                 reg = <0 0xfe710000 0 0x1000>;
 455                 clocks = <&cru PCLK_COREDBG_B>;
 456                 clock-names = "apb_pclk";
 457                 cpu = <&cpu_b1>;
 458         };
 459
 460         usbdrd3_0: usb@fe800000 {
 461                 compatible = "rockchip,rk3399-dwc3";
 462                 #address-cells = <2>;
 463                 #size-cells = <2>;
 464                 ranges;
 465                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 466                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 467                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 468                 clock-names = "ref_clk", "suspend_clk",
 469                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 470                               "aclk_usb3", "grf_clk";
 471                 resets = <&cru SRST_A_USB3_OTG0>;
 472                 reset-names = "usb3-otg";
 473                 status = "disabled";
 474
 475                 usbdrd_dwc3_0: usb@fe800000 {
 476                         compatible = "snps,dwc3";
 477                         reg = <0x0 0xfe800000 0x0 0x100000>;
 478                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 479                         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
 480                                  <&cru SCLK_USB3OTG0_SUSPEND>;
 481                         clock-names = "ref", "bus_early", "suspend";
 482                         dr_mode = "otg";
 483                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 484                         phy-names = "usb2-phy", "usb3-phy";
 485                         phy_type = "utmi_wide";
 486                         snps,dis_enblslpm_quirk;
 487                         snps,dis-u2-freeclk-exists-quirk;
 488                         snps,dis_u2_susphy_quirk;
 489                         snps,dis-del-phy-power-chg-quirk;
 490                         snps,dis-tx-ipgap-linecheck-quirk;
 491                         power-domains = <&power RK3399_PD_USB3>;
 492                         status = "disabled";
 493                 };
 494         };
 495
 496         usbdrd3_1: usb@fe900000 {
 497                 compatible = "rockchip,rk3399-dwc3";
 498                 #address-cells = <2>;
 499                 #size-cells = <2>;
 500                 ranges;
 501                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 502                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 503                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 504                 clock-names = "ref_clk", "suspend_clk",
 505                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 506                               "aclk_usb3", "grf_clk";
 507                 resets = <&cru SRST_A_USB3_OTG1>;
 508                 reset-names = "usb3-otg";
 509                 status = "disabled";
 510
 511                 usbdrd_dwc3_1: usb@fe900000 {
 512                         compatible = "snps,dwc3";
 513                         reg = <0x0 0xfe900000 0x0 0x100000>;
 514                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 515                         clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
 516                                  <&cru SCLK_USB3OTG1_SUSPEND>;
 517                         clock-names = "ref", "bus_early", "suspend";
 518                         dr_mode = "otg";
 519                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 520                         phy-names = "usb2-phy", "usb3-phy";
 521                         phy_type = "utmi_wide";
 522                         snps,dis_enblslpm_quirk;
 523                         snps,dis-u2-freeclk-exists-quirk;
 524                         snps,dis_u2_susphy_quirk;
 525                         snps,dis-del-phy-power-chg-quirk;
 526                         snps,dis-tx-ipgap-linecheck-quirk;
 527                         power-domains = <&power RK3399_PD_USB3>;
 528                         status = "disabled";
 529                 };
 530         };
 531
 532         cdn_dp: dp@fec00000 {
 533                 compatible = "rockchip,rk3399-cdn-dp";
 534                 reg = <0x0 0xfec00000 0x0 0x100000>;
 535                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 536                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 537                 assigned-clock-rates = <100000000>, <200000000>;
 538                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 539                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 540                 clock-names = "core-clk", "pclk", "spdif", "grf";
 541                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 542                 power-domains = <&power RK3399_PD_HDCP>;
 543                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 544                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 545                 reset-names = "spdif", "dptx", "apb", "core";
 546                 rockchip,grf = <&grf>;
 547                 #sound-dai-cells = <1>;
 548                 status = "disabled";
 549
 550                 ports {
 551                         dp_in: port {
 552                                 #address-cells = <1>;
 553                                 #size-cells = <0>;
 554
 555                                 dp_in_vopb: endpoint@0 {
 556                                         reg = <0>;
 557                                         remote-endpoint = <&vopb_out_dp>;
 558                                 };
 559
 560                                 dp_in_vopl: endpoint@1 {
 561                                         reg = <1>;
 562                                         remote-endpoint = <&vopl_out_dp>;
 563                                 };
 564                         };
 565                 };
 566         };
 567
 568         gic: interrupt-controller@fee00000 {
 569                 compatible = "arm,gic-v3";
 570                 #interrupt-cells = <4>;
 571                 #address-cells = <2>;
 572                 #size-cells = <2>;
 573                 ranges;
 574                 interrupt-controller;
 575
 576                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 577                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 578                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 579                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 580                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 581                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 582                 its: msi-controller@fee20000 {
 583                         compatible = "arm,gic-v3-its";
 584                         msi-controller;
 585                         #msi-cells = <1>;
 586                         reg = <0x0 0xfee20000 0x0 0x20000>;
 587                 };
 588
 589                 ppi-partitions {
 590                         ppi_cluster0: interrupt-partition-0 {
 591                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 592                         };
 593
 594                         ppi_cluster1: interrupt-partition-1 {
 595                                 affinity = <&cpu_b0 &cpu_b1>;
 596                         };
 597                 };
 598         };
 599
 600         saradc: saradc@ff100000 {
 601                 compatible = "rockchip,rk3399-saradc";
 602                 reg = <0x0 0xff100000 0x0 0x100>;
 603                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 604                 #io-channel-cells = <1>;
 605                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 606                 clock-names = "saradc", "apb_pclk";
 607                 resets = <&cru SRST_P_SARADC>;
 608                 reset-names = "saradc-apb";
 609                 status = "disabled";
 610         };
 611
 612         crypto0: crypto@ff8b0000 {
 613                 compatible = "rockchip,rk3399-crypto";
 614                 reg = <0x0 0xff8b0000 0x0 0x4000>;
 615                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
 616                 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
 617                 clock-names = "hclk_master", "hclk_slave", "sclk";
 618                 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
 619                 reset-names = "master", "slave", "crypto-rst";
 620         };
 621
 622         crypto1: crypto@ff8b8000 {
 623                 compatible = "rockchip,rk3399-crypto";
 624                 reg = <0x0 0xff8b8000 0x0 0x4000>;
 625                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
 626                 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
 627                 clock-names = "hclk_master", "hclk_slave", "sclk";
 628                 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
 629                 reset-names = "master", "slave", "crypto-rst";
 630         };
 631
 632         i2c1: i2c@ff110000 {
 633                 compatible = "rockchip,rk3399-i2c";
 634                 reg = <0x0 0xff110000 0x0 0x1000>;
 635                 assigned-clocks = <&cru SCLK_I2C1>;
 636                 assigned-clock-rates = <200000000>;
 637                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 638                 clock-names = "i2c", "pclk";
 639                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&i2c1_xfer>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 status = "disabled";
 645         };
 646
 647         i2c2: i2c@ff120000 {
 648                 compatible = "rockchip,rk3399-i2c";
 649                 reg = <0x0 0xff120000 0x0 0x1000>;
 650                 assigned-clocks = <&cru SCLK_I2C2>;
 651                 assigned-clock-rates = <200000000>;
 652                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 653                 clock-names = "i2c", "pclk";
 654                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&i2c2_xfer>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         i2c3: i2c@ff130000 {
 663                 compatible = "rockchip,rk3399-i2c";
 664                 reg = <0x0 0xff130000 0x0 0x1000>;
 665                 assigned-clocks = <&cru SCLK_I2C3>;
 666                 assigned-clock-rates = <200000000>;
 667                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 668                 clock-names = "i2c", "pclk";
 669                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&i2c3_xfer>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 status = "disabled";
 675         };
 676
 677         i2c5: i2c@ff140000 {
 678                 compatible = "rockchip,rk3399-i2c";
 679                 reg = <0x0 0xff140000 0x0 0x1000>;
 680                 assigned-clocks = <&cru SCLK_I2C5>;
 681                 assigned-clock-rates = <200000000>;
 682                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 683                 clock-names = "i2c", "pclk";
 684                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 685                 pinctrl-names = "default";
 686                 pinctrl-0 = <&i2c5_xfer>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 status = "disabled";
 690         };
 691
 692         i2c6: i2c@ff150000 {
 693                 compatible = "rockchip,rk3399-i2c";
 694                 reg = <0x0 0xff150000 0x0 0x1000>;
 695                 assigned-clocks = <&cru SCLK_I2C6>;
 696                 assigned-clock-rates = <200000000>;
 697                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 698                 clock-names = "i2c", "pclk";
 699                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&i2c6_xfer>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         i2c7: i2c@ff160000 {
 708                 compatible = "rockchip,rk3399-i2c";
 709                 reg = <0x0 0xff160000 0x0 0x1000>;
 710                 assigned-clocks = <&cru SCLK_I2C7>;
 711                 assigned-clock-rates = <200000000>;
 712                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 713                 clock-names = "i2c", "pclk";
 714                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&i2c7_xfer>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         uart0: serial@ff180000 {
 723                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 724                 reg = <0x0 0xff180000 0x0 0x100>;
 725                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 726                 clock-names = "baudclk", "apb_pclk";
 727                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 728                 reg-shift = <2>;
 729                 reg-io-width = <4>;
 730                 pinctrl-names = "default";
 731                 pinctrl-0 = <&uart0_xfer>;
 732                 status = "disabled";
 733         };
 734
 735         uart1: serial@ff190000 {
 736                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 737                 reg = <0x0 0xff190000 0x0 0x100>;
 738                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 739                 clock-names = "baudclk", "apb_pclk";
 740                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 741                 reg-shift = <2>;
 742                 reg-io-width = <4>;
 743                 pinctrl-names = "default";
 744                 pinctrl-0 = <&uart1_xfer>;
 745                 status = "disabled";
 746         };
 747
 748         uart2: serial@ff1a0000 {
 749                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 750                 reg = <0x0 0xff1a0000 0x0 0x100>;
 751                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 752                 clock-names = "baudclk", "apb_pclk";
 753                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 754                 reg-shift = <2>;
 755                 reg-io-width = <4>;
 756                 pinctrl-names = "default";
 757                 pinctrl-0 = <&uart2c_xfer>;
 758                 status = "disabled";
 759         };
 760
 761         uart3: serial@ff1b0000 {
 762                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 763                 reg = <0x0 0xff1b0000 0x0 0x100>;
 764                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 765                 clock-names = "baudclk", "apb_pclk";
 766                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 767                 reg-shift = <2>;
 768                 reg-io-width = <4>;
 769                 pinctrl-names = "default";
 770                 pinctrl-0 = <&uart3_xfer>;
 771                 status = "disabled";
 772         };
 773
 774         spi0: spi@ff1c0000 {
 775                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 776                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 777                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 778                 clock-names = "spiclk", "apb_pclk";
 779                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 780                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
 781                 dma-names = "tx", "rx";
 782                 pinctrl-names = "default";
 783                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 784                 #address-cells = <1>;
 785                 #size-cells = <0>;
 786                 status = "disabled";
 787         };
 788
 789         spi1: spi@ff1d0000 {
 790                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 791                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 792                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 793                 clock-names = "spiclk", "apb_pclk";
 794                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 795                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
 796                 dma-names = "tx", "rx";
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 799                 #address-cells = <1>;
 800                 #size-cells = <0>;
 801                 status = "disabled";
 802         };
 803
 804         spi2: spi@ff1e0000 {
 805                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 806                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 807                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 808                 clock-names = "spiclk", "apb_pclk";
 809                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 810                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
 811                 dma-names = "tx", "rx";
 812                 pinctrl-names = "default";
 813                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 814                 #address-cells = <1>;
 815                 #size-cells = <0>;
 816                 status = "disabled";
 817         };
 818
 819         spi4: spi@ff1f0000 {
 820                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 821                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 822                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 823                 clock-names = "spiclk", "apb_pclk";
 824                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 825                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
 826                 dma-names = "tx", "rx";
 827                 pinctrl-names = "default";
 828                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 829                 #address-cells = <1>;
 830                 #size-cells = <0>;
 831                 status = "disabled";
 832         };
 833
 834         spi5: spi@ff200000 {
 835                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 836                 reg = <0x0 0xff200000 0x0 0x1000>;
 837                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 838                 clock-names = "spiclk", "apb_pclk";
 839                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 840                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
 841                 dma-names = "tx", "rx";
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 844                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 845                 #address-cells = <1>;
 846                 #size-cells = <0>;
 847                 status = "disabled";
 848         };
 849
 850         thermal_zones: thermal-zones {
 851                 cpu_thermal: cpu-thermal {
 852                         polling-delay-passive = <100>;
 853                         polling-delay = <1000>;
 854
 855                         thermal-sensors = <&tsadc 0>;
 856
 857                         trips {
 858                                 cpu_alert0: cpu_alert0 {
 859                                         temperature = <70000>;
 860                                         hysteresis = <2000>;
 861                                         type = "passive";
 862                                 };
 863                                 cpu_alert1: cpu_alert1 {
 864                                         temperature = <75000>;
 865                                         hysteresis = <2000>;
 866                                         type = "passive";
 867                                 };
 868                                 cpu_crit: cpu_crit {
 869                                         temperature = <95000>;
 870                                         hysteresis = <2000>;
 871                                         type = "critical";
 872                                 };
 873                         };
 874
 875                         cooling-maps {
 876                                 map0 {
 877                                         trip = <&cpu_alert0>;
 878                                         cooling-device =
 879                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 880                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 881                                 };
 882                                 map1 {
 883                                         trip = <&cpu_alert1>;
 884                                         cooling-device =
 885                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 886                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 887                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 888                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 889                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 890                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 891                                 };
 892                         };
 893                 };
 894
 895                 gpu_thermal: gpu-thermal {
 896                         polling-delay-passive = <100>;
 897                         polling-delay = <1000>;
 898
 899                         thermal-sensors = <&tsadc 1>;
 900
 901                         trips {
 902                                 gpu_alert0: gpu_alert0 {
 903                                         temperature = <75000>;
 904                                         hysteresis = <2000>;
 905                                         type = "passive";
 906                                 };
 907                                 gpu_crit: gpu_crit {
 908                                         temperature = <95000>;
 909                                         hysteresis = <2000>;
 910                                         type = "critical";
 911                                 };
 912                         };
 913
 914                         cooling-maps {
 915                                 map0 {
 916                                         trip = <&gpu_alert0>;
 917                                         cooling-device =
 918                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 919                                 };
 920                         };
 921                 };
 922         };
 923
 924         tsadc: tsadc@ff260000 {
 925                 compatible = "rockchip,rk3399-tsadc";
 926                 reg = <0x0 0xff260000 0x0 0x100>;
 927                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 928                 assigned-clocks = <&cru SCLK_TSADC>;
 929                 assigned-clock-rates = <750000>;
 930                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 931                 clock-names = "tsadc", "apb_pclk";
 932                 resets = <&cru SRST_TSADC>;
 933                 reset-names = "tsadc-apb";
 934                 rockchip,grf = <&grf>;
 935                 rockchip,hw-tshut-temp = <95000>;
 936                 pinctrl-names = "init", "default", "sleep";
 937                 pinctrl-0 = <&otp_pin>;
 938                 pinctrl-1 = <&otp_out>;
 939                 pinctrl-2 = <&otp_pin>;
 940                 #thermal-sensor-cells = <1>;
 941                 status = "disabled";
 942         };
 943
 944         qos_emmc: qos@ffa58000 {
 945                 compatible = "rockchip,rk3399-qos", "syscon";
 946                 reg = <0x0 0xffa58000 0x0 0x20>;
 947         };
 948
 949         qos_gmac: qos@ffa5c000 {
 950                 compatible = "rockchip,rk3399-qos", "syscon";
 951                 reg = <0x0 0xffa5c000 0x0 0x20>;
 952         };
 953
 954         qos_pcie: qos@ffa60080 {
 955                 compatible = "rockchip,rk3399-qos", "syscon";
 956                 reg = <0x0 0xffa60080 0x0 0x20>;
 957         };
 958
 959         qos_usb_host0: qos@ffa60100 {
 960                 compatible = "rockchip,rk3399-qos", "syscon";
 961                 reg = <0x0 0xffa60100 0x0 0x20>;
 962         };
 963
 964         qos_usb_host1: qos@ffa60180 {
 965                 compatible = "rockchip,rk3399-qos", "syscon";
 966                 reg = <0x0 0xffa60180 0x0 0x20>;
 967         };
 968
 969         qos_usb_otg0: qos@ffa70000 {
 970                 compatible = "rockchip,rk3399-qos", "syscon";
 971                 reg = <0x0 0xffa70000 0x0 0x20>;
 972         };
 973
 974         qos_usb_otg1: qos@ffa70080 {
 975                 compatible = "rockchip,rk3399-qos", "syscon";
 976                 reg = <0x0 0xffa70080 0x0 0x20>;
 977         };
 978
 979         qos_sd: qos@ffa74000 {
 980                 compatible = "rockchip,rk3399-qos", "syscon";
 981                 reg = <0x0 0xffa74000 0x0 0x20>;
 982         };
 983
 984         qos_sdioaudio: qos@ffa76000 {
 985                 compatible = "rockchip,rk3399-qos", "syscon";
 986                 reg = <0x0 0xffa76000 0x0 0x20>;
 987         };
 988
 989         qos_hdcp: qos@ffa90000 {
 990                 compatible = "rockchip,rk3399-qos", "syscon";
 991                 reg = <0x0 0xffa90000 0x0 0x20>;
 992         };
 993
 994         qos_iep: qos@ffa98000 {
 995                 compatible = "rockchip,rk3399-qos", "syscon";
 996                 reg = <0x0 0xffa98000 0x0 0x20>;
 997         };
 998
 999         qos_isp0_m0: qos@ffaa0000 {
1000                 compatible = "rockchip,rk3399-qos", "syscon";
1001                 reg = <0x0 0xffaa0000 0x0 0x20>;
1002         };
1003
1004         qos_isp0_m1: qos@ffaa0080 {
1005                 compatible = "rockchip,rk3399-qos", "syscon";
1006                 reg = <0x0 0xffaa0080 0x0 0x20>;
1007         };
1008
1009         qos_isp1_m0: qos@ffaa8000 {
1010                 compatible = "rockchip,rk3399-qos", "syscon";
1011                 reg = <0x0 0xffaa8000 0x0 0x20>;
1012         };
1013
1014         qos_isp1_m1: qos@ffaa8080 {
1015                 compatible = "rockchip,rk3399-qos", "syscon";
1016                 reg = <0x0 0xffaa8080 0x0 0x20>;
1017         };
1018
1019         qos_rga_r: qos@ffab0000 {
1020                 compatible = "rockchip,rk3399-qos", "syscon";
1021                 reg = <0x0 0xffab0000 0x0 0x20>;
1022         };
1023
1024         qos_rga_w: qos@ffab0080 {
1025                 compatible = "rockchip,rk3399-qos", "syscon";
1026                 reg = <0x0 0xffab0080 0x0 0x20>;
1027         };
1028
1029         qos_video_m0: qos@ffab8000 {
1030                 compatible = "rockchip,rk3399-qos", "syscon";
1031                 reg = <0x0 0xffab8000 0x0 0x20>;
1032         };
1033
1034         qos_video_m1_r: qos@ffac0000 {
1035                 compatible = "rockchip,rk3399-qos", "syscon";
1036                 reg = <0x0 0xffac0000 0x0 0x20>;
1037         };
1038
1039         qos_video_m1_w: qos@ffac0080 {
1040                 compatible = "rockchip,rk3399-qos", "syscon";
1041                 reg = <0x0 0xffac0080 0x0 0x20>;
1042         };
1043
1044         qos_vop_big_r: qos@ffac8000 {
1045                 compatible = "rockchip,rk3399-qos", "syscon";
1046                 reg = <0x0 0xffac8000 0x0 0x20>;
1047         };
1048
1049         qos_vop_big_w: qos@ffac8080 {
1050                 compatible = "rockchip,rk3399-qos", "syscon";
1051                 reg = <0x0 0xffac8080 0x0 0x20>;
1052         };
1053
1054         qos_vop_little: qos@ffad0000 {
1055                 compatible = "rockchip,rk3399-qos", "syscon";
1056                 reg = <0x0 0xffad0000 0x0 0x20>;
1057         };
1058
1059         qos_perihp: qos@ffad8080 {
1060                 compatible = "rockchip,rk3399-qos", "syscon";
1061                 reg = <0x0 0xffad8080 0x0 0x20>;
1062         };
1063
1064         qos_gpu: qos@ffae0000 {
1065                 compatible = "rockchip,rk3399-qos", "syscon";
1066                 reg = <0x0 0xffae0000 0x0 0x20>;
1067         };
1068
1069         pmu: power-management@ff310000 {
1070                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1071                 reg = <0x0 0xff310000 0x0 0x1000>;
1072
1073                 /*
1074                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
1075                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
1076                  * Some of the power domains are grouped together for every
1077                  * voltage domain.
1078                  * The detail contents as below.
1079                  */
1080                 power: power-controller {
1081                         compatible = "rockchip,rk3399-power-controller";
1082                         #power-domain-cells = <1>;
1083                         #address-cells = <1>;
1084                         #size-cells = <0>;
1085
1086                         /* These power domains are grouped by VD_CENTER */
1087                         power-domain@RK3399_PD_IEP {
1088                                 reg = <RK3399_PD_IEP>;
1089                                 clocks = <&cru ACLK_IEP>,
1090                                          <&cru HCLK_IEP>;
1091                                 pm_qos = <&qos_iep>;
1092                                 #power-domain-cells = <0>;
1093                         };
1094                         power-domain@RK3399_PD_RGA {
1095                                 reg = <RK3399_PD_RGA>;
1096                                 clocks = <&cru ACLK_RGA>,
1097                                          <&cru HCLK_RGA>;
1098                                 pm_qos = <&qos_rga_r>,
1099                                          <&qos_rga_w>;
1100                                 #power-domain-cells = <0>;
1101                         };
1102                         power-domain@RK3399_PD_VCODEC {
1103                                 reg = <RK3399_PD_VCODEC>;
1104                                 clocks = <&cru ACLK_VCODEC>,
1105                                          <&cru HCLK_VCODEC>;
1106                                 pm_qos = <&qos_video_m0>;
1107                                 #power-domain-cells = <0>;
1108                         };
1109                         power-domain@RK3399_PD_VDU {
1110                                 reg = <RK3399_PD_VDU>;
1111                                 clocks = <&cru ACLK_VDU>,
1112                                          <&cru HCLK_VDU>,
1113                                          <&cru SCLK_VDU_CA>,
1114                                          <&cru SCLK_VDU_CORE>;
1115                                 pm_qos = <&qos_video_m1_r>,
1116                                          <&qos_video_m1_w>;
1117                                 #power-domain-cells = <0>;
1118                         };
1119
1120                         /* These power domains are grouped by VD_GPU */
1121                         power-domain@RK3399_PD_GPU {
1122                                 reg = <RK3399_PD_GPU>;
1123                                 clocks = <&cru ACLK_GPU>;
1124                                 pm_qos = <&qos_gpu>;
1125                                 #power-domain-cells = <0>;
1126                         };
1127
1128                         /* These power domains are grouped by VD_LOGIC */
1129                         power-domain@RK3399_PD_EDP {
1130                                 reg = <RK3399_PD_EDP>;
1131                                 clocks = <&cru PCLK_EDP_CTRL>;
1132                                 #power-domain-cells = <0>;
1133                         };
1134                         power-domain@RK3399_PD_EMMC {
1135                                 reg = <RK3399_PD_EMMC>;
1136                                 clocks = <&cru ACLK_EMMC>;
1137                                 pm_qos = <&qos_emmc>;
1138                                 #power-domain-cells = <0>;
1139                         };
1140                         power-domain@RK3399_PD_GMAC {
1141                                 reg = <RK3399_PD_GMAC>;
1142                                 clocks = <&cru ACLK_GMAC>,
1143                                          <&cru PCLK_GMAC>;
1144                                 pm_qos = <&qos_gmac>;
1145                                 #power-domain-cells = <0>;
1146                         };
1147                         power-domain@RK3399_PD_SD {
1148                                 reg = <RK3399_PD_SD>;
1149                                 clocks = <&cru HCLK_SDMMC>,
1150                                          <&cru SCLK_SDMMC>;
1151                                 pm_qos = <&qos_sd>;
1152                                 #power-domain-cells = <0>;
1153                         };
1154                         power-domain@RK3399_PD_SDIOAUDIO {
1155                                 reg = <RK3399_PD_SDIOAUDIO>;
1156                                 clocks = <&cru HCLK_SDIO>;
1157                                 pm_qos = <&qos_sdioaudio>;
1158                                 #power-domain-cells = <0>;
1159                         };
1160                         power-domain@RK3399_PD_TCPD0 {
1161                                 reg = <RK3399_PD_TCPD0>;
1162                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1163                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1164                                 #power-domain-cells = <0>;
1165                         };
1166                         power-domain@RK3399_PD_TCPD1 {
1167                                 reg = <RK3399_PD_TCPD1>;
1168                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1169                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1170                                 #power-domain-cells = <0>;
1171                         };
1172                         power-domain@RK3399_PD_USB3 {
1173                                 reg = <RK3399_PD_USB3>;
1174                                 clocks = <&cru ACLK_USB3>;
1175                                 pm_qos = <&qos_usb_otg0>,
1176                                          <&qos_usb_otg1>;
1177                                 #power-domain-cells = <0>;
1178                         };
1179                         power-domain@RK3399_PD_VIO {
1180                                 reg = <RK3399_PD_VIO>;
1181                                 #power-domain-cells = <1>;
1182                                 #address-cells = <1>;
1183                                 #size-cells = <0>;
1184
1185                                 power-domain@RK3399_PD_HDCP {
1186                                         reg = <RK3399_PD_HDCP>;
1187                                         clocks = <&cru ACLK_HDCP>,
1188                                                  <&cru HCLK_HDCP>,
1189                                                  <&cru PCLK_HDCP>;
1190                                         pm_qos = <&qos_hdcp>;
1191                                         #power-domain-cells = <0>;
1192                                 };
1193                                 power-domain@RK3399_PD_ISP0 {
1194                                         reg = <RK3399_PD_ISP0>;
1195                                         clocks = <&cru ACLK_ISP0>,
1196                                                  <&cru HCLK_ISP0>;
1197                                         pm_qos = <&qos_isp0_m0>,
1198                                                  <&qos_isp0_m1>;
1199                                         #power-domain-cells = <0>;
1200                                 };
1201                                 power-domain@RK3399_PD_ISP1 {
1202                                         reg = <RK3399_PD_ISP1>;
1203                                         clocks = <&cru ACLK_ISP1>,
1204                                                  <&cru HCLK_ISP1>;
1205                                         pm_qos = <&qos_isp1_m0>,
1206                                                  <&qos_isp1_m1>;
1207                                         #power-domain-cells = <0>;
1208                                 };
1209                                 power-domain@RK3399_PD_VO {
1210                                         reg = <RK3399_PD_VO>;
1211                                         #power-domain-cells = <1>;
1212                                         #address-cells = <1>;
1213                                         #size-cells = <0>;
1214
1215                                         power-domain@RK3399_PD_VOPB {
1216                                                 reg = <RK3399_PD_VOPB>;
1217                                                 clocks = <&cru ACLK_VOP0>,
1218                                                          <&cru HCLK_VOP0>;
1219                                                 pm_qos = <&qos_vop_big_r>,
1220                                                          <&qos_vop_big_w>;
1221                                                 #power-domain-cells = <0>;
1222                                         };
1223                                         power-domain@RK3399_PD_VOPL {
1224                                                 reg = <RK3399_PD_VOPL>;
1225                                                 clocks = <&cru ACLK_VOP1>,
1226                                                          <&cru HCLK_VOP1>;
1227                                                 pm_qos = <&qos_vop_little>;
1228                                                 #power-domain-cells = <0>;
1229                                         };
1230                                 };
1231                         };
1232                 };
1233         };
1234
1235         pmugrf: syscon@ff320000 {
1236                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1237                 reg = <0x0 0xff320000 0x0 0x1000>;
1238
1239                 pmu_io_domains: io-domains {
1240                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1241                         status = "disabled";
1242                 };
1243         };
1244
1245         spi3: spi@ff350000 {
1246                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1247                 reg = <0x0 0xff350000 0x0 0x1000>;
1248                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1249                 clock-names = "spiclk", "apb_pclk";
1250                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1253                 #address-cells = <1>;
1254                 #size-cells = <0>;
1255                 status = "disabled";
1256         };
1257
1258         uart4: serial@ff370000 {
1259                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1260                 reg = <0x0 0xff370000 0x0 0x100>;
1261                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1262                 clock-names = "baudclk", "apb_pclk";
1263                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1264                 reg-shift = <2>;
1265                 reg-io-width = <4>;
1266                 pinctrl-names = "default";
1267                 pinctrl-0 = <&uart4_xfer>;
1268                 status = "disabled";
1269         };
1270
1271         i2c0: i2c@ff3c0000 {
1272                 compatible = "rockchip,rk3399-i2c";
1273                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1274                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1275                 assigned-clock-rates = <200000000>;
1276                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1277                 clock-names = "i2c", "pclk";
1278                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1279                 pinctrl-names = "default";
1280                 pinctrl-0 = <&i2c0_xfer>;
1281                 #address-cells = <1>;
1282                 #size-cells = <0>;
1283                 status = "disabled";
1284         };
1285
1286         i2c4: i2c@ff3d0000 {
1287                 compatible = "rockchip,rk3399-i2c";
1288                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1289                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1290                 assigned-clock-rates = <200000000>;
1291                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1292                 clock-names = "i2c", "pclk";
1293                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1294                 pinctrl-names = "default";
1295                 pinctrl-0 = <&i2c4_xfer>;
1296                 #address-cells = <1>;
1297                 #size-cells = <0>;
1298                 status = "disabled";
1299         };
1300
1301         i2c8: i2c@ff3e0000 {
1302                 compatible = "rockchip,rk3399-i2c";
1303                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1304                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1305                 assigned-clock-rates = <200000000>;
1306                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1307                 clock-names = "i2c", "pclk";
1308                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1309                 pinctrl-names = "default";
1310                 pinctrl-0 = <&i2c8_xfer>;
1311                 #address-cells = <1>;
1312                 #size-cells = <0>;
1313                 status = "disabled";
1314         };
1315
1316         pwm0: pwm@ff420000 {
1317                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1318                 reg = <0x0 0xff420000 0x0 0x10>;
1319                 #pwm-cells = <3>;
1320                 pinctrl-names = "default";
1321                 pinctrl-0 = <&pwm0_pin>;
1322                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1323                 status = "disabled";
1324         };
1325
1326         pwm1: pwm@ff420010 {
1327                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1328                 reg = <0x0 0xff420010 0x0 0x10>;
1329                 #pwm-cells = <3>;
1330                 pinctrl-names = "default";
1331                 pinctrl-0 = <&pwm1_pin>;
1332                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1333                 status = "disabled";
1334         };
1335
1336         pwm2: pwm@ff420020 {
1337                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1338                 reg = <0x0 0xff420020 0x0 0x10>;
1339                 #pwm-cells = <3>;
1340                 pinctrl-names = "default";
1341                 pinctrl-0 = <&pwm2_pin>;
1342                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1343                 status = "disabled";
1344         };
1345
1346         pwm3: pwm@ff420030 {
1347                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1348                 reg = <0x0 0xff420030 0x0 0x10>;
1349                 #pwm-cells = <3>;
1350                 pinctrl-names = "default";
1351                 pinctrl-0 = <&pwm3a_pin>;
1352                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1353                 status = "disabled";
1354         };
1355
1356         dfi: dfi@ff630000 {
1357                 reg = <0x00 0xff630000 0x00 0x4000>;
1358                 compatible = "rockchip,rk3399-dfi";
1359                 rockchip,pmu = <&pmugrf>;
1360                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1361                 clocks = <&cru PCLK_DDR_MON>;
1362                 clock-names = "pclk_ddr_mon";
1363         };
1364
1365         vpu: video-codec@ff650000 {
1366                 compatible = "rockchip,rk3399-vpu";
1367                 reg = <0x0 0xff650000 0x0 0x800>;
1368                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1369                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1370                 interrupt-names = "vepu", "vdpu";
1371                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1372                 clock-names = "aclk", "hclk";
1373                 iommus = <&vpu_mmu>;
1374                 power-domains = <&power RK3399_PD_VCODEC>;
1375         };
1376
1377         vpu_mmu: iommu@ff650800 {
1378                 compatible = "rockchip,iommu";
1379                 reg = <0x0 0xff650800 0x0 0x40>;
1380                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1381                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1382                 clock-names = "aclk", "iface";
1383                 #iommu-cells = <0>;
1384                 power-domains = <&power RK3399_PD_VCODEC>;
1385         };
1386
1387         vdec: video-codec@ff660000 {
1388                 compatible = "rockchip,rk3399-vdec";
1389                 reg = <0x0 0xff660000 0x0 0x480>;
1390                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1391                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1392                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1393                 clock-names = "axi", "ahb", "cabac", "core";
1394                 iommus = <&vdec_mmu>;
1395                 power-domains = <&power RK3399_PD_VDU>;
1396         };
1397
1398         vdec_mmu: iommu@ff660480 {
1399                 compatible = "rockchip,iommu";
1400                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1401                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1402                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1403                 clock-names = "aclk", "iface";
1404                 power-domains = <&power RK3399_PD_VDU>;
1405                 #iommu-cells = <0>;
1406         };
1407
1408         iep_mmu: iommu@ff670800 {
1409                 compatible = "rockchip,iommu";
1410                 reg = <0x0 0xff670800 0x0 0x40>;
1411                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1412                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1413                 clock-names = "aclk", "iface";
1414                 #iommu-cells = <0>;
1415                 status = "disabled";
1416         };
1417
1418         rga: rga@ff680000 {
1419                 compatible = "rockchip,rk3399-rga";
1420                 reg = <0x0 0xff680000 0x0 0x10000>;
1421                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1422                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1423                 clock-names = "aclk", "hclk", "sclk";
1424                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1425                 reset-names = "core", "axi", "ahb";
1426                 power-domains = <&power RK3399_PD_RGA>;
1427         };
1428
1429         efuse0: efuse@ff690000 {
1430                 compatible = "rockchip,rk3399-efuse";
1431                 reg = <0x0 0xff690000 0x0 0x80>;
1432                 #address-cells = <1>;
1433                 #size-cells = <1>;
1434                 clocks = <&cru PCLK_EFUSE1024NS>;
1435                 clock-names = "pclk_efuse";
1436
1437                 /* Data cells */
1438                 cpu_id: cpu-id@7 {
1439                         reg = <0x07 0x10>;
1440                 };
1441                 cpub_leakage: cpu-leakage@17 {
1442                         reg = <0x17 0x1>;
1443                 };
1444                 gpu_leakage: gpu-leakage@18 {
1445                         reg = <0x18 0x1>;
1446                 };
1447                 center_leakage: center-leakage@19 {
1448                         reg = <0x19 0x1>;
1449                 };
1450                 cpul_leakage: cpu-leakage@1a {
1451                         reg = <0x1a 0x1>;
1452                 };
1453                 logic_leakage: logic-leakage@1b {
1454                         reg = <0x1b 0x1>;
1455                 };
1456                 wafer_info: wafer-info@1c {
1457                         reg = <0x1c 0x1>;
1458                 };
1459         };
1460
1461         dmac_bus: dma-controller@ff6d0000 {
1462                 compatible = "arm,pl330", "arm,primecell";
1463                 reg = <0x0 0xff6d0000 0x0 0x4000>;
1464                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1465                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1466                 #dma-cells = <1>;
1467                 arm,pl330-periph-burst;
1468                 clocks = <&cru ACLK_DMAC0_PERILP>;
1469                 clock-names = "apb_pclk";
1470         };
1471
1472         dmac_peri: dma-controller@ff6e0000 {
1473                 compatible = "arm,pl330", "arm,primecell";
1474                 reg = <0x0 0xff6e0000 0x0 0x4000>;
1475                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1476                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1477                 #dma-cells = <1>;
1478                 arm,pl330-periph-burst;
1479                 clocks = <&cru ACLK_DMAC1_PERILP>;
1480                 clock-names = "apb_pclk";
1481         };
1482
1483         pmucru: clock-controller@ff750000 {
1484                 compatible = "rockchip,rk3399-pmucru";
1485                 reg = <0x0 0xff750000 0x0 0x1000>;
1486                 clocks = <&xin24m>;
1487                 clock-names = "xin24m";
1488                 rockchip,grf = <&pmugrf>;
1489                 #clock-cells = <1>;
1490                 #reset-cells = <1>;
1491                 assigned-clocks = <&pmucru PLL_PPLL>;
1492                 assigned-clock-rates = <676000000>;
1493         };
1494
1495         cru: clock-controller@ff760000 {
1496                 compatible = "rockchip,rk3399-cru";
1497                 reg = <0x0 0xff760000 0x0 0x1000>;
1498                 clocks = <&xin24m>;
1499                 clock-names = "xin24m";
1500                 rockchip,grf = <&grf>;
1501                 #clock-cells = <1>;
1502                 #reset-cells = <1>;
1503                 assigned-clocks =
1504                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1505                         <&cru PLL_NPLL>,
1506                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1507                         <&cru PCLK_PERIHP>,
1508                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1509                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1510                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1511                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1512                         <&cru ACLK_GIC_PRE>,
1513                         <&cru PCLK_DDR>,
1514                         <&cru ACLK_VDU>;
1515                 assigned-clock-rates =
1516                          <594000000>,  <800000000>,
1517                         <1000000000>,
1518                          <150000000>,   <75000000>,
1519                           <37500000>,
1520                          <100000000>,  <100000000>,
1521                           <50000000>, <600000000>,
1522                          <100000000>,   <50000000>,
1523                          <400000000>, <400000000>,
1524                          <200000000>,
1525                          <200000000>,
1526                          <400000000>;
1527         };
1528
1529         grf: syscon@ff770000 {
1530                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1531                 reg = <0x0 0xff770000 0x0 0x10000>;
1532                 #address-cells = <1>;
1533                 #size-cells = <1>;
1534
1535                 io_domains: io-domains {
1536                         compatible = "rockchip,rk3399-io-voltage-domain";
1537                         status = "disabled";
1538                 };
1539
1540                 mipi_dphy_rx0: mipi-dphy-rx0 {
1541                         compatible = "rockchip,rk3399-mipi-dphy-rx0";
1542                         clocks = <&cru SCLK_MIPIDPHY_REF>,
1543                                  <&cru SCLK_DPHY_RX0_CFG>,
1544                                  <&cru PCLK_VIO_GRF>;
1545                         clock-names = "dphy-ref", "dphy-cfg", "grf";
1546                         power-domains = <&power RK3399_PD_VIO>;
1547                         #phy-cells = <0>;
1548                         status = "disabled";
1549                 };
1550
1551                 u2phy0: usb2phy@e450 {
1552                         compatible = "rockchip,rk3399-usb2phy";
1553                         reg = <0xe450 0x10>;
1554                         clocks = <&cru SCLK_USB2PHY0_REF>;
1555                         clock-names = "phyclk";
1556                         #clock-cells = <0>;
1557                         clock-output-names = "clk_usbphy0_480m";
1558                         status = "disabled";
1559
1560                         u2phy0_host: host-port {
1561                                 #phy-cells = <0>;
1562                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1563                                 interrupt-names = "linestate";
1564                                 status = "disabled";
1565                         };
1566
1567                         u2phy0_otg: otg-port {
1568                                 #phy-cells = <0>;
1569                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1570                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1571                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1572                                 interrupt-names = "otg-bvalid", "otg-id",
1573                                                   "linestate";
1574                                 status = "disabled";
1575                         };
1576                 };
1577
1578                 u2phy1: usb2phy@e460 {
1579                         compatible = "rockchip,rk3399-usb2phy";
1580                         reg = <0xe460 0x10>;
1581                         clocks = <&cru SCLK_USB2PHY1_REF>;
1582                         clock-names = "phyclk";
1583                         #clock-cells = <0>;
1584                         clock-output-names = "clk_usbphy1_480m";
1585                         status = "disabled";
1586
1587                         u2phy1_host: host-port {
1588                                 #phy-cells = <0>;
1589                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1590                                 interrupt-names = "linestate";
1591                                 status = "disabled";
1592                         };
1593
1594                         u2phy1_otg: otg-port {
1595                                 #phy-cells = <0>;
1596                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1597                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1598                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1599                                 interrupt-names = "otg-bvalid", "otg-id",
1600                                                   "linestate";
1601                                 status = "disabled";
1602                         };
1603                 };
1604
1605                 emmc_phy: phy@f780 {
1606                         compatible = "rockchip,rk3399-emmc-phy";
1607                         reg = <0xf780 0x24>;
1608                         clocks = <&sdhci>;
1609                         clock-names = "emmcclk";
1610                         drive-impedance-ohm = <50>;
1611                         #phy-cells = <0>;
1612                         status = "disabled";
1613                 };
1614
1615                 pcie_phy: pcie-phy {
1616                         compatible = "rockchip,rk3399-pcie-phy";
1617                         clocks = <&cru SCLK_PCIEPHY_REF>;
1618                         clock-names = "refclk";
1619                         #phy-cells = <1>;
1620                         resets = <&cru SRST_PCIEPHY>;
1621                         reset-names = "phy";
1622                         status = "disabled";
1623                 };
1624         };
1625
1626         tcphy0: phy@ff7c0000 {
1627                 compatible = "rockchip,rk3399-typec-phy";
1628                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1629                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1630                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1631                 clock-names = "tcpdcore", "tcpdphy-ref";
1632                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1633                 assigned-clock-rates = <50000000>;
1634                 power-domains = <&power RK3399_PD_TCPD0>;
1635                 resets = <&cru SRST_UPHY0>,
1636                          <&cru SRST_UPHY0_PIPE_L00>,
1637                          <&cru SRST_P_UPHY0_TCPHY>;
1638                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1639                 rockchip,grf = <&grf>;
1640                 status = "disabled";
1641
1642                 tcphy0_dp: dp-port {
1643                         #phy-cells = <0>;
1644                 };
1645
1646                 tcphy0_usb3: usb3-port {
1647                         #phy-cells = <0>;
1648                 };
1649         };
1650
1651         tcphy1: phy@ff800000 {
1652                 compatible = "rockchip,rk3399-typec-phy";
1653                 reg = <0x0 0xff800000 0x0 0x40000>;
1654                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1655                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1656                 clock-names = "tcpdcore", "tcpdphy-ref";
1657                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1658                 assigned-clock-rates = <50000000>;
1659                 power-domains = <&power RK3399_PD_TCPD1>;
1660                 resets = <&cru SRST_UPHY1>,
1661                          <&cru SRST_UPHY1_PIPE_L00>,
1662                          <&cru SRST_P_UPHY1_TCPHY>;
1663                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1664                 rockchip,grf = <&grf>;
1665                 status = "disabled";
1666
1667                 tcphy1_dp: dp-port {
1668                         #phy-cells = <0>;
1669                 };
1670
1671                 tcphy1_usb3: usb3-port {
1672                         #phy-cells = <0>;
1673                 };
1674         };
1675
1676         watchdog@ff848000 {
1677                 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1678                 reg = <0x0 0xff848000 0x0 0x100>;
1679                 clocks = <&cru PCLK_WDT>;
1680                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1681         };
1682
1683         rktimer: rktimer@ff850000 {
1684                 compatible = "rockchip,rk3399-timer";
1685                 reg = <0x0 0xff850000 0x0 0x1000>;
1686                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1687                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1688                 clock-names = "pclk", "timer";
1689         };
1690
1691         spdif: spdif@ff870000 {
1692                 compatible = "rockchip,rk3399-spdif";
1693                 reg = <0x0 0xff870000 0x0 0x1000>;
1694                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1695                 dmas = <&dmac_bus 7>;
1696                 dma-names = "tx";
1697                 clock-names = "mclk", "hclk";
1698                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1699                 pinctrl-names = "default";
1700                 pinctrl-0 = <&spdif_bus>;
1701                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1702                 #sound-dai-cells = <0>;
1703                 status = "disabled";
1704         };
1705
1706         i2s0: i2s@ff880000 {
1707                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1708                 reg = <0x0 0xff880000 0x0 0x1000>;
1709                 rockchip,grf = <&grf>;
1710                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1711                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1712                 dma-names = "tx", "rx";
1713                 clock-names = "i2s_clk", "i2s_hclk";
1714                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1715                 pinctrl-names = "bclk_on", "bclk_off";
1716                 pinctrl-0 = <&i2s0_8ch_bus>;
1717                 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1718                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1719                 #sound-dai-cells = <0>;
1720                 status = "disabled";
1721         };
1722
1723         i2s1: i2s@ff890000 {
1724                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1725                 reg = <0x0 0xff890000 0x0 0x1000>;
1726                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1727                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1728                 dma-names = "tx", "rx";
1729                 clock-names = "i2s_clk", "i2s_hclk";
1730                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1731                 pinctrl-names = "default";
1732                 pinctrl-0 = <&i2s1_2ch_bus>;
1733                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1734                 #sound-dai-cells = <0>;
1735                 status = "disabled";
1736         };
1737
1738         i2s2: i2s@ff8a0000 {
1739                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1740                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1741                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1742                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1743                 dma-names = "tx", "rx";
1744                 clock-names = "i2s_clk", "i2s_hclk";
1745                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1746                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1747                 #sound-dai-cells = <0>;
1748                 status = "disabled";
1749         };
1750
1751         vopl: vop@ff8f0000 {
1752                 compatible = "rockchip,rk3399-vop-lit";
1753                 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
1754                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1755                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1756                 assigned-clock-rates = <400000000>, <100000000>;
1757                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1758                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1759                 iommus = <&vopl_mmu>;
1760                 power-domains = <&power RK3399_PD_VOPL>;
1761                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1762                 reset-names = "axi", "ahb", "dclk";
1763                 status = "disabled";
1764
1765                 vopl_out: port {
1766                         #address-cells = <1>;
1767                         #size-cells = <0>;
1768
1769                         vopl_out_mipi: endpoint@0 {
1770                                 reg = <0>;
1771                                 remote-endpoint = <&mipi_in_vopl>;
1772                         };
1773
1774                         vopl_out_edp: endpoint@1 {
1775                                 reg = <1>;
1776                                 remote-endpoint = <&edp_in_vopl>;
1777                         };
1778
1779                         vopl_out_hdmi: endpoint@2 {
1780                                 reg = <2>;
1781                                 remote-endpoint = <&hdmi_in_vopl>;
1782                         };
1783
1784                         vopl_out_mipi1: endpoint@3 {
1785                                 reg = <3>;
1786                                 remote-endpoint = <&mipi1_in_vopl>;
1787                         };
1788
1789                         vopl_out_dp: endpoint@4 {
1790                                 reg = <4>;
1791                                 remote-endpoint = <&dp_in_vopl>;
1792                         };
1793                 };
1794         };
1795
1796         vopl_mmu: iommu@ff8f3f00 {
1797                 compatible = "rockchip,iommu";
1798                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1799                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1800                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1801                 clock-names = "aclk", "iface";
1802                 power-domains = <&power RK3399_PD_VOPL>;
1803                 #iommu-cells = <0>;
1804                 status = "disabled";
1805         };
1806
1807         vopb: vop@ff900000 {
1808                 compatible = "rockchip,rk3399-vop-big";
1809                 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
1810                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1811                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1812                 assigned-clock-rates = <400000000>, <100000000>;
1813                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1814                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1815                 iommus = <&vopb_mmu>;
1816                 power-domains = <&power RK3399_PD_VOPB>;
1817                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1818                 reset-names = "axi", "ahb", "dclk";
1819                 status = "disabled";
1820
1821                 vopb_out: port {
1822                         #address-cells = <1>;
1823                         #size-cells = <0>;
1824
1825                         vopb_out_edp: endpoint@0 {
1826                                 reg = <0>;
1827                                 remote-endpoint = <&edp_in_vopb>;
1828                         };
1829
1830                         vopb_out_mipi: endpoint@1 {
1831                                 reg = <1>;
1832                                 remote-endpoint = <&mipi_in_vopb>;
1833                         };
1834
1835                         vopb_out_hdmi: endpoint@2 {
1836                                 reg = <2>;
1837                                 remote-endpoint = <&hdmi_in_vopb>;
1838                         };
1839
1840                         vopb_out_mipi1: endpoint@3 {
1841                                 reg = <3>;
1842                                 remote-endpoint = <&mipi1_in_vopb>;
1843                         };
1844
1845                         vopb_out_dp: endpoint@4 {
1846                                 reg = <4>;
1847                                 remote-endpoint = <&dp_in_vopb>;
1848                         };
1849                 };
1850         };
1851
1852         vopb_mmu: iommu@ff903f00 {
1853                 compatible = "rockchip,iommu";
1854                 reg = <0x0 0xff903f00 0x0 0x100>;
1855                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1856                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1857                 clock-names = "aclk", "iface";
1858                 power-domains = <&power RK3399_PD_VOPB>;
1859                 #iommu-cells = <0>;
1860                 status = "disabled";
1861         };
1862
1863         isp0: isp0@ff910000 {
1864                 compatible = "rockchip,rk3399-cif-isp";
1865                 reg = <0x0 0xff910000 0x0 0x4000>;
1866                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1867                 clocks = <&cru SCLK_ISP0>,
1868                          <&cru ACLK_ISP0_WRAPPER>,
1869                          <&cru HCLK_ISP0_WRAPPER>;
1870                 clock-names = "isp", "aclk", "hclk";
1871                 iommus = <&isp0_mmu>;
1872                 phys = <&mipi_dphy_rx0>;
1873                 phy-names = "dphy";
1874                 power-domains = <&power RK3399_PD_ISP0>;
1875                 status = "disabled";
1876
1877                 ports {
1878                         #address-cells = <1>;
1879                         #size-cells = <0>;
1880
1881                         port@0 {
1882                                 reg = <0>;
1883                                 #address-cells = <1>;
1884                                 #size-cells = <0>;
1885                         };
1886                 };
1887         };
1888
1889         isp0_mmu: iommu@ff914000 {
1890                 compatible = "rockchip,iommu";
1891                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1892                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1893                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1894                 clock-names = "aclk", "iface";
1895                 #iommu-cells = <0>;
1896                 power-domains = <&power RK3399_PD_ISP0>;
1897                 rockchip,disable-mmu-reset;
1898         };
1899
1900         isp1: isp1@ff920000 {
1901                 compatible = "rockchip,rk3399-cif-isp";
1902                 reg = <0x0 0xff920000 0x0 0x4000>;
1903                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1904                 clocks = <&cru SCLK_ISP1>,
1905                          <&cru ACLK_ISP1_WRAPPER>,
1906                          <&cru HCLK_ISP1_WRAPPER>;
1907                 clock-names = "isp", "aclk", "hclk";
1908                 iommus = <&isp1_mmu>;
1909                 phys = <&mipi_dsi1>;
1910                 phy-names = "dphy";
1911                 power-domains = <&power RK3399_PD_ISP1>;
1912                 status = "disabled";
1913
1914                 ports {
1915                         #address-cells = <1>;
1916                         #size-cells = <0>;
1917
1918                         port@0 {
1919                                 reg = <0>;
1920                                 #address-cells = <1>;
1921                                 #size-cells = <0>;
1922                         };
1923                 };
1924         };
1925
1926         isp1_mmu: iommu@ff924000 {
1927                 compatible = "rockchip,iommu";
1928                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1929                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1930                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1931                 clock-names = "aclk", "iface";
1932                 #iommu-cells = <0>;
1933                 power-domains = <&power RK3399_PD_ISP1>;
1934                 rockchip,disable-mmu-reset;
1935         };
1936
1937         hdmi_sound: hdmi-sound {
1938                 compatible = "simple-audio-card";
1939                 simple-audio-card,format = "i2s";
1940                 simple-audio-card,mclk-fs = <256>;
1941                 simple-audio-card,name = "hdmi-sound";
1942                 status = "disabled";
1943
1944                 simple-audio-card,cpu {
1945                         sound-dai = <&i2s2>;
1946                 };
1947                 simple-audio-card,codec {
1948                         sound-dai = <&hdmi>;
1949                 };
1950         };
1951
1952         hdmi: hdmi@ff940000 {
1953                 compatible = "rockchip,rk3399-dw-hdmi";
1954                 reg = <0x0 0xff940000 0x0 0x20000>;
1955                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1956                 clocks = <&cru PCLK_HDMI_CTRL>,
1957                          <&cru SCLK_HDMI_SFR>,
1958                          <&cru SCLK_HDMI_CEC>,
1959                          <&cru PCLK_VIO_GRF>,
1960                          <&cru PLL_VPLL>;
1961                 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1962                 power-domains = <&power RK3399_PD_HDCP>;
1963                 reg-io-width = <4>;
1964                 rockchip,grf = <&grf>;
1965                 #sound-dai-cells = <0>;
1966                 status = "disabled";
1967
1968                 ports {
1969                         hdmi_in: port {
1970                                 #address-cells = <1>;
1971                                 #size-cells = <0>;
1972
1973                                 hdmi_in_vopb: endpoint@0 {
1974                                         reg = <0>;
1975                                         remote-endpoint = <&vopb_out_hdmi>;
1976                                 };
1977                                 hdmi_in_vopl: endpoint@1 {
1978                                         reg = <1>;
1979                                         remote-endpoint = <&vopl_out_hdmi>;
1980                                 };
1981                         };
1982                 };
1983         };
1984
1985         mipi_dsi: dsi@ff960000 {
1986                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1987                 reg = <0x0 0xff960000 0x0 0x8000>;
1988                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1989                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1990                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1991                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1992                 power-domains = <&power RK3399_PD_VIO>;
1993                 resets = <&cru SRST_P_MIPI_DSI0>;
1994                 reset-names = "apb";
1995                 rockchip,grf = <&grf>;
1996                 #address-cells = <1>;
1997                 #size-cells = <0>;
1998                 status = "disabled";
1999
2000                 ports {
2001                         #address-cells = <1>;
2002                         #size-cells = <0>;
2003
2004                         mipi_in: port@0 {
2005                                 reg = <0>;
2006                                 #address-cells = <1>;
2007                                 #size-cells = <0>;
2008
2009                                 mipi_in_vopb: endpoint@0 {
2010                                         reg = <0>;
2011                                         remote-endpoint = <&vopb_out_mipi>;
2012                                 };
2013
2014                                 mipi_in_vopl: endpoint@1 {
2015                                         reg = <1>;
2016                                         remote-endpoint = <&vopl_out_mipi>;
2017                                 };
2018                         };
2019
2020                         mipi_out: port@1 {
2021                                 reg = <1>;
2022                         };
2023                 };
2024         };
2025
2026         mipi_dsi1: dsi@ff968000 {
2027                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2028                 reg = <0x0 0xff968000 0x0 0x8000>;
2029                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
2030                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2031                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
2032                 clock-names = "ref", "pclk", "phy_cfg", "grf";
2033                 power-domains = <&power RK3399_PD_VIO>;
2034                 resets = <&cru SRST_P_MIPI_DSI1>;
2035                 reset-names = "apb";
2036                 rockchip,grf = <&grf>;
2037                 #address-cells = <1>;
2038                 #size-cells = <0>;
2039                 #phy-cells = <0>;
2040                 status = "disabled";
2041
2042                 ports {
2043                         #address-cells = <1>;
2044                         #size-cells = <0>;
2045
2046                         mipi1_in: port@0 {
2047                                 reg = <0>;
2048                                 #address-cells = <1>;
2049                                 #size-cells = <0>;
2050
2051                                 mipi1_in_vopb: endpoint@0 {
2052                                         reg = <0>;
2053                                         remote-endpoint = <&vopb_out_mipi1>;
2054                                 };
2055
2056                                 mipi1_in_vopl: endpoint@1 {
2057                                         reg = <1>;
2058                                         remote-endpoint = <&vopl_out_mipi1>;
2059                                 };
2060                         };
2061
2062                         mipi1_out: port@1 {
2063                                 reg = <1>;
2064                         };
2065                 };
2066         };
2067
2068         edp: dp@ff970000 {
2069                 compatible = "rockchip,rk3399-edp";
2070                 reg = <0x0 0xff970000 0x0 0x8000>;
2071                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
2072                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2073                 clock-names = "dp", "pclk", "grf";
2074                 pinctrl-names = "default";
2075                 pinctrl-0 = <&edp_hpd>;
2076                 power-domains = <&power RK3399_PD_EDP>;
2077                 resets = <&cru SRST_P_EDP_CTRL>;
2078                 reset-names = "dp";
2079                 rockchip,grf = <&grf>;
2080                 status = "disabled";
2081
2082                 ports {
2083                         #address-cells = <1>;
2084                         #size-cells = <0>;
2085
2086                         edp_in: port@0 {
2087                                 reg = <0>;
2088                                 #address-cells = <1>;
2089                                 #size-cells = <0>;
2090
2091                                 edp_in_vopb: endpoint@0 {
2092                                         reg = <0>;
2093                                         remote-endpoint = <&vopb_out_edp>;
2094                                 };
2095
2096                                 edp_in_vopl: endpoint@1 {
2097                                         reg = <1>;
2098                                         remote-endpoint = <&vopl_out_edp>;
2099                                 };
2100                         };
2101
2102                         edp_out: port@1 {
2103                                 reg = <1>;
2104                         };
2105                 };
2106         };
2107
2108         gpu: gpu@ff9a0000 {
2109                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2110                 reg = <0x0 0xff9a0000 0x0 0x10000>;
2111                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
2112                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
2113                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
2114                 interrupt-names = "job", "mmu", "gpu";
2115                 clocks = <&cru ACLK_GPU>;
2116                 #cooling-cells = <2>;
2117                 power-domains = <&power RK3399_PD_GPU>;
2118                 status = "disabled";
2119         };
2120
2121         pinctrl: pinctrl {
2122                 compatible = "rockchip,rk3399-pinctrl";
2123                 rockchip,grf = <&grf>;
2124                 rockchip,pmu = <&pmugrf>;
2125                 #address-cells = <2>;
2126                 #size-cells = <2>;
2127                 ranges;
2128
2129                 gpio0: gpio@ff720000 {
2130                         compatible = "rockchip,gpio-bank";
2131                         reg = <0x0 0xff720000 0x0 0x100>;
2132                         clocks = <&pmucru PCLK_GPIO0_PMU>;
2133                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2134
2135                         gpio-controller;
2136                         #gpio-cells = <0x2>;
2137
2138                         interrupt-controller;
2139                         #interrupt-cells = <0x2>;
2140                 };
2141
2142                 gpio1: gpio@ff730000 {
2143                         compatible = "rockchip,gpio-bank";
2144                         reg = <0x0 0xff730000 0x0 0x100>;
2145                         clocks = <&pmucru PCLK_GPIO1_PMU>;
2146                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2147
2148                         gpio-controller;
2149                         #gpio-cells = <0x2>;
2150
2151                         interrupt-controller;
2152                         #interrupt-cells = <0x2>;
2153                 };
2154
2155                 gpio2: gpio@ff780000 {
2156                         compatible = "rockchip,gpio-bank";
2157                         reg = <0x0 0xff780000 0x0 0x100>;
2158                         clocks = <&cru PCLK_GPIO2>;
2159                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2160
2161                         gpio-controller;
2162                         #gpio-cells = <0x2>;
2163
2164                         interrupt-controller;
2165                         #interrupt-cells = <0x2>;
2166                 };
2167
2168                 gpio3: gpio@ff788000 {
2169                         compatible = "rockchip,gpio-bank";
2170                         reg = <0x0 0xff788000 0x0 0x100>;
2171                         clocks = <&cru PCLK_GPIO3>;
2172                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2173
2174                         gpio-controller;
2175                         #gpio-cells = <0x2>;
2176
2177                         interrupt-controller;
2178                         #interrupt-cells = <0x2>;
2179                 };
2180
2181                 gpio4: gpio@ff790000 {
2182                         compatible = "rockchip,gpio-bank";
2183                         reg = <0x0 0xff790000 0x0 0x100>;
2184                         clocks = <&cru PCLK_GPIO4>;
2185                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2186
2187                         gpio-controller;
2188                         #gpio-cells = <0x2>;
2189
2190                         interrupt-controller;
2191                         #interrupt-cells = <0x2>;
2192                 };
2193
2194                 pcfg_pull_up: pcfg-pull-up {
2195                         bias-pull-up;
2196                 };
2197
2198                 pcfg_pull_down: pcfg-pull-down {
2199                         bias-pull-down;
2200                 };
2201
2202                 pcfg_pull_none: pcfg-pull-none {
2203                         bias-disable;
2204                 };
2205
2206                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2207                         bias-disable;
2208                         drive-strength = <12>;
2209                 };
2210
2211                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2212                         bias-disable;
2213                         drive-strength = <13>;
2214                 };
2215
2216                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2217                         bias-disable;
2218                         drive-strength = <18>;
2219                 };
2220
2221                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2222                         bias-disable;
2223                         drive-strength = <20>;
2224                 };
2225
2226                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2227                         bias-pull-up;
2228                         drive-strength = <2>;
2229                 };
2230
2231                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2232                         bias-pull-up;
2233                         drive-strength = <8>;
2234                 };
2235
2236                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2237                         bias-pull-up;
2238                         drive-strength = <18>;
2239                 };
2240
2241                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2242                         bias-pull-up;
2243                         drive-strength = <20>;
2244                 };
2245
2246                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2247                         bias-pull-down;
2248                         drive-strength = <4>;
2249                 };
2250
2251                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2252                         bias-pull-down;
2253                         drive-strength = <8>;
2254                 };
2255
2256                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2257                         bias-pull-down;
2258                         drive-strength = <12>;
2259                 };
2260
2261                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2262                         bias-pull-down;
2263                         drive-strength = <18>;
2264                 };
2265
2266                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2267                         bias-pull-down;
2268                         drive-strength = <20>;
2269                 };
2270
2271                 pcfg_output_high: pcfg-output-high {
2272                         output-high;
2273                 };
2274
2275                 pcfg_output_low: pcfg-output-low {
2276                         output-low;
2277                 };
2278
2279                 pcfg_input_enable: pcfg-input-enable {
2280                         input-enable;
2281                 };
2282
2283                 pcfg_input_pull_up: pcfg-input-pull-up {
2284                         input-enable;
2285                         bias-pull-up;
2286                 };
2287
2288                 pcfg_input_pull_down: pcfg-input-pull-down {
2289                         input-enable;
2290                         bias-pull-down;
2291                 };
2292
2293                 clock {
2294                         clk_32k: clk-32k {
2295                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2296                         };
2297                 };
2298
2299                 cif {
2300                         cif_clkin: cif-clkin {
2301                                 rockchip,pins =
2302                                         <2 RK_PB2 3 &pcfg_pull_none>;
2303                         };
2304
2305                         cif_clkouta: cif-clkouta {
2306                                 rockchip,pins =
2307                                         <2 RK_PB3 3 &pcfg_pull_none>;
2308                         };
2309                 };
2310
2311                 edp {
2312                         edp_hpd: edp-hpd {
2313                                 rockchip,pins =
2314                                         <4 RK_PC7 2 &pcfg_pull_none>;
2315                         };
2316                 };
2317
2318                 gmac {
2319                         rgmii_pins: rgmii-pins {
2320                                 rockchip,pins =
2321                                         /* mac_txclk */
2322                                         <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2323                                         /* mac_rxclk */
2324                                         <3 RK_PB6 1 &pcfg_pull_none>,
2325                                         /* mac_mdio */
2326                                         <3 RK_PB5 1 &pcfg_pull_none>,
2327                                         /* mac_txen */
2328                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2329                                         /* mac_clk */
2330                                         <3 RK_PB3 1 &pcfg_pull_none>,
2331                                         /* mac_rxdv */
2332                                         <3 RK_PB1 1 &pcfg_pull_none>,
2333                                         /* mac_mdc */
2334                                         <3 RK_PB0 1 &pcfg_pull_none>,
2335                                         /* mac_rxd1 */
2336                                         <3 RK_PA7 1 &pcfg_pull_none>,
2337                                         /* mac_rxd0 */
2338                                         <3 RK_PA6 1 &pcfg_pull_none>,
2339                                         /* mac_txd1 */
2340                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2341                                         /* mac_txd0 */
2342                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2343                                         /* mac_rxd3 */
2344                                         <3 RK_PA3 1 &pcfg_pull_none>,
2345                                         /* mac_rxd2 */
2346                                         <3 RK_PA2 1 &pcfg_pull_none>,
2347                                         /* mac_txd3 */
2348                                         <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2349                                         /* mac_txd2 */
2350                                         <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2351                         };
2352
2353                         rmii_pins: rmii-pins {
2354                                 rockchip,pins =
2355                                         /* mac_mdio */
2356                                         <3 RK_PB5 1 &pcfg_pull_none>,
2357                                         /* mac_txen */
2358                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2359                                         /* mac_clk */
2360                                         <3 RK_PB3 1 &pcfg_pull_none>,
2361                                         /* mac_rxer */
2362                                         <3 RK_PB2 1 &pcfg_pull_none>,
2363                                         /* mac_rxdv */
2364                                         <3 RK_PB1 1 &pcfg_pull_none>,
2365                                         /* mac_mdc */
2366                                         <3 RK_PB0 1 &pcfg_pull_none>,
2367                                         /* mac_rxd1 */
2368                                         <3 RK_PA7 1 &pcfg_pull_none>,
2369                                         /* mac_rxd0 */
2370                                         <3 RK_PA6 1 &pcfg_pull_none>,
2371                                         /* mac_txd1 */
2372                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2373                                         /* mac_txd0 */
2374                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2375                         };
2376                 };
2377
2378                 i2c0 {
2379                         i2c0_xfer: i2c0-xfer {
2380                                 rockchip,pins =
2381                                         <1 RK_PB7 2 &pcfg_pull_none>,
2382                                         <1 RK_PC0 2 &pcfg_pull_none>;
2383                         };
2384                 };
2385
2386                 i2c1 {
2387                         i2c1_xfer: i2c1-xfer {
2388                                 rockchip,pins =
2389                                         <4 RK_PA2 1 &pcfg_pull_none>,
2390                                         <4 RK_PA1 1 &pcfg_pull_none>;
2391                         };
2392                 };
2393
2394                 i2c2 {
2395                         i2c2_xfer: i2c2-xfer {
2396                                 rockchip,pins =
2397                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2398                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2399                         };
2400                 };
2401
2402                 i2c3 {
2403                         i2c3_xfer: i2c3-xfer {
2404                                 rockchip,pins =
2405                                         <4 RK_PC1 1 &pcfg_pull_none>,
2406                                         <4 RK_PC0 1 &pcfg_pull_none>;
2407                         };
2408                 };
2409
2410                 i2c4 {
2411                         i2c4_xfer: i2c4-xfer {
2412                                 rockchip,pins =
2413                                         <1 RK_PB4 1 &pcfg_pull_none>,
2414                                         <1 RK_PB3 1 &pcfg_pull_none>;
2415                         };
2416                 };
2417
2418                 i2c5 {
2419                         i2c5_xfer: i2c5-xfer {
2420                                 rockchip,pins =
2421                                         <3 RK_PB3 2 &pcfg_pull_none>,
2422                                         <3 RK_PB2 2 &pcfg_pull_none>;
2423                         };
2424                 };
2425
2426                 i2c6 {
2427                         i2c6_xfer: i2c6-xfer {
2428                                 rockchip,pins =
2429                                         <2 RK_PB2 2 &pcfg_pull_none>,
2430                                         <2 RK_PB1 2 &pcfg_pull_none>;
2431                         };
2432                 };
2433
2434                 i2c7 {
2435                         i2c7_xfer: i2c7-xfer {
2436                                 rockchip,pins =
2437                                         <2 RK_PB0 2 &pcfg_pull_none>,
2438                                         <2 RK_PA7 2 &pcfg_pull_none>;
2439                         };
2440                 };
2441
2442                 i2c8 {
2443                         i2c8_xfer: i2c8-xfer {
2444                                 rockchip,pins =
2445                                         <1 RK_PC5 1 &pcfg_pull_none>,
2446                                         <1 RK_PC4 1 &pcfg_pull_none>;
2447                         };
2448                 };
2449
2450                 i2s0 {
2451                         i2s0_2ch_bus: i2s0-2ch-bus {
2452                                 rockchip,pins =
2453                                         <3 RK_PD0 1 &pcfg_pull_none>,
2454                                         <3 RK_PD1 1 &pcfg_pull_none>,
2455                                         <3 RK_PD2 1 &pcfg_pull_none>,
2456                                         <3 RK_PD3 1 &pcfg_pull_none>,
2457                                         <3 RK_PD7 1 &pcfg_pull_none>,
2458                                         <4 RK_PA0 1 &pcfg_pull_none>;
2459                         };
2460
2461                         i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2462                                 rockchip,pins =
2463                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
2464                                         <3 RK_PD1 1 &pcfg_pull_none>,
2465                                         <3 RK_PD2 1 &pcfg_pull_none>,
2466                                         <3 RK_PD3 1 &pcfg_pull_none>,
2467                                         <3 RK_PD7 1 &pcfg_pull_none>,
2468                                         <4 RK_PA0 1 &pcfg_pull_none>;
2469                         };
2470
2471                         i2s0_8ch_bus: i2s0-8ch-bus {
2472                                 rockchip,pins =
2473                                         <3 RK_PD0 1 &pcfg_pull_none>,
2474                                         <3 RK_PD1 1 &pcfg_pull_none>,
2475                                         <3 RK_PD2 1 &pcfg_pull_none>,
2476                                         <3 RK_PD3 1 &pcfg_pull_none>,
2477                                         <3 RK_PD4 1 &pcfg_pull_none>,
2478                                         <3 RK_PD5 1 &pcfg_pull_none>,
2479                                         <3 RK_PD6 1 &pcfg_pull_none>,
2480                                         <3 RK_PD7 1 &pcfg_pull_none>,
2481                                         <4 RK_PA0 1 &pcfg_pull_none>;
2482                         };
2483
2484                         i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2485                                 rockchip,pins =
2486                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
2487                                         <3 RK_PD1 1 &pcfg_pull_none>,
2488                                         <3 RK_PD2 1 &pcfg_pull_none>,
2489                                         <3 RK_PD3 1 &pcfg_pull_none>,
2490                                         <3 RK_PD4 1 &pcfg_pull_none>,
2491                                         <3 RK_PD5 1 &pcfg_pull_none>,
2492                                         <3 RK_PD6 1 &pcfg_pull_none>,
2493                                         <3 RK_PD7 1 &pcfg_pull_none>,
2494                                         <4 RK_PA0 1 &pcfg_pull_none>;
2495                         };
2496                 };
2497
2498                 i2s1 {
2499                         i2s1_2ch_bus: i2s1-2ch-bus {
2500                                 rockchip,pins =
2501                                         <4 RK_PA3 1 &pcfg_pull_none>,
2502                                         <4 RK_PA4 1 &pcfg_pull_none>,
2503                                         <4 RK_PA5 1 &pcfg_pull_none>,
2504                                         <4 RK_PA6 1 &pcfg_pull_none>,
2505                                         <4 RK_PA7 1 &pcfg_pull_none>;
2506                         };
2507
2508                         i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2509                                 rockchip,pins =
2510                                         <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
2511                                         <4 RK_PA4 1 &pcfg_pull_none>,
2512                                         <4 RK_PA5 1 &pcfg_pull_none>,
2513                                         <4 RK_PA6 1 &pcfg_pull_none>,
2514                                         <4 RK_PA7 1 &pcfg_pull_none>;
2515                         };
2516                 };
2517
2518                 sdio0 {
2519                         sdio0_bus1: sdio0-bus1 {
2520                                 rockchip,pins =
2521                                         <2 RK_PC4 1 &pcfg_pull_up>;
2522                         };
2523
2524                         sdio0_bus4: sdio0-bus4 {
2525                                 rockchip,pins =
2526                                         <2 RK_PC4 1 &pcfg_pull_up>,
2527                                         <2 RK_PC5 1 &pcfg_pull_up>,
2528                                         <2 RK_PC6 1 &pcfg_pull_up>,
2529                                         <2 RK_PC7 1 &pcfg_pull_up>;
2530                         };
2531
2532                         sdio0_cmd: sdio0-cmd {
2533                                 rockchip,pins =
2534                                         <2 RK_PD0 1 &pcfg_pull_up>;
2535                         };
2536
2537                         sdio0_clk: sdio0-clk {
2538                                 rockchip,pins =
2539                                         <2 RK_PD1 1 &pcfg_pull_none>;
2540                         };
2541
2542                         sdio0_cd: sdio0-cd {
2543                                 rockchip,pins =
2544                                         <2 RK_PD2 1 &pcfg_pull_up>;
2545                         };
2546
2547                         sdio0_pwr: sdio0-pwr {
2548                                 rockchip,pins =
2549                                         <2 RK_PD3 1 &pcfg_pull_up>;
2550                         };
2551
2552                         sdio0_bkpwr: sdio0-bkpwr {
2553                                 rockchip,pins =
2554                                         <2 RK_PD4 1 &pcfg_pull_up>;
2555                         };
2556
2557                         sdio0_wp: sdio0-wp {
2558                                 rockchip,pins =
2559                                         <0 RK_PA3 1 &pcfg_pull_up>;
2560                         };
2561
2562                         sdio0_int: sdio0-int {
2563                                 rockchip,pins =
2564                                         <0 RK_PA4 1 &pcfg_pull_up>;
2565                         };
2566                 };
2567
2568                 sdmmc {
2569                         sdmmc_bus1: sdmmc-bus1 {
2570                                 rockchip,pins =
2571                                         <4 RK_PB0 1 &pcfg_pull_up>;
2572                         };
2573
2574                         sdmmc_bus4: sdmmc-bus4 {
2575                                 rockchip,pins =
2576                                         <4 RK_PB0 1 &pcfg_pull_up>,
2577                                         <4 RK_PB1 1 &pcfg_pull_up>,
2578                                         <4 RK_PB2 1 &pcfg_pull_up>,
2579                                         <4 RK_PB3 1 &pcfg_pull_up>;
2580                         };
2581
2582                         sdmmc_clk: sdmmc-clk {
2583                                 rockchip,pins =
2584                                         <4 RK_PB4 1 &pcfg_pull_none>;
2585                         };
2586
2587                         sdmmc_cmd: sdmmc-cmd {
2588                                 rockchip,pins =
2589                                         <4 RK_PB5 1 &pcfg_pull_up>;
2590                         };
2591
2592                         sdmmc_cd: sdmmc-cd {
2593                                 rockchip,pins =
2594                                         <0 RK_PA7 1 &pcfg_pull_up>;
2595                         };
2596
2597                         sdmmc_wp: sdmmc-wp {
2598                                 rockchip,pins =
2599                                         <0 RK_PB0 1 &pcfg_pull_up>;
2600                         };
2601                 };
2602
2603                 suspend {
2604                         ap_pwroff: ap-pwroff {
2605                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2606                         };
2607
2608                         ddrio_pwroff: ddrio-pwroff {
2609                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2610                         };
2611                 };
2612
2613                 spdif {
2614                         spdif_bus: spdif-bus {
2615                                 rockchip,pins =
2616                                         <4 RK_PC5 1 &pcfg_pull_none>;
2617                         };
2618
2619                         spdif_bus_1: spdif-bus-1 {
2620                                 rockchip,pins =
2621                                         <3 RK_PC0 3 &pcfg_pull_none>;
2622                         };
2623                 };
2624
2625                 spi0 {
2626                         spi0_clk: spi0-clk {
2627                                 rockchip,pins =
2628                                         <3 RK_PA6 2 &pcfg_pull_up>;
2629                         };
2630                         spi0_cs0: spi0-cs0 {
2631                                 rockchip,pins =
2632                                         <3 RK_PA7 2 &pcfg_pull_up>;
2633                         };
2634                         spi0_cs1: spi0-cs1 {
2635                                 rockchip,pins =
2636                                         <3 RK_PB0 2 &pcfg_pull_up>;
2637                         };
2638                         spi0_tx: spi0-tx {
2639                                 rockchip,pins =
2640                                         <3 RK_PA5 2 &pcfg_pull_up>;
2641                         };
2642                         spi0_rx: spi0-rx {
2643                                 rockchip,pins =
2644                                         <3 RK_PA4 2 &pcfg_pull_up>;
2645                         };
2646                 };
2647
2648                 spi1 {
2649                         spi1_clk: spi1-clk {
2650                                 rockchip,pins =
2651                                         <1 RK_PB1 2 &pcfg_pull_up>;
2652                         };
2653                         spi1_cs0: spi1-cs0 {
2654                                 rockchip,pins =
2655                                         <1 RK_PB2 2 &pcfg_pull_up>;
2656                         };
2657                         spi1_rx: spi1-rx {
2658                                 rockchip,pins =
2659                                         <1 RK_PA7 2 &pcfg_pull_up>;
2660                         };
2661                         spi1_tx: spi1-tx {
2662                                 rockchip,pins =
2663                                         <1 RK_PB0 2 &pcfg_pull_up>;
2664                         };
2665                 };
2666
2667                 spi2 {
2668                         spi2_clk: spi2-clk {
2669                                 rockchip,pins =
2670                                         <2 RK_PB3 1 &pcfg_pull_up>;
2671                         };
2672                         spi2_cs0: spi2-cs0 {
2673                                 rockchip,pins =
2674                                         <2 RK_PB4 1 &pcfg_pull_up>;
2675                         };
2676                         spi2_rx: spi2-rx {
2677                                 rockchip,pins =
2678                                         <2 RK_PB1 1 &pcfg_pull_up>;
2679                         };
2680                         spi2_tx: spi2-tx {
2681                                 rockchip,pins =
2682                                         <2 RK_PB2 1 &pcfg_pull_up>;
2683                         };
2684                 };
2685
2686                 spi3 {
2687                         spi3_clk: spi3-clk {
2688                                 rockchip,pins =
2689                                         <1 RK_PC1 1 &pcfg_pull_up>;
2690                         };
2691                         spi3_cs0: spi3-cs0 {
2692                                 rockchip,pins =
2693                                         <1 RK_PC2 1 &pcfg_pull_up>;
2694                         };
2695                         spi3_rx: spi3-rx {
2696                                 rockchip,pins =
2697                                         <1 RK_PB7 1 &pcfg_pull_up>;
2698                         };
2699                         spi3_tx: spi3-tx {
2700                                 rockchip,pins =
2701                                         <1 RK_PC0 1 &pcfg_pull_up>;
2702                         };
2703                 };
2704
2705                 spi4 {
2706                         spi4_clk: spi4-clk {
2707                                 rockchip,pins =
2708                                         <3 RK_PA2 2 &pcfg_pull_up>;
2709                         };
2710                         spi4_cs0: spi4-cs0 {
2711                                 rockchip,pins =
2712                                         <3 RK_PA3 2 &pcfg_pull_up>;
2713                         };
2714                         spi4_rx: spi4-rx {
2715                                 rockchip,pins =
2716                                         <3 RK_PA0 2 &pcfg_pull_up>;
2717                         };
2718                         spi4_tx: spi4-tx {
2719                                 rockchip,pins =
2720                                         <3 RK_PA1 2 &pcfg_pull_up>;
2721                         };
2722                 };
2723
2724                 spi5 {
2725                         spi5_clk: spi5-clk {
2726                                 rockchip,pins =
2727                                         <2 RK_PC6 2 &pcfg_pull_up>;
2728                         };
2729                         spi5_cs0: spi5-cs0 {
2730                                 rockchip,pins =
2731                                         <2 RK_PC7 2 &pcfg_pull_up>;
2732                         };
2733                         spi5_rx: spi5-rx {
2734                                 rockchip,pins =
2735                                         <2 RK_PC4 2 &pcfg_pull_up>;
2736                         };
2737                         spi5_tx: spi5-tx {
2738                                 rockchip,pins =
2739                                         <2 RK_PC5 2 &pcfg_pull_up>;
2740                         };
2741                 };
2742
2743                 testclk {
2744                         test_clkout0: test-clkout0 {
2745                                 rockchip,pins =
2746                                         <0 RK_PA0 1 &pcfg_pull_none>;
2747                         };
2748
2749                         test_clkout1: test-clkout1 {
2750                                 rockchip,pins =
2751                                         <2 RK_PD1 2 &pcfg_pull_none>;
2752                         };
2753
2754                         test_clkout2: test-clkout2 {
2755                                 rockchip,pins =
2756                                         <0 RK_PB0 3 &pcfg_pull_none>;
2757                         };
2758                 };
2759
2760                 tsadc {
2761                         otp_pin: otp-pin {
2762                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2763                         };
2764
2765                         otp_out: otp-out {
2766                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2767                         };
2768                 };
2769
2770                 uart0 {
2771                         uart0_xfer: uart0-xfer {
2772                                 rockchip,pins =
2773                                         <2 RK_PC0 1 &pcfg_pull_up>,
2774                                         <2 RK_PC1 1 &pcfg_pull_none>;
2775                         };
2776
2777                         uart0_cts: uart0-cts {
2778                                 rockchip,pins =
2779                                         <2 RK_PC2 1 &pcfg_pull_none>;
2780                         };
2781
2782                         uart0_rts: uart0-rts {
2783                                 rockchip,pins =
2784                                         <2 RK_PC3 1 &pcfg_pull_none>;
2785                         };
2786                 };
2787
2788                 uart1 {
2789                         uart1_xfer: uart1-xfer {
2790                                 rockchip,pins =
2791                                         <3 RK_PB4 2 &pcfg_pull_up>,
2792                                         <3 RK_PB5 2 &pcfg_pull_none>;
2793                         };
2794                 };
2795
2796                 uart2a {
2797                         uart2a_xfer: uart2a-xfer {
2798                                 rockchip,pins =
2799                                         <4 RK_PB0 2 &pcfg_pull_up>,
2800                                         <4 RK_PB1 2 &pcfg_pull_none>;
2801                         };
2802                 };
2803
2804                 uart2b {
2805                         uart2b_xfer: uart2b-xfer {
2806                                 rockchip,pins =
2807                                         <4 RK_PC0 2 &pcfg_pull_up>,
2808                                         <4 RK_PC1 2 &pcfg_pull_none>;
2809                         };
2810                 };
2811
2812                 uart2c {
2813                         uart2c_xfer: uart2c-xfer {
2814                                 rockchip,pins =
2815                                         <4 RK_PC3 1 &pcfg_pull_up>,
2816                                         <4 RK_PC4 1 &pcfg_pull_none>;
2817                         };
2818                 };
2819
2820                 uart3 {
2821                         uart3_xfer: uart3-xfer {
2822                                 rockchip,pins =
2823                                         <3 RK_PB6 2 &pcfg_pull_up>,
2824                                         <3 RK_PB7 2 &pcfg_pull_none>;
2825                         };
2826
2827                         uart3_cts: uart3-cts {
2828                                 rockchip,pins =
2829                                         <3 RK_PC0 2 &pcfg_pull_none>;
2830                         };
2831
2832                         uart3_rts: uart3-rts {
2833                                 rockchip,pins =
2834                                         <3 RK_PC1 2 &pcfg_pull_none>;
2835                         };
2836                 };
2837
2838                 uart4 {
2839                         uart4_xfer: uart4-xfer {
2840                                 rockchip,pins =
2841                                         <1 RK_PA7 1 &pcfg_pull_up>,
2842                                         <1 RK_PB0 1 &pcfg_pull_none>;
2843                         };
2844                 };
2845
2846                 uarthdcp {
2847                         uarthdcp_xfer: uarthdcp-xfer {
2848                                 rockchip,pins =
2849                                         <4 RK_PC5 2 &pcfg_pull_up>,
2850                                         <4 RK_PC6 2 &pcfg_pull_none>;
2851                         };
2852                 };
2853
2854                 pwm0 {
2855                         pwm0_pin: pwm0-pin {
2856                                 rockchip,pins =
2857                                         <4 RK_PC2 1 &pcfg_pull_none>;
2858                         };
2859
2860                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2861                                 rockchip,pins =
2862                                         <4 RK_PC2 1 &pcfg_pull_down>;
2863                         };
2864
2865                         vop0_pwm_pin: vop0-pwm-pin {
2866                                 rockchip,pins =
2867                                         <4 RK_PC2 2 &pcfg_pull_none>;
2868                         };
2869
2870                         vop1_pwm_pin: vop1-pwm-pin {
2871                                 rockchip,pins =
2872                                         <4 RK_PC2 3 &pcfg_pull_none>;
2873                         };
2874                 };
2875
2876                 pwm1 {
2877                         pwm1_pin: pwm1-pin {
2878                                 rockchip,pins =
2879                                         <4 RK_PC6 1 &pcfg_pull_none>;
2880                         };
2881
2882                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2883                                 rockchip,pins =
2884                                         <4 RK_PC6 1 &pcfg_pull_down>;
2885                         };
2886                 };
2887
2888                 pwm2 {
2889                         pwm2_pin: pwm2-pin {
2890                                 rockchip,pins =
2891                                         <1 RK_PC3 1 &pcfg_pull_none>;
2892                         };
2893
2894                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2895                                 rockchip,pins =
2896                                         <1 RK_PC3 1 &pcfg_pull_down>;
2897                         };
2898                 };
2899
2900                 pwm3a {
2901                         pwm3a_pin: pwm3a-pin {
2902                                 rockchip,pins =
2903                                         <0 RK_PA6 1 &pcfg_pull_none>;
2904                         };
2905                 };
2906
2907                 pwm3b {
2908                         pwm3b_pin: pwm3b-pin {
2909                                 rockchip,pins =
2910                                         <1 RK_PB6 1 &pcfg_pull_none>;
2911                         };
2912                 };
2913
2914                 hdmi {
2915                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2916                                 rockchip,pins =
2917                                         <4 RK_PC1 3 &pcfg_pull_none>,
2918                                         <4 RK_PC0 3 &pcfg_pull_none>;
2919                         };
2920
2921                         hdmi_cec: hdmi-cec {
2922                                 rockchip,pins =
2923                                         <4 RK_PC7 1 &pcfg_pull_none>;
2924                         };
2925                 };
2926
2927                 pcie {
2928                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2929                                 rockchip,pins =
2930                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2931                         };
2932
2933                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2934                                 rockchip,pins =
2935                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2936                         };
2937                 };
2938
2939         };
2940 };