1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
75 clocks = <&cru ARMCLKL>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
87 clocks = <&cru ARMCLKL>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
99 clocks = <&cru ARMCLKL>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
111 clocks = <&cru ARMCLKL>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
123 clocks = <&cru ARMCLKB>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
129 #cooling-cells = <2>;
130 duration-us = <10000>;
131 exit-latency-us = <500>;
137 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
141 clocks = <&cru ARMCLKB>;
142 #cooling-cells = <2>; /* min followed by max */
143 dynamic-power-coefficient = <436>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
147 #cooling-cells = <2>;
148 duration-us = <10000>;
149 exit-latency-us = <500>;
154 entry-method = "psci";
156 CPU_SLEEP: cpu-sleep {
157 compatible = "arm,idle-state";
159 arm,psci-suspend-param = <0x0010000>;
160 entry-latency-us = <120>;
161 exit-latency-us = <250>;
162 min-residency-us = <900>;
165 CLUSTER_SLEEP: cluster-sleep {
166 compatible = "arm,idle-state";
168 arm,psci-suspend-param = <0x1010000>;
169 entry-latency-us = <400>;
170 exit-latency-us = <500>;
171 min-residency-us = <2000>;
177 compatible = "rockchip,display-subsystem";
178 ports = <&vopl_out>, <&vopb_out>;
181 dmc: memory-controller {
182 compatible = "rockchip,rk3399-dmc";
183 rockchip,pmu = <&pmugrf>;
184 devfreq-events = <&dfi>;
185 clocks = <&cru SCLK_DDRC>;
186 clock-names = "dmc_clk";
191 compatible = "arm,cortex-a53-pmu";
192 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
196 compatible = "arm,cortex-a72-pmu";
197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
201 compatible = "arm,psci-1.0";
206 compatible = "arm,armv8-timer";
207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
211 arm,no-tick-in-suspend;
215 compatible = "fixed-clock";
216 clock-frequency = <24000000>;
217 clock-output-names = "xin24m";
221 pcie0: pcie@f8000000 {
222 compatible = "rockchip,rk3399-pcie";
223 reg = <0x0 0xf8000000 0x0 0x2000000>,
224 <0x0 0xfd000000 0x0 0x1000000>;
225 reg-names = "axi-base", "apb-base";
227 #address-cells = <3>;
229 #interrupt-cells = <1>;
231 bus-range = <0x0 0x1f>;
232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
234 clock-names = "aclk", "aclk-perf",
236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
237 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
238 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
239 interrupt-names = "sys", "legacy", "client";
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
242 <0 0 0 2 &pcie0_intc 1>,
243 <0 0 0 3 &pcie0_intc 2>,
244 <0 0 0 4 &pcie0_intc 3>;
245 max-link-speed = <1>;
246 msi-map = <0x0 &its 0x0 0x1000>;
247 phys = <&pcie_phy 0>, <&pcie_phy 1>,
248 <&pcie_phy 2>, <&pcie_phy 3>;
249 phy-names = "pcie-phy-0", "pcie-phy-1",
250 "pcie-phy-2", "pcie-phy-3";
251 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
252 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
258 "pm", "pclk", "aclk";
261 pcie0_intc: interrupt-controller {
262 interrupt-controller;
263 #address-cells = <0>;
264 #interrupt-cells = <1>;
268 gmac: ethernet@fe300000 {
269 compatible = "rockchip,rk3399-gmac";
270 reg = <0x0 0xfe300000 0x0 0x10000>;
271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
272 interrupt-names = "macirq";
273 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
274 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
275 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
277 clock-names = "stmmaceth", "mac_clk_rx",
278 "mac_clk_tx", "clk_mac_ref",
279 "clk_mac_refout", "aclk_mac",
281 power-domains = <&power RK3399_PD_GMAC>;
282 resets = <&cru SRST_A_GMAC>;
283 reset-names = "stmmaceth";
284 rockchip,grf = <&grf>;
289 sdio0: mmc@fe310000 {
290 compatible = "rockchip,rk3399-dw-mshc",
291 "rockchip,rk3288-dw-mshc";
292 reg = <0x0 0xfe310000 0x0 0x4000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
294 max-frequency = <150000000>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
299 power-domains = <&power RK3399_PD_SDIOAUDIO>;
300 resets = <&cru SRST_SDIO0>;
301 reset-names = "reset";
305 sdmmc: mmc@fe320000 {
306 compatible = "rockchip,rk3399-dw-mshc",
307 "rockchip,rk3288-dw-mshc";
308 reg = <0x0 0xfe320000 0x0 0x4000>;
309 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
310 max-frequency = <150000000>;
311 assigned-clocks = <&cru HCLK_SD>;
312 assigned-clock-rates = <200000000>;
313 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
314 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
315 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
316 fifo-depth = <0x100>;
317 power-domains = <&power RK3399_PD_SD>;
318 resets = <&cru SRST_SDMMC>;
319 reset-names = "reset";
323 sdhci: mmc@fe330000 {
324 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
325 reg = <0x0 0xfe330000 0x0 0x10000>;
326 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
327 arasan,soc-ctl-syscon = <&grf>;
328 assigned-clocks = <&cru SCLK_EMMC>;
329 assigned-clock-rates = <200000000>;
330 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
331 clock-names = "clk_xin", "clk_ahb";
332 clock-output-names = "emmc_cardclock";
335 phy-names = "phy_arasan";
336 power-domains = <&power RK3399_PD_EMMC>;
341 usb_host0_ehci: usb@fe380000 {
342 compatible = "generic-ehci";
343 reg = <0x0 0xfe380000 0x0 0x20000>;
344 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
345 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
347 phys = <&u2phy0_host>;
352 usb_host0_ohci: usb@fe3a0000 {
353 compatible = "generic-ohci";
354 reg = <0x0 0xfe3a0000 0x0 0x20000>;
355 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
358 phys = <&u2phy0_host>;
363 usb_host1_ehci: usb@fe3c0000 {
364 compatible = "generic-ehci";
365 reg = <0x0 0xfe3c0000 0x0 0x20000>;
366 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
367 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
369 phys = <&u2phy1_host>;
374 usb_host1_ohci: usb@fe3e0000 {
375 compatible = "generic-ohci";
376 reg = <0x0 0xfe3e0000 0x0 0x20000>;
377 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
380 phys = <&u2phy1_host>;
386 compatible = "arm,coresight-cpu-debug", "arm,primecell";
387 reg = <0 0xfe430000 0 0x1000>;
388 clocks = <&cru PCLK_COREDBG_L>;
389 clock-names = "apb_pclk";
394 compatible = "arm,coresight-cpu-debug", "arm,primecell";
395 reg = <0 0xfe432000 0 0x1000>;
396 clocks = <&cru PCLK_COREDBG_L>;
397 clock-names = "apb_pclk";
402 compatible = "arm,coresight-cpu-debug", "arm,primecell";
403 reg = <0 0xfe434000 0 0x1000>;
404 clocks = <&cru PCLK_COREDBG_L>;
405 clock-names = "apb_pclk";
410 compatible = "arm,coresight-cpu-debug", "arm,primecell";
411 reg = <0 0xfe436000 0 0x1000>;
412 clocks = <&cru PCLK_COREDBG_L>;
413 clock-names = "apb_pclk";
418 compatible = "arm,coresight-cpu-debug", "arm,primecell";
419 reg = <0 0xfe610000 0 0x1000>;
420 clocks = <&cru PCLK_COREDBG_B>;
421 clock-names = "apb_pclk";
426 compatible = "arm,coresight-cpu-debug", "arm,primecell";
427 reg = <0 0xfe710000 0 0x1000>;
428 clocks = <&cru PCLK_COREDBG_B>;
429 clock-names = "apb_pclk";
433 usbdrd3_0: usb@fe800000 {
434 compatible = "rockchip,rk3399-dwc3";
435 #address-cells = <2>;
438 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
439 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
440 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
441 clock-names = "ref_clk", "suspend_clk",
442 "bus_clk", "aclk_usb3_rksoc_axi_perf",
443 "aclk_usb3", "grf_clk";
444 resets = <&cru SRST_A_USB3_OTG0>;
445 reset-names = "usb3-otg";
448 usbdrd_dwc3_0: usb@fe800000 {
449 compatible = "snps,dwc3";
450 reg = <0x0 0xfe800000 0x0 0x100000>;
451 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
452 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
453 <&cru SCLK_USB3OTG0_SUSPEND>;
454 clock-names = "ref", "bus_early", "suspend";
456 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
457 phy-names = "usb2-phy", "usb3-phy";
458 phy_type = "utmi_wide";
459 snps,dis_enblslpm_quirk;
460 snps,dis-u2-freeclk-exists-quirk;
461 snps,dis_u2_susphy_quirk;
462 snps,dis-del-phy-power-chg-quirk;
463 snps,dis-tx-ipgap-linecheck-quirk;
464 power-domains = <&power RK3399_PD_USB3>;
469 usbdrd3_1: usb@fe900000 {
470 compatible = "rockchip,rk3399-dwc3";
471 #address-cells = <2>;
474 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
475 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
476 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
477 clock-names = "ref_clk", "suspend_clk",
478 "bus_clk", "aclk_usb3_rksoc_axi_perf",
479 "aclk_usb3", "grf_clk";
480 resets = <&cru SRST_A_USB3_OTG1>;
481 reset-names = "usb3-otg";
484 usbdrd_dwc3_1: usb@fe900000 {
485 compatible = "snps,dwc3";
486 reg = <0x0 0xfe900000 0x0 0x100000>;
487 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
488 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
489 <&cru SCLK_USB3OTG1_SUSPEND>;
490 clock-names = "ref", "bus_early", "suspend";
492 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
493 phy-names = "usb2-phy", "usb3-phy";
494 phy_type = "utmi_wide";
495 snps,dis_enblslpm_quirk;
496 snps,dis-u2-freeclk-exists-quirk;
497 snps,dis_u2_susphy_quirk;
498 snps,dis-del-phy-power-chg-quirk;
499 snps,dis-tx-ipgap-linecheck-quirk;
500 power-domains = <&power RK3399_PD_USB3>;
505 cdn_dp: dp@fec00000 {
506 compatible = "rockchip,rk3399-cdn-dp";
507 reg = <0x0 0xfec00000 0x0 0x100000>;
508 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
509 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
510 assigned-clock-rates = <100000000>, <200000000>;
511 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
512 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
513 clock-names = "core-clk", "pclk", "spdif", "grf";
514 phys = <&tcphy0_dp>, <&tcphy1_dp>;
515 power-domains = <&power RK3399_PD_HDCP>;
516 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
517 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
518 reset-names = "spdif", "dptx", "apb", "core";
519 rockchip,grf = <&grf>;
520 #sound-dai-cells = <1>;
525 #address-cells = <1>;
528 dp_in_vopb: endpoint@0 {
530 remote-endpoint = <&vopb_out_dp>;
533 dp_in_vopl: endpoint@1 {
535 remote-endpoint = <&vopl_out_dp>;
541 gic: interrupt-controller@fee00000 {
542 compatible = "arm,gic-v3";
543 #interrupt-cells = <4>;
544 #address-cells = <2>;
547 interrupt-controller;
549 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
550 <0x0 0xfef00000 0 0xc0000>, /* GICR */
551 <0x0 0xfff00000 0 0x10000>, /* GICC */
552 <0x0 0xfff10000 0 0x10000>, /* GICH */
553 <0x0 0xfff20000 0 0x10000>; /* GICV */
554 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
555 its: interrupt-controller@fee20000 {
556 compatible = "arm,gic-v3-its";
559 reg = <0x0 0xfee20000 0x0 0x20000>;
563 ppi_cluster0: interrupt-partition-0 {
564 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
567 ppi_cluster1: interrupt-partition-1 {
568 affinity = <&cpu_b0 &cpu_b1>;
573 saradc: saradc@ff100000 {
574 compatible = "rockchip,rk3399-saradc";
575 reg = <0x0 0xff100000 0x0 0x100>;
576 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
577 #io-channel-cells = <1>;
578 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
579 clock-names = "saradc", "apb_pclk";
580 resets = <&cru SRST_P_SARADC>;
581 reset-names = "saradc-apb";
586 compatible = "rockchip,rk3399-i2c";
587 reg = <0x0 0xff110000 0x0 0x1000>;
588 assigned-clocks = <&cru SCLK_I2C1>;
589 assigned-clock-rates = <200000000>;
590 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>;
601 compatible = "rockchip,rk3399-i2c";
602 reg = <0x0 0xff120000 0x0 0x1000>;
603 assigned-clocks = <&cru SCLK_I2C2>;
604 assigned-clock-rates = <200000000>;
605 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
606 clock-names = "i2c", "pclk";
607 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c2_xfer>;
610 #address-cells = <1>;
616 compatible = "rockchip,rk3399-i2c";
617 reg = <0x0 0xff130000 0x0 0x1000>;
618 assigned-clocks = <&cru SCLK_I2C3>;
619 assigned-clock-rates = <200000000>;
620 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
621 clock-names = "i2c", "pclk";
622 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c3_xfer>;
625 #address-cells = <1>;
631 compatible = "rockchip,rk3399-i2c";
632 reg = <0x0 0xff140000 0x0 0x1000>;
633 assigned-clocks = <&cru SCLK_I2C5>;
634 assigned-clock-rates = <200000000>;
635 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
636 clock-names = "i2c", "pclk";
637 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&i2c5_xfer>;
640 #address-cells = <1>;
646 compatible = "rockchip,rk3399-i2c";
647 reg = <0x0 0xff150000 0x0 0x1000>;
648 assigned-clocks = <&cru SCLK_I2C6>;
649 assigned-clock-rates = <200000000>;
650 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
651 clock-names = "i2c", "pclk";
652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&i2c6_xfer>;
655 #address-cells = <1>;
661 compatible = "rockchip,rk3399-i2c";
662 reg = <0x0 0xff160000 0x0 0x1000>;
663 assigned-clocks = <&cru SCLK_I2C7>;
664 assigned-clock-rates = <200000000>;
665 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
666 clock-names = "i2c", "pclk";
667 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&i2c7_xfer>;
670 #address-cells = <1>;
675 uart0: serial@ff180000 {
676 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
677 reg = <0x0 0xff180000 0x0 0x100>;
678 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
679 clock-names = "baudclk", "apb_pclk";
680 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&uart0_xfer>;
688 uart1: serial@ff190000 {
689 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
690 reg = <0x0 0xff190000 0x0 0x100>;
691 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
692 clock-names = "baudclk", "apb_pclk";
693 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&uart1_xfer>;
701 uart2: serial@ff1a0000 {
702 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
703 reg = <0x0 0xff1a0000 0x0 0x100>;
704 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
705 clock-names = "baudclk", "apb_pclk";
706 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&uart2c_xfer>;
714 uart3: serial@ff1b0000 {
715 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
716 reg = <0x0 0xff1b0000 0x0 0x100>;
717 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
718 clock-names = "baudclk", "apb_pclk";
719 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&uart3_xfer>;
728 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
729 reg = <0x0 0xff1c0000 0x0 0x1000>;
730 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
731 clock-names = "spiclk", "apb_pclk";
732 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
733 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
734 dma-names = "tx", "rx";
735 pinctrl-names = "default";
736 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
737 #address-cells = <1>;
743 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
744 reg = <0x0 0xff1d0000 0x0 0x1000>;
745 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
746 clock-names = "spiclk", "apb_pclk";
747 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
748 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
749 dma-names = "tx", "rx";
750 pinctrl-names = "default";
751 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
752 #address-cells = <1>;
758 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
759 reg = <0x0 0xff1e0000 0x0 0x1000>;
760 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
761 clock-names = "spiclk", "apb_pclk";
762 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
763 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
764 dma-names = "tx", "rx";
765 pinctrl-names = "default";
766 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
767 #address-cells = <1>;
773 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
774 reg = <0x0 0xff1f0000 0x0 0x1000>;
775 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
776 clock-names = "spiclk", "apb_pclk";
777 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
778 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
779 dma-names = "tx", "rx";
780 pinctrl-names = "default";
781 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
782 #address-cells = <1>;
788 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
789 reg = <0x0 0xff200000 0x0 0x1000>;
790 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
791 clock-names = "spiclk", "apb_pclk";
792 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
793 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
794 dma-names = "tx", "rx";
795 pinctrl-names = "default";
796 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
797 power-domains = <&power RK3399_PD_SDIOAUDIO>;
798 #address-cells = <1>;
803 thermal_zones: thermal-zones {
804 cpu_thermal: cpu-thermal {
805 polling-delay-passive = <100>;
806 polling-delay = <1000>;
808 thermal-sensors = <&tsadc 0>;
811 cpu_alert0: cpu_alert0 {
812 temperature = <70000>;
816 cpu_alert1: cpu_alert1 {
817 temperature = <75000>;
822 temperature = <95000>;
830 trip = <&cpu_alert0>;
832 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
833 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
836 trip = <&cpu_alert1>;
838 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
839 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
840 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
841 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
842 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
843 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
848 gpu_thermal: gpu-thermal {
849 polling-delay-passive = <100>;
850 polling-delay = <1000>;
852 thermal-sensors = <&tsadc 1>;
855 gpu_alert0: gpu_alert0 {
856 temperature = <75000>;
861 temperature = <95000>;
869 trip = <&gpu_alert0>;
871 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
877 tsadc: tsadc@ff260000 {
878 compatible = "rockchip,rk3399-tsadc";
879 reg = <0x0 0xff260000 0x0 0x100>;
880 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
881 assigned-clocks = <&cru SCLK_TSADC>;
882 assigned-clock-rates = <750000>;
883 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
884 clock-names = "tsadc", "apb_pclk";
885 resets = <&cru SRST_TSADC>;
886 reset-names = "tsadc-apb";
887 rockchip,grf = <&grf>;
888 rockchip,hw-tshut-temp = <95000>;
889 pinctrl-names = "init", "default", "sleep";
890 pinctrl-0 = <&otp_pin>;
891 pinctrl-1 = <&otp_out>;
892 pinctrl-2 = <&otp_pin>;
893 #thermal-sensor-cells = <1>;
897 qos_emmc: qos@ffa58000 {
898 compatible = "rockchip,rk3399-qos", "syscon";
899 reg = <0x0 0xffa58000 0x0 0x20>;
902 qos_gmac: qos@ffa5c000 {
903 compatible = "rockchip,rk3399-qos", "syscon";
904 reg = <0x0 0xffa5c000 0x0 0x20>;
907 qos_pcie: qos@ffa60080 {
908 compatible = "rockchip,rk3399-qos", "syscon";
909 reg = <0x0 0xffa60080 0x0 0x20>;
912 qos_usb_host0: qos@ffa60100 {
913 compatible = "rockchip,rk3399-qos", "syscon";
914 reg = <0x0 0xffa60100 0x0 0x20>;
917 qos_usb_host1: qos@ffa60180 {
918 compatible = "rockchip,rk3399-qos", "syscon";
919 reg = <0x0 0xffa60180 0x0 0x20>;
922 qos_usb_otg0: qos@ffa70000 {
923 compatible = "rockchip,rk3399-qos", "syscon";
924 reg = <0x0 0xffa70000 0x0 0x20>;
927 qos_usb_otg1: qos@ffa70080 {
928 compatible = "rockchip,rk3399-qos", "syscon";
929 reg = <0x0 0xffa70080 0x0 0x20>;
932 qos_sd: qos@ffa74000 {
933 compatible = "rockchip,rk3399-qos", "syscon";
934 reg = <0x0 0xffa74000 0x0 0x20>;
937 qos_sdioaudio: qos@ffa76000 {
938 compatible = "rockchip,rk3399-qos", "syscon";
939 reg = <0x0 0xffa76000 0x0 0x20>;
942 qos_hdcp: qos@ffa90000 {
943 compatible = "rockchip,rk3399-qos", "syscon";
944 reg = <0x0 0xffa90000 0x0 0x20>;
947 qos_iep: qos@ffa98000 {
948 compatible = "rockchip,rk3399-qos", "syscon";
949 reg = <0x0 0xffa98000 0x0 0x20>;
952 qos_isp0_m0: qos@ffaa0000 {
953 compatible = "rockchip,rk3399-qos", "syscon";
954 reg = <0x0 0xffaa0000 0x0 0x20>;
957 qos_isp0_m1: qos@ffaa0080 {
958 compatible = "rockchip,rk3399-qos", "syscon";
959 reg = <0x0 0xffaa0080 0x0 0x20>;
962 qos_isp1_m0: qos@ffaa8000 {
963 compatible = "rockchip,rk3399-qos", "syscon";
964 reg = <0x0 0xffaa8000 0x0 0x20>;
967 qos_isp1_m1: qos@ffaa8080 {
968 compatible = "rockchip,rk3399-qos", "syscon";
969 reg = <0x0 0xffaa8080 0x0 0x20>;
972 qos_rga_r: qos@ffab0000 {
973 compatible = "rockchip,rk3399-qos", "syscon";
974 reg = <0x0 0xffab0000 0x0 0x20>;
977 qos_rga_w: qos@ffab0080 {
978 compatible = "rockchip,rk3399-qos", "syscon";
979 reg = <0x0 0xffab0080 0x0 0x20>;
982 qos_video_m0: qos@ffab8000 {
983 compatible = "rockchip,rk3399-qos", "syscon";
984 reg = <0x0 0xffab8000 0x0 0x20>;
987 qos_video_m1_r: qos@ffac0000 {
988 compatible = "rockchip,rk3399-qos", "syscon";
989 reg = <0x0 0xffac0000 0x0 0x20>;
992 qos_video_m1_w: qos@ffac0080 {
993 compatible = "rockchip,rk3399-qos", "syscon";
994 reg = <0x0 0xffac0080 0x0 0x20>;
997 qos_vop_big_r: qos@ffac8000 {
998 compatible = "rockchip,rk3399-qos", "syscon";
999 reg = <0x0 0xffac8000 0x0 0x20>;
1002 qos_vop_big_w: qos@ffac8080 {
1003 compatible = "rockchip,rk3399-qos", "syscon";
1004 reg = <0x0 0xffac8080 0x0 0x20>;
1007 qos_vop_little: qos@ffad0000 {
1008 compatible = "rockchip,rk3399-qos", "syscon";
1009 reg = <0x0 0xffad0000 0x0 0x20>;
1012 qos_perihp: qos@ffad8080 {
1013 compatible = "rockchip,rk3399-qos", "syscon";
1014 reg = <0x0 0xffad8080 0x0 0x20>;
1017 qos_gpu: qos@ffae0000 {
1018 compatible = "rockchip,rk3399-qos", "syscon";
1019 reg = <0x0 0xffae0000 0x0 0x20>;
1022 pmu: power-management@ff310000 {
1023 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1024 reg = <0x0 0xff310000 0x0 0x1000>;
1027 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
1028 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
1029 * Some of the power domains are grouped together for every
1031 * The detail contents as below.
1033 power: power-controller {
1034 compatible = "rockchip,rk3399-power-controller";
1035 #power-domain-cells = <1>;
1036 #address-cells = <1>;
1039 /* These power domains are grouped by VD_CENTER */
1040 power-domain@RK3399_PD_IEP {
1041 reg = <RK3399_PD_IEP>;
1042 clocks = <&cru ACLK_IEP>,
1044 pm_qos = <&qos_iep>;
1045 #power-domain-cells = <0>;
1047 power-domain@RK3399_PD_RGA {
1048 reg = <RK3399_PD_RGA>;
1049 clocks = <&cru ACLK_RGA>,
1051 pm_qos = <&qos_rga_r>,
1053 #power-domain-cells = <0>;
1055 power-domain@RK3399_PD_VCODEC {
1056 reg = <RK3399_PD_VCODEC>;
1057 clocks = <&cru ACLK_VCODEC>,
1059 pm_qos = <&qos_video_m0>;
1060 #power-domain-cells = <0>;
1062 power-domain@RK3399_PD_VDU {
1063 reg = <RK3399_PD_VDU>;
1064 clocks = <&cru ACLK_VDU>,
1067 <&cru SCLK_VDU_CORE>;
1068 pm_qos = <&qos_video_m1_r>,
1070 #power-domain-cells = <0>;
1073 /* These power domains are grouped by VD_GPU */
1074 power-domain@RK3399_PD_GPU {
1075 reg = <RK3399_PD_GPU>;
1076 clocks = <&cru ACLK_GPU>;
1077 pm_qos = <&qos_gpu>;
1078 #power-domain-cells = <0>;
1081 /* These power domains are grouped by VD_LOGIC */
1082 power-domain@RK3399_PD_EDP {
1083 reg = <RK3399_PD_EDP>;
1084 clocks = <&cru PCLK_EDP_CTRL>;
1085 #power-domain-cells = <0>;
1087 power-domain@RK3399_PD_EMMC {
1088 reg = <RK3399_PD_EMMC>;
1089 clocks = <&cru ACLK_EMMC>;
1090 pm_qos = <&qos_emmc>;
1091 #power-domain-cells = <0>;
1093 power-domain@RK3399_PD_GMAC {
1094 reg = <RK3399_PD_GMAC>;
1095 clocks = <&cru ACLK_GMAC>,
1097 pm_qos = <&qos_gmac>;
1098 #power-domain-cells = <0>;
1100 power-domain@RK3399_PD_SD {
1101 reg = <RK3399_PD_SD>;
1102 clocks = <&cru HCLK_SDMMC>,
1105 #power-domain-cells = <0>;
1107 power-domain@RK3399_PD_SDIOAUDIO {
1108 reg = <RK3399_PD_SDIOAUDIO>;
1109 clocks = <&cru HCLK_SDIO>;
1110 pm_qos = <&qos_sdioaudio>;
1111 #power-domain-cells = <0>;
1113 power-domain@RK3399_PD_TCPD0 {
1114 reg = <RK3399_PD_TCPD0>;
1115 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1116 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1117 #power-domain-cells = <0>;
1119 power-domain@RK3399_PD_TCPD1 {
1120 reg = <RK3399_PD_TCPD1>;
1121 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1122 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1123 #power-domain-cells = <0>;
1125 power-domain@RK3399_PD_USB3 {
1126 reg = <RK3399_PD_USB3>;
1127 clocks = <&cru ACLK_USB3>;
1128 pm_qos = <&qos_usb_otg0>,
1130 #power-domain-cells = <0>;
1132 power-domain@RK3399_PD_VIO {
1133 reg = <RK3399_PD_VIO>;
1134 #power-domain-cells = <1>;
1135 #address-cells = <1>;
1138 power-domain@RK3399_PD_HDCP {
1139 reg = <RK3399_PD_HDCP>;
1140 clocks = <&cru ACLK_HDCP>,
1143 pm_qos = <&qos_hdcp>;
1144 #power-domain-cells = <0>;
1146 power-domain@RK3399_PD_ISP0 {
1147 reg = <RK3399_PD_ISP0>;
1148 clocks = <&cru ACLK_ISP0>,
1150 pm_qos = <&qos_isp0_m0>,
1152 #power-domain-cells = <0>;
1154 power-domain@RK3399_PD_ISP1 {
1155 reg = <RK3399_PD_ISP1>;
1156 clocks = <&cru ACLK_ISP1>,
1158 pm_qos = <&qos_isp1_m0>,
1160 #power-domain-cells = <0>;
1162 power-domain@RK3399_PD_VO {
1163 reg = <RK3399_PD_VO>;
1164 #power-domain-cells = <1>;
1165 #address-cells = <1>;
1168 power-domain@RK3399_PD_VOPB {
1169 reg = <RK3399_PD_VOPB>;
1170 clocks = <&cru ACLK_VOP0>,
1172 pm_qos = <&qos_vop_big_r>,
1174 #power-domain-cells = <0>;
1176 power-domain@RK3399_PD_VOPL {
1177 reg = <RK3399_PD_VOPL>;
1178 clocks = <&cru ACLK_VOP1>,
1180 pm_qos = <&qos_vop_little>;
1181 #power-domain-cells = <0>;
1188 pmugrf: syscon@ff320000 {
1189 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1190 reg = <0x0 0xff320000 0x0 0x1000>;
1192 pmu_io_domains: io-domains {
1193 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1194 status = "disabled";
1198 spi3: spi@ff350000 {
1199 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1200 reg = <0x0 0xff350000 0x0 0x1000>;
1201 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1202 clock-names = "spiclk", "apb_pclk";
1203 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1206 #address-cells = <1>;
1208 status = "disabled";
1211 uart4: serial@ff370000 {
1212 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1213 reg = <0x0 0xff370000 0x0 0x100>;
1214 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1215 clock-names = "baudclk", "apb_pclk";
1216 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&uart4_xfer>;
1221 status = "disabled";
1224 i2c0: i2c@ff3c0000 {
1225 compatible = "rockchip,rk3399-i2c";
1226 reg = <0x0 0xff3c0000 0x0 0x1000>;
1227 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1228 assigned-clock-rates = <200000000>;
1229 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1230 clock-names = "i2c", "pclk";
1231 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&i2c0_xfer>;
1234 #address-cells = <1>;
1236 status = "disabled";
1239 i2c4: i2c@ff3d0000 {
1240 compatible = "rockchip,rk3399-i2c";
1241 reg = <0x0 0xff3d0000 0x0 0x1000>;
1242 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1243 assigned-clock-rates = <200000000>;
1244 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1245 clock-names = "i2c", "pclk";
1246 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&i2c4_xfer>;
1249 #address-cells = <1>;
1251 status = "disabled";
1254 i2c8: i2c@ff3e0000 {
1255 compatible = "rockchip,rk3399-i2c";
1256 reg = <0x0 0xff3e0000 0x0 0x1000>;
1257 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1258 assigned-clock-rates = <200000000>;
1259 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1260 clock-names = "i2c", "pclk";
1261 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&i2c8_xfer>;
1264 #address-cells = <1>;
1266 status = "disabled";
1269 pwm0: pwm@ff420000 {
1270 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1271 reg = <0x0 0xff420000 0x0 0x10>;
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&pwm0_pin>;
1275 clocks = <&pmucru PCLK_RKPWM_PMU>;
1276 status = "disabled";
1279 pwm1: pwm@ff420010 {
1280 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1281 reg = <0x0 0xff420010 0x0 0x10>;
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&pwm1_pin>;
1285 clocks = <&pmucru PCLK_RKPWM_PMU>;
1286 status = "disabled";
1289 pwm2: pwm@ff420020 {
1290 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1291 reg = <0x0 0xff420020 0x0 0x10>;
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&pwm2_pin>;
1295 clocks = <&pmucru PCLK_RKPWM_PMU>;
1296 status = "disabled";
1299 pwm3: pwm@ff420030 {
1300 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1301 reg = <0x0 0xff420030 0x0 0x10>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&pwm3a_pin>;
1305 clocks = <&pmucru PCLK_RKPWM_PMU>;
1306 status = "disabled";
1310 reg = <0x00 0xff630000 0x00 0x4000>;
1311 compatible = "rockchip,rk3399-dfi";
1312 rockchip,pmu = <&pmugrf>;
1313 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1314 clocks = <&cru PCLK_DDR_MON>;
1315 clock-names = "pclk_ddr_mon";
1316 status = "disabled";
1319 vpu: video-codec@ff650000 {
1320 compatible = "rockchip,rk3399-vpu";
1321 reg = <0x0 0xff650000 0x0 0x800>;
1322 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1323 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1324 interrupt-names = "vepu", "vdpu";
1325 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1326 clock-names = "aclk", "hclk";
1327 iommus = <&vpu_mmu>;
1328 power-domains = <&power RK3399_PD_VCODEC>;
1331 vpu_mmu: iommu@ff650800 {
1332 compatible = "rockchip,iommu";
1333 reg = <0x0 0xff650800 0x0 0x40>;
1334 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1335 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1336 clock-names = "aclk", "iface";
1338 power-domains = <&power RK3399_PD_VCODEC>;
1341 vdec: video-codec@ff660000 {
1342 compatible = "rockchip,rk3399-vdec";
1343 reg = <0x0 0xff660000 0x0 0x480>;
1344 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1345 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1346 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1347 clock-names = "axi", "ahb", "cabac", "core";
1348 iommus = <&vdec_mmu>;
1349 power-domains = <&power RK3399_PD_VDU>;
1352 vdec_mmu: iommu@ff660480 {
1353 compatible = "rockchip,iommu";
1354 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1356 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1357 clock-names = "aclk", "iface";
1358 power-domains = <&power RK3399_PD_VDU>;
1362 iep_mmu: iommu@ff670800 {
1363 compatible = "rockchip,iommu";
1364 reg = <0x0 0xff670800 0x0 0x40>;
1365 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1366 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1367 clock-names = "aclk", "iface";
1369 status = "disabled";
1373 compatible = "rockchip,rk3399-rga";
1374 reg = <0x0 0xff680000 0x0 0x10000>;
1375 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1376 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1377 clock-names = "aclk", "hclk", "sclk";
1378 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1379 reset-names = "core", "axi", "ahb";
1380 power-domains = <&power RK3399_PD_RGA>;
1383 efuse0: efuse@ff690000 {
1384 compatible = "rockchip,rk3399-efuse";
1385 reg = <0x0 0xff690000 0x0 0x80>;
1386 #address-cells = <1>;
1388 clocks = <&cru PCLK_EFUSE1024NS>;
1389 clock-names = "pclk_efuse";
1395 cpub_leakage: cpu-leakage@17 {
1398 gpu_leakage: gpu-leakage@18 {
1401 center_leakage: center-leakage@19 {
1404 cpul_leakage: cpu-leakage@1a {
1407 logic_leakage: logic-leakage@1b {
1410 wafer_info: wafer-info@1c {
1415 dmac_bus: dma-controller@ff6d0000 {
1416 compatible = "arm,pl330", "arm,primecell";
1417 reg = <0x0 0xff6d0000 0x0 0x4000>;
1418 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1419 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1421 arm,pl330-periph-burst;
1422 clocks = <&cru ACLK_DMAC0_PERILP>;
1423 clock-names = "apb_pclk";
1426 dmac_peri: dma-controller@ff6e0000 {
1427 compatible = "arm,pl330", "arm,primecell";
1428 reg = <0x0 0xff6e0000 0x0 0x4000>;
1429 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1430 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1432 arm,pl330-periph-burst;
1433 clocks = <&cru ACLK_DMAC1_PERILP>;
1434 clock-names = "apb_pclk";
1437 pmucru: clock-controller@ff750000 {
1438 compatible = "rockchip,rk3399-pmucru";
1439 reg = <0x0 0xff750000 0x0 0x1000>;
1441 clock-names = "xin24m";
1442 rockchip,grf = <&pmugrf>;
1445 assigned-clocks = <&pmucru PLL_PPLL>;
1446 assigned-clock-rates = <676000000>;
1449 cru: clock-controller@ff760000 {
1450 compatible = "rockchip,rk3399-cru";
1451 reg = <0x0 0xff760000 0x0 0x1000>;
1453 clock-names = "xin24m";
1454 rockchip,grf = <&grf>;
1458 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1460 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1462 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1463 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1464 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1465 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1466 <&cru ACLK_GIC_PRE>,
1469 assigned-clock-rates =
1470 <594000000>, <800000000>,
1472 <150000000>, <75000000>,
1474 <100000000>, <100000000>,
1475 <50000000>, <600000000>,
1476 <100000000>, <50000000>,
1477 <400000000>, <400000000>,
1483 grf: syscon@ff770000 {
1484 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1485 reg = <0x0 0xff770000 0x0 0x10000>;
1486 #address-cells = <1>;
1489 io_domains: io-domains {
1490 compatible = "rockchip,rk3399-io-voltage-domain";
1491 status = "disabled";
1494 mipi_dphy_rx0: mipi-dphy-rx0 {
1495 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1496 clocks = <&cru SCLK_MIPIDPHY_REF>,
1497 <&cru SCLK_DPHY_RX0_CFG>,
1498 <&cru PCLK_VIO_GRF>;
1499 clock-names = "dphy-ref", "dphy-cfg", "grf";
1500 power-domains = <&power RK3399_PD_VIO>;
1502 status = "disabled";
1505 u2phy0: usb2phy@e450 {
1506 compatible = "rockchip,rk3399-usb2phy";
1507 reg = <0xe450 0x10>;
1508 clocks = <&cru SCLK_USB2PHY0_REF>;
1509 clock-names = "phyclk";
1511 clock-output-names = "clk_usbphy0_480m";
1512 status = "disabled";
1514 u2phy0_host: host-port {
1516 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1517 interrupt-names = "linestate";
1518 status = "disabled";
1521 u2phy0_otg: otg-port {
1523 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1524 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1525 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1526 interrupt-names = "otg-bvalid", "otg-id",
1528 status = "disabled";
1532 u2phy1: usb2phy@e460 {
1533 compatible = "rockchip,rk3399-usb2phy";
1534 reg = <0xe460 0x10>;
1535 clocks = <&cru SCLK_USB2PHY1_REF>;
1536 clock-names = "phyclk";
1538 clock-output-names = "clk_usbphy1_480m";
1539 status = "disabled";
1541 u2phy1_host: host-port {
1543 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1544 interrupt-names = "linestate";
1545 status = "disabled";
1548 u2phy1_otg: otg-port {
1550 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1551 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1552 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1553 interrupt-names = "otg-bvalid", "otg-id",
1555 status = "disabled";
1559 emmc_phy: phy@f780 {
1560 compatible = "rockchip,rk3399-emmc-phy";
1561 reg = <0xf780 0x24>;
1563 clock-names = "emmcclk";
1564 drive-impedance-ohm = <50>;
1566 status = "disabled";
1569 pcie_phy: pcie-phy {
1570 compatible = "rockchip,rk3399-pcie-phy";
1571 clocks = <&cru SCLK_PCIEPHY_REF>;
1572 clock-names = "refclk";
1574 resets = <&cru SRST_PCIEPHY>;
1575 reset-names = "phy";
1576 status = "disabled";
1580 tcphy0: phy@ff7c0000 {
1581 compatible = "rockchip,rk3399-typec-phy";
1582 reg = <0x0 0xff7c0000 0x0 0x40000>;
1583 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1584 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1585 clock-names = "tcpdcore", "tcpdphy-ref";
1586 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1587 assigned-clock-rates = <50000000>;
1588 power-domains = <&power RK3399_PD_TCPD0>;
1589 resets = <&cru SRST_UPHY0>,
1590 <&cru SRST_UPHY0_PIPE_L00>,
1591 <&cru SRST_P_UPHY0_TCPHY>;
1592 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1593 rockchip,grf = <&grf>;
1594 status = "disabled";
1596 tcphy0_dp: dp-port {
1600 tcphy0_usb3: usb3-port {
1605 tcphy1: phy@ff800000 {
1606 compatible = "rockchip,rk3399-typec-phy";
1607 reg = <0x0 0xff800000 0x0 0x40000>;
1608 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1609 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1610 clock-names = "tcpdcore", "tcpdphy-ref";
1611 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1612 assigned-clock-rates = <50000000>;
1613 power-domains = <&power RK3399_PD_TCPD1>;
1614 resets = <&cru SRST_UPHY1>,
1615 <&cru SRST_UPHY1_PIPE_L00>,
1616 <&cru SRST_P_UPHY1_TCPHY>;
1617 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1618 rockchip,grf = <&grf>;
1619 status = "disabled";
1621 tcphy1_dp: dp-port {
1625 tcphy1_usb3: usb3-port {
1631 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1632 reg = <0x0 0xff848000 0x0 0x100>;
1633 clocks = <&cru PCLK_WDT>;
1634 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1637 rktimer: rktimer@ff850000 {
1638 compatible = "rockchip,rk3399-timer";
1639 reg = <0x0 0xff850000 0x0 0x1000>;
1640 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1641 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1642 clock-names = "pclk", "timer";
1645 spdif: spdif@ff870000 {
1646 compatible = "rockchip,rk3399-spdif";
1647 reg = <0x0 0xff870000 0x0 0x1000>;
1648 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1649 dmas = <&dmac_bus 7>;
1651 clock-names = "mclk", "hclk";
1652 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&spdif_bus>;
1655 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1656 #sound-dai-cells = <0>;
1657 status = "disabled";
1660 i2s0: i2s@ff880000 {
1661 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1662 reg = <0x0 0xff880000 0x0 0x1000>;
1663 rockchip,grf = <&grf>;
1664 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1665 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1666 dma-names = "tx", "rx";
1667 clock-names = "i2s_clk", "i2s_hclk";
1668 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1669 pinctrl-names = "bclk_on", "bclk_off";
1670 pinctrl-0 = <&i2s0_8ch_bus>;
1671 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1672 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1673 #sound-dai-cells = <0>;
1674 status = "disabled";
1677 i2s1: i2s@ff890000 {
1678 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1679 reg = <0x0 0xff890000 0x0 0x1000>;
1680 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1681 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1682 dma-names = "tx", "rx";
1683 clock-names = "i2s_clk", "i2s_hclk";
1684 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&i2s1_2ch_bus>;
1687 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1688 #sound-dai-cells = <0>;
1689 status = "disabled";
1692 i2s2: i2s@ff8a0000 {
1693 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1694 reg = <0x0 0xff8a0000 0x0 0x1000>;
1695 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1696 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1697 dma-names = "tx", "rx";
1698 clock-names = "i2s_clk", "i2s_hclk";
1699 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1700 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1701 #sound-dai-cells = <0>;
1702 status = "disabled";
1705 vopl: vop@ff8f0000 {
1706 compatible = "rockchip,rk3399-vop-lit";
1707 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
1708 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1709 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1710 assigned-clock-rates = <400000000>, <100000000>;
1711 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1712 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1713 iommus = <&vopl_mmu>;
1714 power-domains = <&power RK3399_PD_VOPL>;
1715 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1716 reset-names = "axi", "ahb", "dclk";
1717 status = "disabled";
1720 #address-cells = <1>;
1723 vopl_out_mipi: endpoint@0 {
1725 remote-endpoint = <&mipi_in_vopl>;
1728 vopl_out_edp: endpoint@1 {
1730 remote-endpoint = <&edp_in_vopl>;
1733 vopl_out_hdmi: endpoint@2 {
1735 remote-endpoint = <&hdmi_in_vopl>;
1738 vopl_out_mipi1: endpoint@3 {
1740 remote-endpoint = <&mipi1_in_vopl>;
1743 vopl_out_dp: endpoint@4 {
1745 remote-endpoint = <&dp_in_vopl>;
1750 vopl_mmu: iommu@ff8f3f00 {
1751 compatible = "rockchip,iommu";
1752 reg = <0x0 0xff8f3f00 0x0 0x100>;
1753 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1754 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1755 clock-names = "aclk", "iface";
1756 power-domains = <&power RK3399_PD_VOPL>;
1758 status = "disabled";
1761 vopb: vop@ff900000 {
1762 compatible = "rockchip,rk3399-vop-big";
1763 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
1764 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1765 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1766 assigned-clock-rates = <400000000>, <100000000>;
1767 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1768 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1769 iommus = <&vopb_mmu>;
1770 power-domains = <&power RK3399_PD_VOPB>;
1771 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1772 reset-names = "axi", "ahb", "dclk";
1773 status = "disabled";
1776 #address-cells = <1>;
1779 vopb_out_edp: endpoint@0 {
1781 remote-endpoint = <&edp_in_vopb>;
1784 vopb_out_mipi: endpoint@1 {
1786 remote-endpoint = <&mipi_in_vopb>;
1789 vopb_out_hdmi: endpoint@2 {
1791 remote-endpoint = <&hdmi_in_vopb>;
1794 vopb_out_mipi1: endpoint@3 {
1796 remote-endpoint = <&mipi1_in_vopb>;
1799 vopb_out_dp: endpoint@4 {
1801 remote-endpoint = <&dp_in_vopb>;
1806 vopb_mmu: iommu@ff903f00 {
1807 compatible = "rockchip,iommu";
1808 reg = <0x0 0xff903f00 0x0 0x100>;
1809 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1810 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1811 clock-names = "aclk", "iface";
1812 power-domains = <&power RK3399_PD_VOPB>;
1814 status = "disabled";
1817 isp0: isp0@ff910000 {
1818 compatible = "rockchip,rk3399-cif-isp";
1819 reg = <0x0 0xff910000 0x0 0x4000>;
1820 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1821 clocks = <&cru SCLK_ISP0>,
1822 <&cru ACLK_ISP0_WRAPPER>,
1823 <&cru HCLK_ISP0_WRAPPER>;
1824 clock-names = "isp", "aclk", "hclk";
1825 iommus = <&isp0_mmu>;
1826 phys = <&mipi_dphy_rx0>;
1828 power-domains = <&power RK3399_PD_ISP0>;
1829 status = "disabled";
1832 #address-cells = <1>;
1837 #address-cells = <1>;
1843 isp0_mmu: iommu@ff914000 {
1844 compatible = "rockchip,iommu";
1845 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1846 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1847 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1848 clock-names = "aclk", "iface";
1850 power-domains = <&power RK3399_PD_ISP0>;
1851 rockchip,disable-mmu-reset;
1854 isp1: isp1@ff920000 {
1855 compatible = "rockchip,rk3399-cif-isp";
1856 reg = <0x0 0xff920000 0x0 0x4000>;
1857 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1858 clocks = <&cru SCLK_ISP1>,
1859 <&cru ACLK_ISP1_WRAPPER>,
1860 <&cru HCLK_ISP1_WRAPPER>;
1861 clock-names = "isp", "aclk", "hclk";
1862 iommus = <&isp1_mmu>;
1863 phys = <&mipi_dsi1>;
1865 power-domains = <&power RK3399_PD_ISP1>;
1866 status = "disabled";
1869 #address-cells = <1>;
1874 #address-cells = <1>;
1880 isp1_mmu: iommu@ff924000 {
1881 compatible = "rockchip,iommu";
1882 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1883 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1884 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1885 clock-names = "aclk", "iface";
1887 power-domains = <&power RK3399_PD_ISP1>;
1888 rockchip,disable-mmu-reset;
1891 hdmi_sound: hdmi-sound {
1892 compatible = "simple-audio-card";
1893 simple-audio-card,format = "i2s";
1894 simple-audio-card,mclk-fs = <256>;
1895 simple-audio-card,name = "hdmi-sound";
1896 status = "disabled";
1898 simple-audio-card,cpu {
1899 sound-dai = <&i2s2>;
1901 simple-audio-card,codec {
1902 sound-dai = <&hdmi>;
1906 hdmi: hdmi@ff940000 {
1907 compatible = "rockchip,rk3399-dw-hdmi";
1908 reg = <0x0 0xff940000 0x0 0x20000>;
1910 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1911 clocks = <&cru PCLK_HDMI_CTRL>,
1912 <&cru SCLK_HDMI_SFR>,
1913 <&cru SCLK_HDMI_CEC>,
1914 <&cru PCLK_VIO_GRF>,
1916 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1917 power-domains = <&power RK3399_PD_HDCP>;
1918 rockchip,grf = <&grf>;
1919 #sound-dai-cells = <0>;
1920 status = "disabled";
1923 #address-cells = <1>;
1928 #address-cells = <1>;
1931 hdmi_in_vopb: endpoint@0 {
1933 remote-endpoint = <&vopb_out_hdmi>;
1935 hdmi_in_vopl: endpoint@1 {
1937 remote-endpoint = <&vopl_out_hdmi>;
1947 mipi_dsi: mipi@ff960000 {
1948 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1949 reg = <0x0 0xff960000 0x0 0x8000>;
1950 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1951 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1952 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1953 clock-names = "ref", "pclk", "phy_cfg", "grf";
1954 power-domains = <&power RK3399_PD_VIO>;
1955 resets = <&cru SRST_P_MIPI_DSI0>;
1956 reset-names = "apb";
1957 rockchip,grf = <&grf>;
1958 #address-cells = <1>;
1960 status = "disabled";
1963 #address-cells = <1>;
1968 #address-cells = <1>;
1971 mipi_in_vopb: endpoint@0 {
1973 remote-endpoint = <&vopb_out_mipi>;
1975 mipi_in_vopl: endpoint@1 {
1977 remote-endpoint = <&vopl_out_mipi>;
1983 mipi_dsi1: mipi@ff968000 {
1984 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1985 reg = <0x0 0xff968000 0x0 0x8000>;
1986 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1987 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1988 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1989 clock-names = "ref", "pclk", "phy_cfg", "grf";
1990 power-domains = <&power RK3399_PD_VIO>;
1991 resets = <&cru SRST_P_MIPI_DSI1>;
1992 reset-names = "apb";
1993 rockchip,grf = <&grf>;
1994 #address-cells = <1>;
1997 status = "disabled";
2000 #address-cells = <1>;
2005 #address-cells = <1>;
2008 mipi1_in_vopb: endpoint@0 {
2010 remote-endpoint = <&vopb_out_mipi1>;
2013 mipi1_in_vopl: endpoint@1 {
2015 remote-endpoint = <&vopl_out_mipi1>;
2022 compatible = "rockchip,rk3399-edp";
2023 reg = <0x0 0xff970000 0x0 0x8000>;
2024 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
2025 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2026 clock-names = "dp", "pclk", "grf";
2027 pinctrl-names = "default";
2028 pinctrl-0 = <&edp_hpd>;
2029 power-domains = <&power RK3399_PD_EDP>;
2030 resets = <&cru SRST_P_EDP_CTRL>;
2032 rockchip,grf = <&grf>;
2033 status = "disabled";
2036 #address-cells = <1>;
2040 #address-cells = <1>;
2043 edp_in_vopb: endpoint@0 {
2045 remote-endpoint = <&vopb_out_edp>;
2048 edp_in_vopl: endpoint@1 {
2050 remote-endpoint = <&vopl_out_edp>;
2057 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2058 reg = <0x0 0xff9a0000 0x0 0x10000>;
2059 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
2060 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
2061 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
2062 interrupt-names = "job", "mmu", "gpu";
2063 clocks = <&cru ACLK_GPU>;
2064 #cooling-cells = <2>;
2065 power-domains = <&power RK3399_PD_GPU>;
2066 status = "disabled";
2070 compatible = "rockchip,rk3399-pinctrl";
2071 rockchip,grf = <&grf>;
2072 rockchip,pmu = <&pmugrf>;
2073 #address-cells = <2>;
2077 gpio0: gpio@ff720000 {
2078 compatible = "rockchip,gpio-bank";
2079 reg = <0x0 0xff720000 0x0 0x100>;
2080 clocks = <&pmucru PCLK_GPIO0_PMU>;
2081 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2084 #gpio-cells = <0x2>;
2086 interrupt-controller;
2087 #interrupt-cells = <0x2>;
2090 gpio1: gpio@ff730000 {
2091 compatible = "rockchip,gpio-bank";
2092 reg = <0x0 0xff730000 0x0 0x100>;
2093 clocks = <&pmucru PCLK_GPIO1_PMU>;
2094 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2097 #gpio-cells = <0x2>;
2099 interrupt-controller;
2100 #interrupt-cells = <0x2>;
2103 gpio2: gpio@ff780000 {
2104 compatible = "rockchip,gpio-bank";
2105 reg = <0x0 0xff780000 0x0 0x100>;
2106 clocks = <&cru PCLK_GPIO2>;
2107 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2110 #gpio-cells = <0x2>;
2112 interrupt-controller;
2113 #interrupt-cells = <0x2>;
2116 gpio3: gpio@ff788000 {
2117 compatible = "rockchip,gpio-bank";
2118 reg = <0x0 0xff788000 0x0 0x100>;
2119 clocks = <&cru PCLK_GPIO3>;
2120 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2123 #gpio-cells = <0x2>;
2125 interrupt-controller;
2126 #interrupt-cells = <0x2>;
2129 gpio4: gpio@ff790000 {
2130 compatible = "rockchip,gpio-bank";
2131 reg = <0x0 0xff790000 0x0 0x100>;
2132 clocks = <&cru PCLK_GPIO4>;
2133 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2136 #gpio-cells = <0x2>;
2138 interrupt-controller;
2139 #interrupt-cells = <0x2>;
2142 pcfg_pull_up: pcfg-pull-up {
2146 pcfg_pull_down: pcfg-pull-down {
2150 pcfg_pull_none: pcfg-pull-none {
2154 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2156 drive-strength = <12>;
2159 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2161 drive-strength = <13>;
2164 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2166 drive-strength = <18>;
2169 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2171 drive-strength = <20>;
2174 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2176 drive-strength = <2>;
2179 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2181 drive-strength = <8>;
2184 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2186 drive-strength = <18>;
2189 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2191 drive-strength = <20>;
2194 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2196 drive-strength = <4>;
2199 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2201 drive-strength = <8>;
2204 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2206 drive-strength = <12>;
2209 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2211 drive-strength = <18>;
2214 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2216 drive-strength = <20>;
2219 pcfg_output_high: pcfg-output-high {
2223 pcfg_output_low: pcfg-output-low {
2227 pcfg_input_enable: pcfg-input-enable {
2231 pcfg_input_pull_up: pcfg-input-pull-up {
2236 pcfg_input_pull_down: pcfg-input-pull-down {
2243 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2248 cif_clkin: cif-clkin {
2250 <2 RK_PB2 3 &pcfg_pull_none>;
2253 cif_clkouta: cif-clkouta {
2255 <2 RK_PB3 3 &pcfg_pull_none>;
2262 <4 RK_PC7 2 &pcfg_pull_none>;
2267 rgmii_pins: rgmii-pins {
2270 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2272 <3 RK_PB6 1 &pcfg_pull_none>,
2274 <3 RK_PB5 1 &pcfg_pull_none>,
2276 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2278 <3 RK_PB3 1 &pcfg_pull_none>,
2280 <3 RK_PB1 1 &pcfg_pull_none>,
2282 <3 RK_PB0 1 &pcfg_pull_none>,
2284 <3 RK_PA7 1 &pcfg_pull_none>,
2286 <3 RK_PA6 1 &pcfg_pull_none>,
2288 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2290 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2292 <3 RK_PA3 1 &pcfg_pull_none>,
2294 <3 RK_PA2 1 &pcfg_pull_none>,
2296 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2298 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2301 rmii_pins: rmii-pins {
2304 <3 RK_PB5 1 &pcfg_pull_none>,
2306 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2308 <3 RK_PB3 1 &pcfg_pull_none>,
2310 <3 RK_PB2 1 &pcfg_pull_none>,
2312 <3 RK_PB1 1 &pcfg_pull_none>,
2314 <3 RK_PB0 1 &pcfg_pull_none>,
2316 <3 RK_PA7 1 &pcfg_pull_none>,
2318 <3 RK_PA6 1 &pcfg_pull_none>,
2320 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2322 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2327 i2c0_xfer: i2c0-xfer {
2329 <1 RK_PB7 2 &pcfg_pull_none>,
2330 <1 RK_PC0 2 &pcfg_pull_none>;
2335 i2c1_xfer: i2c1-xfer {
2337 <4 RK_PA2 1 &pcfg_pull_none>,
2338 <4 RK_PA1 1 &pcfg_pull_none>;
2343 i2c2_xfer: i2c2-xfer {
2345 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2346 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2351 i2c3_xfer: i2c3-xfer {
2353 <4 RK_PC1 1 &pcfg_pull_none>,
2354 <4 RK_PC0 1 &pcfg_pull_none>;
2359 i2c4_xfer: i2c4-xfer {
2361 <1 RK_PB4 1 &pcfg_pull_none>,
2362 <1 RK_PB3 1 &pcfg_pull_none>;
2367 i2c5_xfer: i2c5-xfer {
2369 <3 RK_PB3 2 &pcfg_pull_none>,
2370 <3 RK_PB2 2 &pcfg_pull_none>;
2375 i2c6_xfer: i2c6-xfer {
2377 <2 RK_PB2 2 &pcfg_pull_none>,
2378 <2 RK_PB1 2 &pcfg_pull_none>;
2383 i2c7_xfer: i2c7-xfer {
2385 <2 RK_PB0 2 &pcfg_pull_none>,
2386 <2 RK_PA7 2 &pcfg_pull_none>;
2391 i2c8_xfer: i2c8-xfer {
2393 <1 RK_PC5 1 &pcfg_pull_none>,
2394 <1 RK_PC4 1 &pcfg_pull_none>;
2399 i2s0_2ch_bus: i2s0-2ch-bus {
2401 <3 RK_PD0 1 &pcfg_pull_none>,
2402 <3 RK_PD1 1 &pcfg_pull_none>,
2403 <3 RK_PD2 1 &pcfg_pull_none>,
2404 <3 RK_PD3 1 &pcfg_pull_none>,
2405 <3 RK_PD7 1 &pcfg_pull_none>,
2406 <4 RK_PA0 1 &pcfg_pull_none>;
2409 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2411 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
2412 <3 RK_PD1 1 &pcfg_pull_none>,
2413 <3 RK_PD2 1 &pcfg_pull_none>,
2414 <3 RK_PD3 1 &pcfg_pull_none>,
2415 <3 RK_PD7 1 &pcfg_pull_none>,
2416 <4 RK_PA0 1 &pcfg_pull_none>;
2419 i2s0_8ch_bus: i2s0-8ch-bus {
2421 <3 RK_PD0 1 &pcfg_pull_none>,
2422 <3 RK_PD1 1 &pcfg_pull_none>,
2423 <3 RK_PD2 1 &pcfg_pull_none>,
2424 <3 RK_PD3 1 &pcfg_pull_none>,
2425 <3 RK_PD4 1 &pcfg_pull_none>,
2426 <3 RK_PD5 1 &pcfg_pull_none>,
2427 <3 RK_PD6 1 &pcfg_pull_none>,
2428 <3 RK_PD7 1 &pcfg_pull_none>,
2429 <4 RK_PA0 1 &pcfg_pull_none>;
2432 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2434 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
2435 <3 RK_PD1 1 &pcfg_pull_none>,
2436 <3 RK_PD2 1 &pcfg_pull_none>,
2437 <3 RK_PD3 1 &pcfg_pull_none>,
2438 <3 RK_PD4 1 &pcfg_pull_none>,
2439 <3 RK_PD5 1 &pcfg_pull_none>,
2440 <3 RK_PD6 1 &pcfg_pull_none>,
2441 <3 RK_PD7 1 &pcfg_pull_none>,
2442 <4 RK_PA0 1 &pcfg_pull_none>;
2447 i2s1_2ch_bus: i2s1-2ch-bus {
2449 <4 RK_PA3 1 &pcfg_pull_none>,
2450 <4 RK_PA4 1 &pcfg_pull_none>,
2451 <4 RK_PA5 1 &pcfg_pull_none>,
2452 <4 RK_PA6 1 &pcfg_pull_none>,
2453 <4 RK_PA7 1 &pcfg_pull_none>;
2456 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2458 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
2459 <4 RK_PA4 1 &pcfg_pull_none>,
2460 <4 RK_PA5 1 &pcfg_pull_none>,
2461 <4 RK_PA6 1 &pcfg_pull_none>,
2462 <4 RK_PA7 1 &pcfg_pull_none>;
2467 sdio0_bus1: sdio0-bus1 {
2469 <2 RK_PC4 1 &pcfg_pull_up>;
2472 sdio0_bus4: sdio0-bus4 {
2474 <2 RK_PC4 1 &pcfg_pull_up>,
2475 <2 RK_PC5 1 &pcfg_pull_up>,
2476 <2 RK_PC6 1 &pcfg_pull_up>,
2477 <2 RK_PC7 1 &pcfg_pull_up>;
2480 sdio0_cmd: sdio0-cmd {
2482 <2 RK_PD0 1 &pcfg_pull_up>;
2485 sdio0_clk: sdio0-clk {
2487 <2 RK_PD1 1 &pcfg_pull_none>;
2490 sdio0_cd: sdio0-cd {
2492 <2 RK_PD2 1 &pcfg_pull_up>;
2495 sdio0_pwr: sdio0-pwr {
2497 <2 RK_PD3 1 &pcfg_pull_up>;
2500 sdio0_bkpwr: sdio0-bkpwr {
2502 <2 RK_PD4 1 &pcfg_pull_up>;
2505 sdio0_wp: sdio0-wp {
2507 <0 RK_PA3 1 &pcfg_pull_up>;
2510 sdio0_int: sdio0-int {
2512 <0 RK_PA4 1 &pcfg_pull_up>;
2517 sdmmc_bus1: sdmmc-bus1 {
2519 <4 RK_PB0 1 &pcfg_pull_up>;
2522 sdmmc_bus4: sdmmc-bus4 {
2524 <4 RK_PB0 1 &pcfg_pull_up>,
2525 <4 RK_PB1 1 &pcfg_pull_up>,
2526 <4 RK_PB2 1 &pcfg_pull_up>,
2527 <4 RK_PB3 1 &pcfg_pull_up>;
2530 sdmmc_clk: sdmmc-clk {
2532 <4 RK_PB4 1 &pcfg_pull_none>;
2535 sdmmc_cmd: sdmmc-cmd {
2537 <4 RK_PB5 1 &pcfg_pull_up>;
2540 sdmmc_cd: sdmmc-cd {
2542 <0 RK_PA7 1 &pcfg_pull_up>;
2545 sdmmc_wp: sdmmc-wp {
2547 <0 RK_PB0 1 &pcfg_pull_up>;
2552 ap_pwroff: ap-pwroff {
2553 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2556 ddrio_pwroff: ddrio-pwroff {
2557 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2562 spdif_bus: spdif-bus {
2564 <4 RK_PC5 1 &pcfg_pull_none>;
2567 spdif_bus_1: spdif-bus-1 {
2569 <3 RK_PC0 3 &pcfg_pull_none>;
2574 spi0_clk: spi0-clk {
2576 <3 RK_PA6 2 &pcfg_pull_up>;
2578 spi0_cs0: spi0-cs0 {
2580 <3 RK_PA7 2 &pcfg_pull_up>;
2582 spi0_cs1: spi0-cs1 {
2584 <3 RK_PB0 2 &pcfg_pull_up>;
2588 <3 RK_PA5 2 &pcfg_pull_up>;
2592 <3 RK_PA4 2 &pcfg_pull_up>;
2597 spi1_clk: spi1-clk {
2599 <1 RK_PB1 2 &pcfg_pull_up>;
2601 spi1_cs0: spi1-cs0 {
2603 <1 RK_PB2 2 &pcfg_pull_up>;
2607 <1 RK_PA7 2 &pcfg_pull_up>;
2611 <1 RK_PB0 2 &pcfg_pull_up>;
2616 spi2_clk: spi2-clk {
2618 <2 RK_PB3 1 &pcfg_pull_up>;
2620 spi2_cs0: spi2-cs0 {
2622 <2 RK_PB4 1 &pcfg_pull_up>;
2626 <2 RK_PB1 1 &pcfg_pull_up>;
2630 <2 RK_PB2 1 &pcfg_pull_up>;
2635 spi3_clk: spi3-clk {
2637 <1 RK_PC1 1 &pcfg_pull_up>;
2639 spi3_cs0: spi3-cs0 {
2641 <1 RK_PC2 1 &pcfg_pull_up>;
2645 <1 RK_PB7 1 &pcfg_pull_up>;
2649 <1 RK_PC0 1 &pcfg_pull_up>;
2654 spi4_clk: spi4-clk {
2656 <3 RK_PA2 2 &pcfg_pull_up>;
2658 spi4_cs0: spi4-cs0 {
2660 <3 RK_PA3 2 &pcfg_pull_up>;
2664 <3 RK_PA0 2 &pcfg_pull_up>;
2668 <3 RK_PA1 2 &pcfg_pull_up>;
2673 spi5_clk: spi5-clk {
2675 <2 RK_PC6 2 &pcfg_pull_up>;
2677 spi5_cs0: spi5-cs0 {
2679 <2 RK_PC7 2 &pcfg_pull_up>;
2683 <2 RK_PC4 2 &pcfg_pull_up>;
2687 <2 RK_PC5 2 &pcfg_pull_up>;
2692 test_clkout0: test-clkout0 {
2694 <0 RK_PA0 1 &pcfg_pull_none>;
2697 test_clkout1: test-clkout1 {
2699 <2 RK_PD1 2 &pcfg_pull_none>;
2702 test_clkout2: test-clkout2 {
2704 <0 RK_PB0 3 &pcfg_pull_none>;
2710 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2714 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2719 uart0_xfer: uart0-xfer {
2721 <2 RK_PC0 1 &pcfg_pull_up>,
2722 <2 RK_PC1 1 &pcfg_pull_none>;
2725 uart0_cts: uart0-cts {
2727 <2 RK_PC2 1 &pcfg_pull_none>;
2730 uart0_rts: uart0-rts {
2732 <2 RK_PC3 1 &pcfg_pull_none>;
2737 uart1_xfer: uart1-xfer {
2739 <3 RK_PB4 2 &pcfg_pull_up>,
2740 <3 RK_PB5 2 &pcfg_pull_none>;
2745 uart2a_xfer: uart2a-xfer {
2747 <4 RK_PB0 2 &pcfg_pull_up>,
2748 <4 RK_PB1 2 &pcfg_pull_none>;
2753 uart2b_xfer: uart2b-xfer {
2755 <4 RK_PC0 2 &pcfg_pull_up>,
2756 <4 RK_PC1 2 &pcfg_pull_none>;
2761 uart2c_xfer: uart2c-xfer {
2763 <4 RK_PC3 1 &pcfg_pull_up>,
2764 <4 RK_PC4 1 &pcfg_pull_none>;
2769 uart3_xfer: uart3-xfer {
2771 <3 RK_PB6 2 &pcfg_pull_up>,
2772 <3 RK_PB7 2 &pcfg_pull_none>;
2775 uart3_cts: uart3-cts {
2777 <3 RK_PC0 2 &pcfg_pull_none>;
2780 uart3_rts: uart3-rts {
2782 <3 RK_PC1 2 &pcfg_pull_none>;
2787 uart4_xfer: uart4-xfer {
2789 <1 RK_PA7 1 &pcfg_pull_up>,
2790 <1 RK_PB0 1 &pcfg_pull_none>;
2795 uarthdcp_xfer: uarthdcp-xfer {
2797 <4 RK_PC5 2 &pcfg_pull_up>,
2798 <4 RK_PC6 2 &pcfg_pull_none>;
2803 pwm0_pin: pwm0-pin {
2805 <4 RK_PC2 1 &pcfg_pull_none>;
2808 pwm0_pin_pull_down: pwm0-pin-pull-down {
2810 <4 RK_PC2 1 &pcfg_pull_down>;
2813 vop0_pwm_pin: vop0-pwm-pin {
2815 <4 RK_PC2 2 &pcfg_pull_none>;
2818 vop1_pwm_pin: vop1-pwm-pin {
2820 <4 RK_PC2 3 &pcfg_pull_none>;
2825 pwm1_pin: pwm1-pin {
2827 <4 RK_PC6 1 &pcfg_pull_none>;
2830 pwm1_pin_pull_down: pwm1-pin-pull-down {
2832 <4 RK_PC6 1 &pcfg_pull_down>;
2837 pwm2_pin: pwm2-pin {
2839 <1 RK_PC3 1 &pcfg_pull_none>;
2842 pwm2_pin_pull_down: pwm2-pin-pull-down {
2844 <1 RK_PC3 1 &pcfg_pull_down>;
2849 pwm3a_pin: pwm3a-pin {
2851 <0 RK_PA6 1 &pcfg_pull_none>;
2856 pwm3b_pin: pwm3b-pin {
2858 <1 RK_PB6 1 &pcfg_pull_none>;
2863 hdmi_i2c_xfer: hdmi-i2c-xfer {
2865 <4 RK_PC1 3 &pcfg_pull_none>,
2866 <4 RK_PC0 3 &pcfg_pull_none>;
2869 hdmi_cec: hdmi-cec {
2871 <4 RK_PC7 1 &pcfg_pull_none>;
2876 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2878 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2881 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2883 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;