arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 mmc0 = &sdio0;
  70                 mmc1 = &sdmmc;
  71                 mmc2 = &sdhci;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         dynamic-power-coefficient = <100>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         dynamic-power-coefficient = <100>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         dynamic-power-coefficient = <100>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         dynamic-power-coefficient = <100>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         dynamic-power-coefficient = <436>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         dynamic-power-coefficient = <436>;
 163                 };
 164         };
 165
 166         display-subsystem {
 167                 compatible = "rockchip,display-subsystem";
 168                 ports = <&vopl_out>, <&vopb_out>;
 169         };
 170
 171         pmu_a53 {
 172                 compatible = "arm,cortex-a53-pmu";
 173                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 174         };
 175
 176         pmu_a72 {
 177                 compatible = "arm,cortex-a72-pmu";
 178                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 179         };
 180
 181         psci {
 182                 compatible = "arm,psci-1.0";
 183                 method = "smc";
 184         };
 185
 186         timer {
 187                 compatible = "arm,armv8-timer";
 188                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 189                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 190                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 191                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 192                 arm,no-tick-in-suspend;
 193         };
 194
 195         xin24m: xin24m {
 196                 compatible = "fixed-clock";
 197                 clock-frequency = <24000000>;
 198                 clock-output-names = "xin24m";
 199                 #clock-cells = <0>;
 200         };
 201
 202         amba {
 203                 compatible = "simple-bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 dmac_bus: dma-controller@ff6d0000 {
 209                         compatible = "arm,pl330", "arm,primecell";
 210                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 211                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 212                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 213                         #dma-cells = <1>;
 214                         clocks = <&cru ACLK_DMAC0_PERILP>;
 215                         clock-names = "apb_pclk";
 216                 };
 217
 218                 dmac_peri: dma-controller@ff6e0000 {
 219                         compatible = "arm,pl330", "arm,primecell";
 220                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 221                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 222                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 223                         #dma-cells = <1>;
 224                         clocks = <&cru ACLK_DMAC1_PERILP>;
 225                         clock-names = "apb_pclk";
 226                 };
 227         };
 228
 229         pcie0: pcie@f8000000 {
 230                 compatible = "rockchip,rk3399-pcie";
 231                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 232                       <0x0 0xfd000000 0x0 0x1000000>;
 233                 reg-names = "axi-base", "apb-base";
 234                 device_type = "pci";
 235                 #address-cells = <3>;
 236                 #size-cells = <2>;
 237                 #interrupt-cells = <1>;
 238                 aspm-no-l0s;
 239                 bus-range = <0x0 0x1f>;
 240                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 241                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 242                 clock-names = "aclk", "aclk-perf",
 243                               "hclk", "pm";
 244                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 245                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 246                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 247                 interrupt-names = "sys", "legacy", "client";
 248                 interrupt-map-mask = <0 0 0 7>;
 249                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 250                                 <0 0 0 2 &pcie0_intc 1>,
 251                                 <0 0 0 3 &pcie0_intc 2>,
 252                                 <0 0 0 4 &pcie0_intc 3>;
 253                 max-link-speed = <1>;
 254                 msi-map = <0x0 &its 0x0 0x1000>;
 255                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 256                        <&pcie_phy 2>, <&pcie_phy 3>;
 257                 phy-names = "pcie-phy-0", "pcie-phy-1",
 258                             "pcie-phy-2", "pcie-phy-3";
 259                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 260                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 261                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 262                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 263                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 264                          <&cru SRST_A_PCIE>;
 265                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 266                               "pm", "pclk", "aclk";
 267                 status = "disabled";
 268
 269                 pcie0_intc: interrupt-controller {
 270                         interrupt-controller;
 271                         #address-cells = <0>;
 272                         #interrupt-cells = <1>;
 273                 };
 274         };
 275
 276         gmac: ethernet@fe300000 {
 277                 compatible = "rockchip,rk3399-gmac";
 278                 reg = <0x0 0xfe300000 0x0 0x10000>;
 279                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 280                 interrupt-names = "macirq";
 281                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 282                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 283                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 284                          <&cru PCLK_GMAC>;
 285                 clock-names = "stmmaceth", "mac_clk_rx",
 286                               "mac_clk_tx", "clk_mac_ref",
 287                               "clk_mac_refout", "aclk_mac",
 288                               "pclk_mac";
 289                 power-domains = <&power RK3399_PD_GMAC>;
 290                 resets = <&cru SRST_A_GMAC>;
 291                 reset-names = "stmmaceth";
 292                 rockchip,grf = <&grf>;
 293                 status = "disabled";
 294         };
 295
 296         sdio0: dwmmc@fe310000 {
 297                 compatible = "rockchip,rk3399-dw-mshc",
 298                              "rockchip,rk3288-dw-mshc";
 299                 reg = <0x0 0xfe310000 0x0 0x4000>;
 300                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 301                 max-frequency = <150000000>;
 302                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 303                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 304                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 305                 fifo-depth = <0x100>;
 306                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 307                 resets = <&cru SRST_SDIO0>;
 308                 reset-names = "reset";
 309                 status = "disabled";
 310         };
 311
 312         sdmmc: dwmmc@fe320000 {
 313                 compatible = "rockchip,rk3399-dw-mshc",
 314                              "rockchip,rk3288-dw-mshc";
 315                 reg = <0x0 0xfe320000 0x0 0x4000>;
 316                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 317                 max-frequency = <150000000>;
 318                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 319                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 320                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 321                 fifo-depth = <0x100>;
 322                 power-domains = <&power RK3399_PD_SD>;
 323                 resets = <&cru SRST_SDMMC>;
 324                 reset-names = "reset";
 325                 status = "disabled";
 326         };
 327
 328         sdhci: sdhci@fe330000 {
 329                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 330                 reg = <0x0 0xfe330000 0x0 0x10000>;
 331                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 arasan,soc-ctl-syscon = <&grf>;
 333                 assigned-clocks = <&cru SCLK_EMMC>;
 334                 assigned-clock-rates = <200000000>;
 335                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 336                 clock-names = "clk_xin", "clk_ahb";
 337                 clock-output-names = "emmc_cardclock";
 338                 #clock-cells = <0>;
 339                 phys = <&emmc_phy>;
 340                 phy-names = "phy_arasan";
 341                 power-domains = <&power RK3399_PD_EMMC>;
 342                 status = "disabled";
 343         };
 344
 345         usb_host0_ehci: usb@fe380000 {
 346                 compatible = "generic-ehci";
 347                 reg = <0x0 0xfe380000 0x0 0x20000>;
 348                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 349                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 350                          <&u2phy0>;
 351                 clock-names = "usbhost", "arbiter",
 352                               "utmi";
 353                 phys = <&u2phy0_host>;
 354                 phy-names = "usb";
 355                 status = "disabled";
 356         };
 357
 358         usb_host0_ohci: usb@fe3a0000 {
 359                 compatible = "generic-ohci";
 360                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 361                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 362                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 363                          <&u2phy0>;
 364                 clock-names = "usbhost", "arbiter",
 365                               "utmi";
 366                 phys = <&u2phy0_host>;
 367                 phy-names = "usb";
 368                 status = "disabled";
 369         };
 370
 371         usb_host1_ehci: usb@fe3c0000 {
 372                 compatible = "generic-ehci";
 373                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 374                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 375                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 376                          <&u2phy1>;
 377                 clock-names = "usbhost", "arbiter",
 378                               "utmi";
 379                 phys = <&u2phy1_host>;
 380                 phy-names = "usb";
 381                 status = "disabled";
 382         };
 383
 384         usb_host1_ohci: usb@fe3e0000 {
 385                 compatible = "generic-ohci";
 386                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 387                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 388                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 389                          <&u2phy1>;
 390                 clock-names = "usbhost", "arbiter",
 391                               "utmi";
 392                 phys = <&u2phy1_host>;
 393                 phy-names = "usb";
 394                 status = "disabled";
 395         };
 396
 397         usbdrd3_0: usb@fe800000 {
 398                 compatible = "rockchip,rk3399-dwc3";
 399                 #address-cells = <2>;
 400                 #size-cells = <2>;
 401                 ranges;
 402                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 403                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 404                 clock-names = "ref_clk", "suspend_clk",
 405                               "bus_clk", "grf_clk";
 406                 status = "disabled";
 407
 408                 usbdrd_dwc3_0: usb@fe800000 {
 409                         compatible = "snps,dwc3";
 410                         reg = <0x0 0xfe800000 0x0 0x100000>;
 411                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 412                         dr_mode = "otg";
 413                         phys = <&u2phy0_otg>;
 414                         phy-names = "usb2-phy";
 415                         phy_type = "utmi_wide";
 416                         snps,dis_enblslpm_quirk;
 417                         snps,dis-u2-freeclk-exists-quirk;
 418                         snps,dis_u2_susphy_quirk;
 419                         snps,dis-del-phy-power-chg-quirk;
 420                         snps,dis-tx-ipgap-linecheck-quirk;
 421                         status = "disabled";
 422                 };
 423         };
 424
 425         usbdrd3_1: usb@fe900000 {
 426                 compatible = "rockchip,rk3399-dwc3";
 427                 #address-cells = <2>;
 428                 #size-cells = <2>;
 429                 ranges;
 430                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 431                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 432                 clock-names = "ref_clk", "suspend_clk",
 433                               "bus_clk", "grf_clk";
 434                 status = "disabled";
 435
 436                 usbdrd_dwc3_1: usb@fe900000 {
 437                         compatible = "snps,dwc3";
 438                         reg = <0x0 0xfe900000 0x0 0x100000>;
 439                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 440                         dr_mode = "otg";
 441                         phys = <&u2phy1_otg>;
 442                         phy-names = "usb2-phy";
 443                         phy_type = "utmi_wide";
 444                         snps,dis_enblslpm_quirk;
 445                         snps,dis-u2-freeclk-exists-quirk;
 446                         snps,dis_u2_susphy_quirk;
 447                         snps,dis-del-phy-power-chg-quirk;
 448                         snps,dis-tx-ipgap-linecheck-quirk;
 449                         status = "disabled";
 450                 };
 451         };
 452
 453         gic: interrupt-controller@fee00000 {
 454                 compatible = "arm,gic-v3";
 455                 #interrupt-cells = <4>;
 456                 #address-cells = <2>;
 457                 #size-cells = <2>;
 458                 ranges;
 459                 interrupt-controller;
 460
 461                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 462                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 463                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 464                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 465                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 466                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 467                 its: interrupt-controller@fee20000 {
 468                         compatible = "arm,gic-v3-its";
 469                         msi-controller;
 470                         reg = <0x0 0xfee20000 0x0 0x20000>;
 471                 };
 472
 473                 ppi-partitions {
 474                         ppi_cluster0: interrupt-partition-0 {
 475                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 476                         };
 477
 478                         ppi_cluster1: interrupt-partition-1 {
 479                                 affinity = <&cpu_b0 &cpu_b1>;
 480                         };
 481                 };
 482         };
 483
 484         saradc: saradc@ff100000 {
 485                 compatible = "rockchip,rk3399-saradc";
 486                 reg = <0x0 0xff100000 0x0 0x100>;
 487                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 488                 #io-channel-cells = <1>;
 489                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 490                 clock-names = "saradc", "apb_pclk";
 491                 resets = <&cru SRST_P_SARADC>;
 492                 reset-names = "saradc-apb";
 493                 status = "disabled";
 494         };
 495
 496         i2c1: i2c@ff110000 {
 497                 compatible = "rockchip,rk3399-i2c";
 498                 reg = <0x0 0xff110000 0x0 0x1000>;
 499                 assigned-clocks = <&cru SCLK_I2C1>;
 500                 assigned-clock-rates = <200000000>;
 501                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 502                 clock-names = "i2c", "pclk";
 503                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&i2c1_xfer>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 status = "disabled";
 509         };
 510
 511         i2c2: i2c@ff120000 {
 512                 compatible = "rockchip,rk3399-i2c";
 513                 reg = <0x0 0xff120000 0x0 0x1000>;
 514                 assigned-clocks = <&cru SCLK_I2C2>;
 515                 assigned-clock-rates = <200000000>;
 516                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 517                 clock-names = "i2c", "pclk";
 518                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&i2c2_xfer>;
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 status = "disabled";
 524         };
 525
 526         i2c3: i2c@ff130000 {
 527                 compatible = "rockchip,rk3399-i2c";
 528                 reg = <0x0 0xff130000 0x0 0x1000>;
 529                 assigned-clocks = <&cru SCLK_I2C3>;
 530                 assigned-clock-rates = <200000000>;
 531                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 532                 clock-names = "i2c", "pclk";
 533                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&i2c3_xfer>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 status = "disabled";
 539         };
 540
 541         i2c5: i2c@ff140000 {
 542                 compatible = "rockchip,rk3399-i2c";
 543                 reg = <0x0 0xff140000 0x0 0x1000>;
 544                 assigned-clocks = <&cru SCLK_I2C5>;
 545                 assigned-clock-rates = <200000000>;
 546                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 547                 clock-names = "i2c", "pclk";
 548                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&i2c5_xfer>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 status = "disabled";
 554         };
 555
 556         i2c6: i2c@ff150000 {
 557                 compatible = "rockchip,rk3399-i2c";
 558                 reg = <0x0 0xff150000 0x0 0x1000>;
 559                 assigned-clocks = <&cru SCLK_I2C6>;
 560                 assigned-clock-rates = <200000000>;
 561                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 562                 clock-names = "i2c", "pclk";
 563                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c6_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c7: i2c@ff160000 {
 572                 compatible = "rockchip,rk3399-i2c";
 573                 reg = <0x0 0xff160000 0x0 0x1000>;
 574                 assigned-clocks = <&cru SCLK_I2C7>;
 575                 assigned-clock-rates = <200000000>;
 576                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 577                 clock-names = "i2c", "pclk";
 578                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c7_xfer>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         uart0: serial@ff180000 {
 587                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 588                 reg = <0x0 0xff180000 0x0 0x100>;
 589                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 590                 clock-names = "baudclk", "apb_pclk";
 591                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 592                 reg-shift = <2>;
 593                 reg-io-width = <4>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&uart0_xfer>;
 596                 status = "disabled";
 597         };
 598
 599         uart1: serial@ff190000 {
 600                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 601                 reg = <0x0 0xff190000 0x0 0x100>;
 602                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 603                 clock-names = "baudclk", "apb_pclk";
 604                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 605                 reg-shift = <2>;
 606                 reg-io-width = <4>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&uart1_xfer>;
 609                 status = "disabled";
 610         };
 611
 612         uart2: serial@ff1a0000 {
 613                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 614                 reg = <0x0 0xff1a0000 0x0 0x100>;
 615                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 616                 clock-names = "baudclk", "apb_pclk";
 617                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 618                 reg-shift = <2>;
 619                 reg-io-width = <4>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&uart2c_xfer>;
 622                 status = "disabled";
 623         };
 624
 625         uart3: serial@ff1b0000 {
 626                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 627                 reg = <0x0 0xff1b0000 0x0 0x100>;
 628                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&uart3_xfer>;
 635                 status = "disabled";
 636         };
 637
 638         spi0: spi@ff1c0000 {
 639                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 640                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 641                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 642                 clock-names = "spiclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 status = "disabled";
 649         };
 650
 651         spi1: spi@ff1d0000 {
 652                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 653                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 654                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 655                 clock-names = "spiclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 status = "disabled";
 662         };
 663
 664         spi2: spi@ff1e0000 {
 665                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 666                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 667                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 668                 clock-names = "spiclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 status = "disabled";
 675         };
 676
 677         spi4: spi@ff1f0000 {
 678                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 679                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 680                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 681                 clock-names = "spiclk", "apb_pclk";
 682                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 status = "disabled";
 688         };
 689
 690         spi5: spi@ff200000 {
 691                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 692                 reg = <0x0 0xff200000 0x0 0x1000>;
 693                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 694                 clock-names = "spiclk", "apb_pclk";
 695                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 698                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 status = "disabled";
 702         };
 703
 704         thermal_zones: thermal-zones {
 705                 cpu_thermal: cpu {
 706                         polling-delay-passive = <100>;
 707                         polling-delay = <1000>;
 708
 709                         thermal-sensors = <&tsadc 0>;
 710
 711                         trips {
 712                                 cpu_alert0: cpu_alert0 {
 713                                         temperature = <70000>;
 714                                         hysteresis = <2000>;
 715                                         type = "passive";
 716                                 };
 717                                 cpu_alert1: cpu_alert1 {
 718                                         temperature = <75000>;
 719                                         hysteresis = <2000>;
 720                                         type = "passive";
 721                                 };
 722                                 cpu_crit: cpu_crit {
 723                                         temperature = <95000>;
 724                                         hysteresis = <2000>;
 725                                         type = "critical";
 726                                 };
 727                         };
 728
 729                         cooling-maps {
 730                                 map0 {
 731                                         trip = <&cpu_alert0>;
 732                                         cooling-device =
 733                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 734                                 };
 735                                 map1 {
 736                                         trip = <&cpu_alert1>;
 737                                         cooling-device =
 738                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 739                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 740                                 };
 741                         };
 742                 };
 743
 744                 gpu_thermal: gpu {
 745                         polling-delay-passive = <100>;
 746                         polling-delay = <1000>;
 747
 748                         thermal-sensors = <&tsadc 1>;
 749
 750                         trips {
 751                                 gpu_alert0: gpu_alert0 {
 752                                         temperature = <75000>;
 753                                         hysteresis = <2000>;
 754                                         type = "passive";
 755                                 };
 756                                 gpu_crit: gpu_crit {
 757                                         temperature = <95000>;
 758                                         hysteresis = <2000>;
 759                                         type = "critical";
 760                                 };
 761                         };
 762
 763                         cooling-maps {
 764                                 map0 {
 765                                         trip = <&gpu_alert0>;
 766                                         cooling-device =
 767                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                 };
 769                         };
 770                 };
 771         };
 772
 773         tsadc: tsadc@ff260000 {
 774                 compatible = "rockchip,rk3399-tsadc";
 775                 reg = <0x0 0xff260000 0x0 0x100>;
 776                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 777                 assigned-clocks = <&cru SCLK_TSADC>;
 778                 assigned-clock-rates = <750000>;
 779                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 780                 clock-names = "tsadc", "apb_pclk";
 781                 resets = <&cru SRST_TSADC>;
 782                 reset-names = "tsadc-apb";
 783                 rockchip,grf = <&grf>;
 784                 rockchip,hw-tshut-temp = <95000>;
 785                 pinctrl-names = "init", "default", "sleep";
 786                 pinctrl-0 = <&otp_gpio>;
 787                 pinctrl-1 = <&otp_out>;
 788                 pinctrl-2 = <&otp_gpio>;
 789                 #thermal-sensor-cells = <1>;
 790                 status = "disabled";
 791         };
 792
 793         qos_emmc: qos@ffa58000 {
 794                 compatible = "syscon";
 795                 reg = <0x0 0xffa58000 0x0 0x20>;
 796         };
 797
 798         qos_gmac: qos@ffa5c000 {
 799                 compatible = "syscon";
 800                 reg = <0x0 0xffa5c000 0x0 0x20>;
 801         };
 802
 803         qos_pcie: qos@ffa60080 {
 804                 compatible = "syscon";
 805                 reg = <0x0 0xffa60080 0x0 0x20>;
 806         };
 807
 808         qos_usb_host0: qos@ffa60100 {
 809                 compatible = "syscon";
 810                 reg = <0x0 0xffa60100 0x0 0x20>;
 811         };
 812
 813         qos_usb_host1: qos@ffa60180 {
 814                 compatible = "syscon";
 815                 reg = <0x0 0xffa60180 0x0 0x20>;
 816         };
 817
 818         qos_usb_otg0: qos@ffa70000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa70000 0x0 0x20>;
 821         };
 822
 823         qos_usb_otg1: qos@ffa70080 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa70080 0x0 0x20>;
 826         };
 827
 828         qos_sd: qos@ffa74000 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa74000 0x0 0x20>;
 831         };
 832
 833         qos_sdioaudio: qos@ffa76000 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa76000 0x0 0x20>;
 836         };
 837
 838         qos_hdcp: qos@ffa90000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa90000 0x0 0x20>;
 841         };
 842
 843         qos_iep: qos@ffa98000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa98000 0x0 0x20>;
 846         };
 847
 848         qos_isp0_m0: qos@ffaa0000 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffaa0000 0x0 0x20>;
 851         };
 852
 853         qos_isp0_m1: qos@ffaa0080 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffaa0080 0x0 0x20>;
 856         };
 857
 858         qos_isp1_m0: qos@ffaa8000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffaa8000 0x0 0x20>;
 861         };
 862
 863         qos_isp1_m1: qos@ffaa8080 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffaa8080 0x0 0x20>;
 866         };
 867
 868         qos_rga_r: qos@ffab0000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffab0000 0x0 0x20>;
 871         };
 872
 873         qos_rga_w: qos@ffab0080 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffab0080 0x0 0x20>;
 876         };
 877
 878         qos_video_m0: qos@ffab8000 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffab8000 0x0 0x20>;
 881         };
 882
 883         qos_video_m1_r: qos@ffac0000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffac0000 0x0 0x20>;
 886         };
 887
 888         qos_video_m1_w: qos@ffac0080 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffac0080 0x0 0x20>;
 891         };
 892
 893         qos_vop_big_r: qos@ffac8000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffac8000 0x0 0x20>;
 896         };
 897
 898         qos_vop_big_w: qos@ffac8080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffac8080 0x0 0x20>;
 901         };
 902
 903         qos_vop_little: qos@ffad0000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffad0000 0x0 0x20>;
 906         };
 907
 908         qos_perihp: qos@ffad8080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffad8080 0x0 0x20>;
 911         };
 912
 913         qos_gpu: qos@ffae0000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffae0000 0x0 0x20>;
 916         };
 917
 918         pmu: power-management@ff310000 {
 919                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 920                 reg = <0x0 0xff310000 0x0 0x1000>;
 921
 922                 /*
 923                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 924                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 925                  * Some of the power domains are grouped together for every
 926                  * voltage domain.
 927                  * The detail contents as below.
 928                  */
 929                 power: power-controller {
 930                         compatible = "rockchip,rk3399-power-controller";
 931                         #power-domain-cells = <1>;
 932                         #address-cells = <1>;
 933                         #size-cells = <0>;
 934
 935                         /* These power domains are grouped by VD_CENTER */
 936                         pd_iep@RK3399_PD_IEP {
 937                                 reg = <RK3399_PD_IEP>;
 938                                 clocks = <&cru ACLK_IEP>,
 939                                          <&cru HCLK_IEP>;
 940                                 pm_qos = <&qos_iep>;
 941                         };
 942                         pd_rga@RK3399_PD_RGA {
 943                                 reg = <RK3399_PD_RGA>;
 944                                 clocks = <&cru ACLK_RGA>,
 945                                          <&cru HCLK_RGA>;
 946                                 pm_qos = <&qos_rga_r>,
 947                                          <&qos_rga_w>;
 948                         };
 949                         pd_vcodec@RK3399_PD_VCODEC {
 950                                 reg = <RK3399_PD_VCODEC>;
 951                                 clocks = <&cru ACLK_VCODEC>,
 952                                          <&cru HCLK_VCODEC>;
 953                                 pm_qos = <&qos_video_m0>;
 954                         };
 955                         pd_vdu@RK3399_PD_VDU {
 956                                 reg = <RK3399_PD_VDU>;
 957                                 clocks = <&cru ACLK_VDU>,
 958                                          <&cru HCLK_VDU>;
 959                                 pm_qos = <&qos_video_m1_r>,
 960                                          <&qos_video_m1_w>;
 961                         };
 962
 963                         /* These power domains are grouped by VD_GPU */
 964                         pd_gpu@RK3399_PD_GPU {
 965                                 reg = <RK3399_PD_GPU>;
 966                                 clocks = <&cru ACLK_GPU>;
 967                                 pm_qos = <&qos_gpu>;
 968                         };
 969
 970                         /* These power domains are grouped by VD_LOGIC */
 971                         pd_edp@RK3399_PD_EDP {
 972                                 reg = <RK3399_PD_EDP>;
 973                                 clocks = <&cru PCLK_EDP_CTRL>;
 974                         };
 975                         pd_emmc@RK3399_PD_EMMC {
 976                                 reg = <RK3399_PD_EMMC>;
 977                                 clocks = <&cru ACLK_EMMC>;
 978                                 pm_qos = <&qos_emmc>;
 979                         };
 980                         pd_gmac@RK3399_PD_GMAC {
 981                                 reg = <RK3399_PD_GMAC>;
 982                                 clocks = <&cru ACLK_GMAC>,
 983                                          <&cru PCLK_GMAC>;
 984                                 pm_qos = <&qos_gmac>;
 985                         };
 986                         pd_sd@RK3399_PD_SD {
 987                                 reg = <RK3399_PD_SD>;
 988                                 clocks = <&cru HCLK_SDMMC>,
 989                                          <&cru SCLK_SDMMC>;
 990                                 pm_qos = <&qos_sd>;
 991                         };
 992                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
 993                                 reg = <RK3399_PD_SDIOAUDIO>;
 994                                 clocks = <&cru HCLK_SDIO>;
 995                                 pm_qos = <&qos_sdioaudio>;
 996                         };
 997                         pd_vio@RK3399_PD_VIO {
 998                                 reg = <RK3399_PD_VIO>;
 999                                 #address-cells = <1>;
1000                                 #size-cells = <0>;
1001
1002                                 pd_hdcp@RK3399_PD_HDCP {
1003                                         reg = <RK3399_PD_HDCP>;
1004                                         clocks = <&cru ACLK_HDCP>,
1005                                                  <&cru HCLK_HDCP>,
1006                                                  <&cru PCLK_HDCP>;
1007                                         pm_qos = <&qos_hdcp>;
1008                                 };
1009                                 pd_isp0@RK3399_PD_ISP0 {
1010                                         reg = <RK3399_PD_ISP0>;
1011                                         clocks = <&cru ACLK_ISP0>,
1012                                                  <&cru HCLK_ISP0>;
1013                                         pm_qos = <&qos_isp0_m0>,
1014                                                  <&qos_isp0_m1>;
1015                                 };
1016                                 pd_isp1@RK3399_PD_ISP1 {
1017                                         reg = <RK3399_PD_ISP1>;
1018                                         clocks = <&cru ACLK_ISP1>,
1019                                                  <&cru HCLK_ISP1>;
1020                                         pm_qos = <&qos_isp1_m0>,
1021                                                  <&qos_isp1_m1>;
1022                                 };
1023                                 pd_tcpc0@RK3399_PD_TCPC0 {
1024                                         reg = <RK3399_PD_TCPD0>;
1025                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1026                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1027                                 };
1028                                 pd_tcpc1@RK3399_PD_TCPC1 {
1029                                         reg = <RK3399_PD_TCPD1>;
1030                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1031                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1032                                 };
1033                                 pd_vo@RK3399_PD_VO {
1034                                         reg = <RK3399_PD_VO>;
1035                                         #address-cells = <1>;
1036                                         #size-cells = <0>;
1037
1038                                         pd_vopb@RK3399_PD_VOPB {
1039                                                 reg = <RK3399_PD_VOPB>;
1040                                                 clocks = <&cru ACLK_VOP0>,
1041                                                          <&cru HCLK_VOP0>;
1042                                                 pm_qos = <&qos_vop_big_r>,
1043                                                          <&qos_vop_big_w>;
1044                                         };
1045                                         pd_vopl@RK3399_PD_VOPL {
1046                                                 reg = <RK3399_PD_VOPL>;
1047                                                 clocks = <&cru ACLK_VOP1>,
1048                                                          <&cru HCLK_VOP1>;
1049                                                 pm_qos = <&qos_vop_little>;
1050                                         };
1051                                 };
1052                         };
1053                 };
1054         };
1055
1056         pmugrf: syscon@ff320000 {
1057                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1058                 reg = <0x0 0xff320000 0x0 0x1000>;
1059                 #address-cells = <1>;
1060                 #size-cells = <1>;
1061
1062                 pmu_io_domains: io-domains {
1063                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1064                         status = "disabled";
1065                 };
1066         };
1067
1068         spi3: spi@ff350000 {
1069                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1070                 reg = <0x0 0xff350000 0x0 0x1000>;
1071                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1072                 clock-names = "spiclk", "apb_pclk";
1073                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1074                 pinctrl-names = "default";
1075                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1076                 #address-cells = <1>;
1077                 #size-cells = <0>;
1078                 status = "disabled";
1079         };
1080
1081         uart4: serial@ff370000 {
1082                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1083                 reg = <0x0 0xff370000 0x0 0x100>;
1084                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1085                 clock-names = "baudclk", "apb_pclk";
1086                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1087                 reg-shift = <2>;
1088                 reg-io-width = <4>;
1089                 pinctrl-names = "default";
1090                 pinctrl-0 = <&uart4_xfer>;
1091                 status = "disabled";
1092         };
1093
1094         i2c0: i2c@ff3c0000 {
1095                 compatible = "rockchip,rk3399-i2c";
1096                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1097                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1098                 assigned-clock-rates = <200000000>;
1099                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1100                 clock-names = "i2c", "pclk";
1101                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1102                 pinctrl-names = "default";
1103                 pinctrl-0 = <&i2c0_xfer>;
1104                 #address-cells = <1>;
1105                 #size-cells = <0>;
1106                 status = "disabled";
1107         };
1108
1109         i2c4: i2c@ff3d0000 {
1110                 compatible = "rockchip,rk3399-i2c";
1111                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1112                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1113                 assigned-clock-rates = <200000000>;
1114                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1115                 clock-names = "i2c", "pclk";
1116                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1117                 pinctrl-names = "default";
1118                 pinctrl-0 = <&i2c4_xfer>;
1119                 #address-cells = <1>;
1120                 #size-cells = <0>;
1121                 status = "disabled";
1122         };
1123
1124         i2c8: i2c@ff3e0000 {
1125                 compatible = "rockchip,rk3399-i2c";
1126                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1127                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1128                 assigned-clock-rates = <200000000>;
1129                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1130                 clock-names = "i2c", "pclk";
1131                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1132                 pinctrl-names = "default";
1133                 pinctrl-0 = <&i2c8_xfer>;
1134                 #address-cells = <1>;
1135                 #size-cells = <0>;
1136                 status = "disabled";
1137         };
1138
1139         pwm0: pwm@ff420000 {
1140                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1141                 reg = <0x0 0xff420000 0x0 0x10>;
1142                 #pwm-cells = <3>;
1143                 pinctrl-names = "default";
1144                 pinctrl-0 = <&pwm0_pin>;
1145                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1146                 clock-names = "pwm";
1147                 status = "disabled";
1148         };
1149
1150         pwm1: pwm@ff420010 {
1151                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1152                 reg = <0x0 0xff420010 0x0 0x10>;
1153                 #pwm-cells = <3>;
1154                 pinctrl-names = "default";
1155                 pinctrl-0 = <&pwm1_pin>;
1156                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1157                 clock-names = "pwm";
1158                 status = "disabled";
1159         };
1160
1161         pwm2: pwm@ff420020 {
1162                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1163                 reg = <0x0 0xff420020 0x0 0x10>;
1164                 #pwm-cells = <3>;
1165                 pinctrl-names = "default";
1166                 pinctrl-0 = <&pwm2_pin>;
1167                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1168                 clock-names = "pwm";
1169                 status = "disabled";
1170         };
1171
1172         pwm3: pwm@ff420030 {
1173                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1174                 reg = <0x0 0xff420030 0x0 0x10>;
1175                 #pwm-cells = <3>;
1176                 pinctrl-names = "default";
1177                 pinctrl-0 = <&pwm3a_pin>;
1178                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1179                 clock-names = "pwm";
1180                 status = "disabled";
1181         };
1182
1183         vpu_mmu: iommu@ff650800 {
1184                 compatible = "rockchip,iommu";
1185                 reg = <0x0 0xff650800 0x0 0x40>;
1186                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1187                 interrupt-names = "vpu_mmu";
1188                 #iommu-cells = <0>;
1189                 status = "disabled";
1190         };
1191
1192         vdec_mmu: iommu@ff660480 {
1193                 compatible = "rockchip,iommu";
1194                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1195                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1196                 interrupt-names = "vdec_mmu";
1197                 #iommu-cells = <0>;
1198                 status = "disabled";
1199         };
1200
1201         iep_mmu: iommu@ff670800 {
1202                 compatible = "rockchip,iommu";
1203                 reg = <0x0 0xff670800 0x0 0x40>;
1204                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1205                 interrupt-names = "iep_mmu";
1206                 #iommu-cells = <0>;
1207                 status = "disabled";
1208         };
1209
1210         efuse0: efuse@ff690000 {
1211                 compatible = "rockchip,rk3399-efuse";
1212                 reg = <0x0 0xff690000 0x0 0x80>;
1213                 #address-cells = <1>;
1214                 #size-cells = <1>;
1215                 clocks = <&cru PCLK_EFUSE1024NS>;
1216                 clock-names = "pclk_efuse";
1217
1218                 /* Data cells */
1219                 cpu_id: cpu-id@7 {
1220                         reg = <0x07 0x10>;
1221                 };
1222                 cpub_leakage: cpu-leakage@17 {
1223                         reg = <0x17 0x1>;
1224                 };
1225                 gpu_leakage: gpu-leakage@18 {
1226                         reg = <0x18 0x1>;
1227                 };
1228                 center_leakage: center-leakage@19 {
1229                         reg = <0x19 0x1>;
1230                 };
1231                 cpul_leakage: cpu-leakage@1a {
1232                         reg = <0x1a 0x1>;
1233                 };
1234                 logic_leakage: logic-leakage@1b {
1235                         reg = <0x1b 0x1>;
1236                 };
1237                 wafer_info: wafer-info@1c {
1238                         reg = <0x1c 0x1>;
1239                 };
1240         };
1241
1242         pmucru: pmu-clock-controller@ff750000 {
1243                 compatible = "rockchip,rk3399-pmucru";
1244                 reg = <0x0 0xff750000 0x0 0x1000>;
1245                 rockchip,grf = <&pmugrf>;
1246                 #clock-cells = <1>;
1247                 #reset-cells = <1>;
1248                 assigned-clocks = <&pmucru PLL_PPLL>;
1249                 assigned-clock-rates = <676000000>;
1250         };
1251
1252         cru: clock-controller@ff760000 {
1253                 compatible = "rockchip,rk3399-cru";
1254                 reg = <0x0 0xff760000 0x0 0x1000>;
1255                 rockchip,grf = <&grf>;
1256                 #clock-cells = <1>;
1257                 #reset-cells = <1>;
1258                 assigned-clocks =
1259                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1260                         <&cru PLL_NPLL>,
1261                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1262                         <&cru PCLK_PERIHP>,
1263                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1264                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1265                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1266                 assigned-clock-rates =
1267                          <594000000>,  <800000000>,
1268                         <1000000000>,
1269                          <150000000>,   <75000000>,
1270                           <37500000>,
1271                          <100000000>,  <100000000>,
1272                           <50000000>, <600000000>,
1273                          <100000000>,   <50000000>;
1274         };
1275
1276         grf: syscon@ff770000 {
1277                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1278                 reg = <0x0 0xff770000 0x0 0x10000>;
1279                 #address-cells = <1>;
1280                 #size-cells = <1>;
1281
1282                 io_domains: io-domains {
1283                         compatible = "rockchip,rk3399-io-voltage-domain";
1284                         status = "disabled";
1285                 };
1286
1287                 u2phy0: usb2-phy@e450 {
1288                         compatible = "rockchip,rk3399-usb2phy";
1289                         reg = <0xe450 0x10>;
1290                         clocks = <&cru SCLK_USB2PHY0_REF>;
1291                         clock-names = "phyclk";
1292                         #clock-cells = <0>;
1293                         clock-output-names = "clk_usbphy0_480m";
1294                         status = "disabled";
1295
1296                         u2phy0_host: host-port {
1297                                 #phy-cells = <0>;
1298                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1299                                 interrupt-names = "linestate";
1300                                 status = "disabled";
1301                         };
1302
1303                         u2phy0_otg: otg-port {
1304                                 #phy-cells = <0>;
1305                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1306                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1307                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1308                                 interrupt-names = "otg-bvalid", "otg-id",
1309                                                   "linestate";
1310                                 status = "disabled";
1311                         };
1312                 };
1313
1314                 u2phy1: usb2-phy@e460 {
1315                         compatible = "rockchip,rk3399-usb2phy";
1316                         reg = <0xe460 0x10>;
1317                         clocks = <&cru SCLK_USB2PHY1_REF>;
1318                         clock-names = "phyclk";
1319                         #clock-cells = <0>;
1320                         clock-output-names = "clk_usbphy1_480m";
1321                         status = "disabled";
1322
1323                         u2phy1_host: host-port {
1324                                 #phy-cells = <0>;
1325                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1326                                 interrupt-names = "linestate";
1327                                 status = "disabled";
1328                         };
1329
1330                         u2phy1_otg: otg-port {
1331                                 #phy-cells = <0>;
1332                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1333                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1334                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1335                                 interrupt-names = "otg-bvalid", "otg-id",
1336                                                   "linestate";
1337                                 status = "disabled";
1338                         };
1339                 };
1340
1341                 emmc_phy: phy@f780 {
1342                         compatible = "rockchip,rk3399-emmc-phy";
1343                         reg = <0xf780 0x24>;
1344                         clocks = <&sdhci>;
1345                         clock-names = "emmcclk";
1346                         #phy-cells = <0>;
1347                         status = "disabled";
1348                 };
1349
1350                 pcie_phy: pcie-phy {
1351                         compatible = "rockchip,rk3399-pcie-phy";
1352                         clocks = <&cru SCLK_PCIEPHY_REF>;
1353                         clock-names = "refclk";
1354                         #phy-cells = <1>;
1355                         resets = <&cru SRST_PCIEPHY>;
1356                         reset-names = "phy";
1357                         status = "disabled";
1358                 };
1359         };
1360
1361         tcphy0: phy@ff7c0000 {
1362                 compatible = "rockchip,rk3399-typec-phy";
1363                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1364                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1365                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1366                 clock-names = "tcpdcore", "tcpdphy-ref";
1367                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1368                 assigned-clock-rates = <50000000>;
1369                 power-domains = <&power RK3399_PD_TCPD0>;
1370                 resets = <&cru SRST_UPHY0>,
1371                          <&cru SRST_UPHY0_PIPE_L00>,
1372                          <&cru SRST_P_UPHY0_TCPHY>;
1373                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1374                 rockchip,grf = <&grf>;
1375                 rockchip,typec-conn-dir = <0xe580 0 16>;
1376                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1377                 rockchip,external-psm = <0xe588 14 30>;
1378                 rockchip,pipe-status = <0xe5c0 0 0>;
1379                 status = "disabled";
1380
1381                 tcphy0_dp: dp-port {
1382                         #phy-cells = <0>;
1383                 };
1384
1385                 tcphy0_usb3: usb3-port {
1386                         #phy-cells = <0>;
1387                 };
1388         };
1389
1390         tcphy1: phy@ff800000 {
1391                 compatible = "rockchip,rk3399-typec-phy";
1392                 reg = <0x0 0xff800000 0x0 0x40000>;
1393                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1394                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1395                 clock-names = "tcpdcore", "tcpdphy-ref";
1396                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1397                 assigned-clock-rates = <50000000>;
1398                 power-domains = <&power RK3399_PD_TCPD1>;
1399                 resets = <&cru SRST_UPHY1>,
1400                          <&cru SRST_UPHY1_PIPE_L00>,
1401                          <&cru SRST_P_UPHY1_TCPHY>;
1402                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1403                 rockchip,grf = <&grf>;
1404                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1405                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1406                 rockchip,external-psm = <0xe594 14 30>;
1407                 rockchip,pipe-status = <0xe5c0 16 16>;
1408                 status = "disabled";
1409
1410                 tcphy1_dp: dp-port {
1411                         #phy-cells = <0>;
1412                 };
1413
1414                 tcphy1_usb3: usb3-port {
1415                         #phy-cells = <0>;
1416                 };
1417         };
1418
1419         watchdog@ff848000 {
1420                 compatible = "snps,dw-wdt";
1421                 reg = <0x0 0xff848000 0x0 0x100>;
1422                 clocks = <&cru PCLK_WDT>;
1423                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1424         };
1425
1426         rktimer: rktimer@ff850000 {
1427                 compatible = "rockchip,rk3399-timer";
1428                 reg = <0x0 0xff850000 0x0 0x1000>;
1429                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1430                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1431                 clock-names = "pclk", "timer";
1432         };
1433
1434         spdif: spdif@ff870000 {
1435                 compatible = "rockchip,rk3399-spdif";
1436                 reg = <0x0 0xff870000 0x0 0x1000>;
1437                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1438                 dmas = <&dmac_bus 7>;
1439                 dma-names = "tx";
1440                 clock-names = "mclk", "hclk";
1441                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1442                 pinctrl-names = "default";
1443                 pinctrl-0 = <&spdif_bus>;
1444                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1445                 status = "disabled";
1446         };
1447
1448         i2s0: i2s@ff880000 {
1449                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1450                 reg = <0x0 0xff880000 0x0 0x1000>;
1451                 rockchip,grf = <&grf>;
1452                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1453                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1454                 dma-names = "tx", "rx";
1455                 clock-names = "i2s_clk", "i2s_hclk";
1456                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1457                 pinctrl-names = "default";
1458                 pinctrl-0 = <&i2s0_8ch_bus>;
1459                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1460                 status = "disabled";
1461         };
1462
1463         i2s1: i2s@ff890000 {
1464                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1465                 reg = <0x0 0xff890000 0x0 0x1000>;
1466                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1467                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1468                 dma-names = "tx", "rx";
1469                 clock-names = "i2s_clk", "i2s_hclk";
1470                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1471                 pinctrl-names = "default";
1472                 pinctrl-0 = <&i2s1_2ch_bus>;
1473                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1474                 status = "disabled";
1475         };
1476
1477         i2s2: i2s@ff8a0000 {
1478                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1479                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1480                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1481                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1482                 dma-names = "tx", "rx";
1483                 clock-names = "i2s_clk", "i2s_hclk";
1484                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1485                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1486                 status = "disabled";
1487         };
1488
1489         vopl: vop@ff8f0000 {
1490                 compatible = "rockchip,rk3399-vop-lit";
1491                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1492                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1493                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1494                 assigned-clock-rates = <400000000>, <100000000>;
1495                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1496                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1497                 iommus = <&vopl_mmu>;
1498                 power-domains = <&power RK3399_PD_VOPL>;
1499                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1500                 reset-names = "axi", "ahb", "dclk";
1501                 status = "disabled";
1502
1503                 vopl_out: port {
1504                         #address-cells = <1>;
1505                         #size-cells = <0>;
1506
1507                         vopl_out_mipi: endpoint@0 {
1508                                 reg = <0>;
1509                                 remote-endpoint = <&mipi_in_vopl>;
1510                         };
1511
1512                         vopl_out_edp: endpoint@1 {
1513                                 reg = <1>;
1514                                 remote-endpoint = <&edp_in_vopl>;
1515                         };
1516
1517                         vopl_out_hdmi: endpoint@2 {
1518                                 reg = <2>;
1519                                 remote-endpoint = <&hdmi_in_vopl>;
1520                         };
1521                 };
1522         };
1523
1524         vopl_mmu: iommu@ff8f3f00 {
1525                 compatible = "rockchip,iommu";
1526                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1527                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1528                 interrupt-names = "vopl_mmu";
1529                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1530                 clock-names = "aclk", "hclk";
1531                 power-domains = <&power RK3399_PD_VOPL>;
1532                 #iommu-cells = <0>;
1533                 status = "disabled";
1534         };
1535
1536         vopb: vop@ff900000 {
1537                 compatible = "rockchip,rk3399-vop-big";
1538                 reg = <0x0 0xff900000 0x0 0x3efc>;
1539                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1540                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1541                 assigned-clock-rates = <400000000>, <100000000>;
1542                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1543                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1544                 iommus = <&vopb_mmu>;
1545                 power-domains = <&power RK3399_PD_VOPB>;
1546                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1547                 reset-names = "axi", "ahb", "dclk";
1548                 status = "disabled";
1549
1550                 vopb_out: port {
1551                         #address-cells = <1>;
1552                         #size-cells = <0>;
1553
1554                         vopb_out_edp: endpoint@0 {
1555                                 reg = <0>;
1556                                 remote-endpoint = <&edp_in_vopb>;
1557                         };
1558
1559                         vopb_out_mipi: endpoint@1 {
1560                                 reg = <1>;
1561                                 remote-endpoint = <&mipi_in_vopb>;
1562                         };
1563
1564                         vopb_out_hdmi: endpoint@2 {
1565                                 reg = <2>;
1566                                 remote-endpoint = <&hdmi_in_vopb>;
1567                         };
1568                 };
1569         };
1570
1571         vopb_mmu: iommu@ff903f00 {
1572                 compatible = "rockchip,iommu";
1573                 reg = <0x0 0xff903f00 0x0 0x100>;
1574                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1575                 interrupt-names = "vopb_mmu";
1576                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1577                 clock-names = "aclk", "hclk";
1578                 power-domains = <&power RK3399_PD_VOPB>;
1579                 #iommu-cells = <0>;
1580                 status = "disabled";
1581         };
1582
1583         isp0_mmu: iommu@ff914000 {
1584                 compatible = "rockchip,iommu";
1585                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1586                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1587                 interrupt-names = "isp0_mmu";
1588                 #iommu-cells = <0>;
1589                 rockchip,disable-mmu-reset;
1590                 status = "disabled";
1591         };
1592
1593         isp1_mmu: iommu@ff924000 {
1594                 compatible = "rockchip,iommu";
1595                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1596                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1597                 interrupt-names = "isp1_mmu";
1598                 #iommu-cells = <0>;
1599                 rockchip,disable-mmu-reset;
1600                 status = "disabled";
1601         };
1602
1603         hdmi: hdmi@ff940000 {
1604                 compatible = "rockchip,rk3399-dw-hdmi";
1605                 reg = <0x0 0xff940000 0x0 0x20000>;
1606                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1607                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1608                 clock-names = "iahb", "isfr", "vpll", "grf";
1609                 power-domains = <&power RK3399_PD_HDCP>;
1610                 reg-io-width = <4>;
1611                 rockchip,grf = <&grf>;
1612                 status = "disabled";
1613
1614                 ports {
1615                         hdmi_in: port {
1616                                 #address-cells = <1>;
1617                                 #size-cells = <0>;
1618
1619                                 hdmi_in_vopb: endpoint@0 {
1620                                         reg = <0>;
1621                                         remote-endpoint = <&vopb_out_hdmi>;
1622                                 };
1623                                 hdmi_in_vopl: endpoint@1 {
1624                                         reg = <1>;
1625                                         remote-endpoint = <&vopl_out_hdmi>;
1626                                 };
1627                         };
1628                 };
1629         };
1630
1631         mipi_dsi: mipi@ff960000 {
1632                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1633                 reg = <0x0 0xff960000 0x0 0x8000>;
1634                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1635                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1636                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1637                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1638                 power-domains = <&power RK3399_PD_VIO>;
1639                 rockchip,grf = <&grf>;
1640                 status = "disabled";
1641
1642                 ports {
1643                         mipi_in: port {
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646
1647                                 mipi_in_vopb: endpoint@0 {
1648                                         reg = <0>;
1649                                         remote-endpoint = <&vopb_out_mipi>;
1650                                 };
1651                                 mipi_in_vopl: endpoint@1 {
1652                                         reg = <1>;
1653                                         remote-endpoint = <&vopl_out_mipi>;
1654                                 };
1655                         };
1656                 };
1657         };
1658
1659         edp: edp@ff970000 {
1660                 compatible = "rockchip,rk3399-edp";
1661                 reg = <0x0 0xff970000 0x0 0x8000>;
1662                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1663                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1664                 clock-names = "dp", "pclk";
1665                 pinctrl-names = "default";
1666                 pinctrl-0 = <&edp_hpd>;
1667                 power-domains = <&power RK3399_PD_EDP>;
1668                 resets = <&cru SRST_P_EDP_CTRL>;
1669                 reset-names = "dp";
1670                 rockchip,grf = <&grf>;
1671                 status = "disabled";
1672
1673                 ports {
1674                         #address-cells = <1>;
1675                         #size-cells = <0>;
1676                         edp_in: port@0 {
1677                                 reg = <0>;
1678                                 #address-cells = <1>;
1679                                 #size-cells = <0>;
1680
1681                                 edp_in_vopb: endpoint@0 {
1682                                         reg = <0>;
1683                                         remote-endpoint = <&vopb_out_edp>;
1684                                 };
1685
1686                                 edp_in_vopl: endpoint@1 {
1687                                         reg = <1>;
1688                                         remote-endpoint = <&vopl_out_edp>;
1689                                 };
1690                         };
1691                 };
1692         };
1693
1694         gpu: gpu@ff9a0000 {
1695                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1696                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1697                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1698                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1699                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1700                 interrupt-names = "job", "mmu", "gpu";
1701                 clocks = <&cru ACLK_GPU>;
1702                 power-domains = <&power RK3399_PD_GPU>;
1703                 status = "disabled";
1704         };
1705
1706         pinctrl: pinctrl {
1707                 compatible = "rockchip,rk3399-pinctrl";
1708                 rockchip,grf = <&grf>;
1709                 rockchip,pmu = <&pmugrf>;
1710                 #address-cells = <2>;
1711                 #size-cells = <2>;
1712                 ranges;
1713
1714                 gpio0: gpio0@ff720000 {
1715                         compatible = "rockchip,gpio-bank";
1716                         reg = <0x0 0xff720000 0x0 0x100>;
1717                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1718                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1719
1720                         gpio-controller;
1721                         #gpio-cells = <0x2>;
1722
1723                         interrupt-controller;
1724                         #interrupt-cells = <0x2>;
1725                 };
1726
1727                 gpio1: gpio1@ff730000 {
1728                         compatible = "rockchip,gpio-bank";
1729                         reg = <0x0 0xff730000 0x0 0x100>;
1730                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1731                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1732
1733                         gpio-controller;
1734                         #gpio-cells = <0x2>;
1735
1736                         interrupt-controller;
1737                         #interrupt-cells = <0x2>;
1738                 };
1739
1740                 gpio2: gpio2@ff780000 {
1741                         compatible = "rockchip,gpio-bank";
1742                         reg = <0x0 0xff780000 0x0 0x100>;
1743                         clocks = <&cru PCLK_GPIO2>;
1744                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1745
1746                         gpio-controller;
1747                         #gpio-cells = <0x2>;
1748
1749                         interrupt-controller;
1750                         #interrupt-cells = <0x2>;
1751                 };
1752
1753                 gpio3: gpio3@ff788000 {
1754                         compatible = "rockchip,gpio-bank";
1755                         reg = <0x0 0xff788000 0x0 0x100>;
1756                         clocks = <&cru PCLK_GPIO3>;
1757                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1758
1759                         gpio-controller;
1760                         #gpio-cells = <0x2>;
1761
1762                         interrupt-controller;
1763                         #interrupt-cells = <0x2>;
1764                 };
1765
1766                 gpio4: gpio4@ff790000 {
1767                         compatible = "rockchip,gpio-bank";
1768                         reg = <0x0 0xff790000 0x0 0x100>;
1769                         clocks = <&cru PCLK_GPIO4>;
1770                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1771
1772                         gpio-controller;
1773                         #gpio-cells = <0x2>;
1774
1775                         interrupt-controller;
1776                         #interrupt-cells = <0x2>;
1777                 };
1778
1779                 pcfg_pull_up: pcfg-pull-up {
1780                         bias-pull-up;
1781                 };
1782
1783                 pcfg_pull_down: pcfg-pull-down {
1784                         bias-pull-down;
1785                 };
1786
1787                 pcfg_pull_none: pcfg-pull-none {
1788                         bias-disable;
1789                 };
1790
1791                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1792                         bias-disable;
1793                         drive-strength = <12>;
1794                 };
1795
1796                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1797                         bias-pull-up;
1798                         drive-strength = <8>;
1799                 };
1800
1801                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1802                         bias-pull-down;
1803                         drive-strength = <4>;
1804                 };
1805
1806                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1807                         bias-pull-up;
1808                         drive-strength = <2>;
1809                 };
1810
1811                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1812                         bias-pull-down;
1813                         drive-strength = <12>;
1814                 };
1815
1816                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1817                         bias-disable;
1818                         drive-strength = <13>;
1819                 };
1820
1821                 clock {
1822                         clk_32k: clk-32k {
1823                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 edp {
1828                         edp_hpd: edp-hpd {
1829                                 rockchip,pins =
1830                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832                 };
1833
1834                 gmac {
1835                         rgmii_pins: rgmii-pins {
1836                                 rockchip,pins =
1837                                         /* mac_txclk */
1838                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1839                                         /* mac_rxclk */
1840                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1841                                         /* mac_mdio */
1842                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1843                                         /* mac_txen */
1844                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1845                                         /* mac_clk */
1846                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1847                                         /* mac_rxdv */
1848                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1849                                         /* mac_mdc */
1850                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1851                                         /* mac_rxd1 */
1852                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1853                                         /* mac_rxd0 */
1854                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1855                                         /* mac_txd1 */
1856                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1857                                         /* mac_txd0 */
1858                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1859                                         /* mac_rxd3 */
1860                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1861                                         /* mac_rxd2 */
1862                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1863                                         /* mac_txd3 */
1864                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1865                                         /* mac_txd2 */
1866                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1867                         };
1868
1869                         rmii_pins: rmii-pins {
1870                                 rockchip,pins =
1871                                         /* mac_mdio */
1872                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1873                                         /* mac_txen */
1874                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1875                                         /* mac_clk */
1876                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1877                                         /* mac_rxer */
1878                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1879                                         /* mac_rxdv */
1880                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1881                                         /* mac_mdc */
1882                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1883                                         /* mac_rxd1 */
1884                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1885                                         /* mac_rxd0 */
1886                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1887                                         /* mac_txd1 */
1888                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1889                                         /* mac_txd0 */
1890                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1891                         };
1892                 };
1893
1894                 i2c0 {
1895                         i2c0_xfer: i2c0-xfer {
1896                                 rockchip,pins =
1897                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1898                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1899                         };
1900                 };
1901
1902                 i2c1 {
1903                         i2c1_xfer: i2c1-xfer {
1904                                 rockchip,pins =
1905                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1906                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1907                         };
1908                 };
1909
1910                 i2c2 {
1911                         i2c2_xfer: i2c2-xfer {
1912                                 rockchip,pins =
1913                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1914                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1915                         };
1916                 };
1917
1918                 i2c3 {
1919                         i2c3_xfer: i2c3-xfer {
1920                                 rockchip,pins =
1921                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1922                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1923                         };
1924                 };
1925
1926                 i2c4 {
1927                         i2c4_xfer: i2c4-xfer {
1928                                 rockchip,pins =
1929                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1930                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1931                         };
1932                 };
1933
1934                 i2c5 {
1935                         i2c5_xfer: i2c5-xfer {
1936                                 rockchip,pins =
1937                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1938                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1939                         };
1940                 };
1941
1942                 i2c6 {
1943                         i2c6_xfer: i2c6-xfer {
1944                                 rockchip,pins =
1945                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1946                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1947                         };
1948                 };
1949
1950                 i2c7 {
1951                         i2c7_xfer: i2c7-xfer {
1952                                 rockchip,pins =
1953                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1954                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1955                         };
1956                 };
1957
1958                 i2c8 {
1959                         i2c8_xfer: i2c8-xfer {
1960                                 rockchip,pins =
1961                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1962                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1963                         };
1964                 };
1965
1966                 i2s0 {
1967                         i2s0_8ch_bus: i2s0-8ch-bus {
1968                                 rockchip,pins =
1969                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1970                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1971                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1972                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1973                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1974                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1975                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1976                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1977                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1978                         };
1979                 };
1980
1981                 i2s1 {
1982                         i2s1_2ch_bus: i2s1-2ch-bus {
1983                                 rockchip,pins =
1984                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1985                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1986                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1987                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1988                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1989                         };
1990                 };
1991
1992                 sdio0 {
1993                         sdio0_bus1: sdio0-bus1 {
1994                                 rockchip,pins =
1995                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
1996                         };
1997
1998                         sdio0_bus4: sdio0-bus4 {
1999                                 rockchip,pins =
2000                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2001                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2002                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2003                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2004                         };
2005
2006                         sdio0_cmd: sdio0-cmd {
2007                                 rockchip,pins =
2008                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010
2011                         sdio0_clk: sdio0-clk {
2012                                 rockchip,pins =
2013                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2014                         };
2015
2016                         sdio0_cd: sdio0-cd {
2017                                 rockchip,pins =
2018                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2019                         };
2020
2021                         sdio0_pwr: sdio0-pwr {
2022                                 rockchip,pins =
2023                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2024                         };
2025
2026                         sdio0_bkpwr: sdio0-bkpwr {
2027                                 rockchip,pins =
2028                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2029                         };
2030
2031                         sdio0_wp: sdio0-wp {
2032                                 rockchip,pins =
2033                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2034                         };
2035
2036                         sdio0_int: sdio0-int {
2037                                 rockchip,pins =
2038                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2039                         };
2040                 };
2041
2042                 sdmmc {
2043                         sdmmc_bus1: sdmmc-bus1 {
2044                                 rockchip,pins =
2045                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2046                         };
2047
2048                         sdmmc_bus4: sdmmc-bus4 {
2049                                 rockchip,pins =
2050                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2051                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2052                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2053                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2054                         };
2055
2056                         sdmmc_clk: sdmmc-clk {
2057                                 rockchip,pins =
2058                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2059                         };
2060
2061                         sdmmc_cmd: sdmmc-cmd {
2062                                 rockchip,pins =
2063                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2064                         };
2065
2066                         sdmmc_cd: sdmmc-cd {
2067                                 rockchip,pins =
2068                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2069                         };
2070
2071                         sdmmc_wp: sdmmc-wp {
2072                                 rockchip,pins =
2073                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2074                         };
2075                 };
2076
2077                 suspend {
2078                         ap_pwroff: ap-pwroff {
2079                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2080                         };
2081
2082                         ddrio_pwroff: ddrio-pwroff {
2083                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2084                         };
2085                 };
2086
2087                 spdif {
2088                         spdif_bus: spdif-bus {
2089                                 rockchip,pins =
2090                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2091                         };
2092
2093                         spdif_bus_1: spdif-bus-1 {
2094                                 rockchip,pins =
2095                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2096                         };
2097                 };
2098
2099                 spi0 {
2100                         spi0_clk: spi0-clk {
2101                                 rockchip,pins =
2102                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2103                         };
2104                         spi0_cs0: spi0-cs0 {
2105                                 rockchip,pins =
2106                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2107                         };
2108                         spi0_cs1: spi0-cs1 {
2109                                 rockchip,pins =
2110                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2111                         };
2112                         spi0_tx: spi0-tx {
2113                                 rockchip,pins =
2114                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2115                         };
2116                         spi0_rx: spi0-rx {
2117                                 rockchip,pins =
2118                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2119                         };
2120                 };
2121
2122                 spi1 {
2123                         spi1_clk: spi1-clk {
2124                                 rockchip,pins =
2125                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2126                         };
2127                         spi1_cs0: spi1-cs0 {
2128                                 rockchip,pins =
2129                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2130                         };
2131                         spi1_rx: spi1-rx {
2132                                 rockchip,pins =
2133                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2134                         };
2135                         spi1_tx: spi1-tx {
2136                                 rockchip,pins =
2137                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2138                         };
2139                 };
2140
2141                 spi2 {
2142                         spi2_clk: spi2-clk {
2143                                 rockchip,pins =
2144                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2145                         };
2146                         spi2_cs0: spi2-cs0 {
2147                                 rockchip,pins =
2148                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2149                         };
2150                         spi2_rx: spi2-rx {
2151                                 rockchip,pins =
2152                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2153                         };
2154                         spi2_tx: spi2-tx {
2155                                 rockchip,pins =
2156                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2157                         };
2158                 };
2159
2160                 spi3 {
2161                         spi3_clk: spi3-clk {
2162                                 rockchip,pins =
2163                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2164                         };
2165                         spi3_cs0: spi3-cs0 {
2166                                 rockchip,pins =
2167                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2168                         };
2169                         spi3_rx: spi3-rx {
2170                                 rockchip,pins =
2171                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2172                         };
2173                         spi3_tx: spi3-tx {
2174                                 rockchip,pins =
2175                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2176                         };
2177                 };
2178
2179                 spi4 {
2180                         spi4_clk: spi4-clk {
2181                                 rockchip,pins =
2182                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2183                         };
2184                         spi4_cs0: spi4-cs0 {
2185                                 rockchip,pins =
2186                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2187                         };
2188                         spi4_rx: spi4-rx {
2189                                 rockchip,pins =
2190                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2191                         };
2192                         spi4_tx: spi4-tx {
2193                                 rockchip,pins =
2194                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2195                         };
2196                 };
2197
2198                 spi5 {
2199                         spi5_clk: spi5-clk {
2200                                 rockchip,pins =
2201                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2202                         };
2203                         spi5_cs0: spi5-cs0 {
2204                                 rockchip,pins =
2205                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2206                         };
2207                         spi5_rx: spi5-rx {
2208                                 rockchip,pins =
2209                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2210                         };
2211                         spi5_tx: spi5-tx {
2212                                 rockchip,pins =
2213                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2214                         };
2215                 };
2216
2217                 tsadc {
2218                         otp_gpio: otp-gpio {
2219                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2220                         };
2221
2222                         otp_out: otp-out {
2223                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2224                         };
2225                 };
2226
2227                 uart0 {
2228                         uart0_xfer: uart0-xfer {
2229                                 rockchip,pins =
2230                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2231                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2232                         };
2233
2234                         uart0_cts: uart0-cts {
2235                                 rockchip,pins =
2236                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2237                         };
2238
2239                         uart0_rts: uart0-rts {
2240                                 rockchip,pins =
2241                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2242                         };
2243                 };
2244
2245                 uart1 {
2246                         uart1_xfer: uart1-xfer {
2247                                 rockchip,pins =
2248                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2249                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2250                         };
2251                 };
2252
2253                 uart2a {
2254                         uart2a_xfer: uart2a-xfer {
2255                                 rockchip,pins =
2256                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2257                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2258                         };
2259                 };
2260
2261                 uart2b {
2262                         uart2b_xfer: uart2b-xfer {
2263                                 rockchip,pins =
2264                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2265                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2266                         };
2267                 };
2268
2269                 uart2c {
2270                         uart2c_xfer: uart2c-xfer {
2271                                 rockchip,pins =
2272                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2273                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2274                         };
2275                 };
2276
2277                 uart3 {
2278                         uart3_xfer: uart3-xfer {
2279                                 rockchip,pins =
2280                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2281                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2282                         };
2283
2284                         uart3_cts: uart3-cts {
2285                                 rockchip,pins =
2286                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2287                         };
2288
2289                         uart3_rts: uart3-rts {
2290                                 rockchip,pins =
2291                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2292                         };
2293                 };
2294
2295                 uart4 {
2296                         uart4_xfer: uart4-xfer {
2297                                 rockchip,pins =
2298                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2299                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2300                         };
2301                 };
2302
2303                 uarthdcp {
2304                         uarthdcp_xfer: uarthdcp-xfer {
2305                                 rockchip,pins =
2306                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2307                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2308                         };
2309                 };
2310
2311                 pwm0 {
2312                         pwm0_pin: pwm0-pin {
2313                                 rockchip,pins =
2314                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2315                         };
2316
2317                         vop0_pwm_pin: vop0-pwm-pin {
2318                                 rockchip,pins =
2319                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2320                         };
2321                 };
2322
2323                 pwm1 {
2324                         pwm1_pin: pwm1-pin {
2325                                 rockchip,pins =
2326                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2327                         };
2328
2329                         vop1_pwm_pin: vop1-pwm-pin {
2330                                 rockchip,pins =
2331                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2332                         };
2333                 };
2334
2335                 pwm2 {
2336                         pwm2_pin: pwm2-pin {
2337                                 rockchip,pins =
2338                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2339                         };
2340                 };
2341
2342                 pwm3a {
2343                         pwm3a_pin: pwm3a-pin {
2344                                 rockchip,pins =
2345                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2346                         };
2347                 };
2348
2349                 pwm3b {
2350                         pwm3b_pin: pwm3b-pin {
2351                                 rockchip,pins =
2352                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2353                         };
2354                 };
2355
2356                 hdmi {
2357                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2358                                 rockchip,pins =
2359                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2360                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2361                         };
2362
2363                         hdmi_cec: hdmi-cec {
2364                                 rockchip,pins =
2365                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2366                         };
2367                 };
2368
2369                 pcie {
2370                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2371                                 rockchip,pins =
2372                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2373                         };
2374
2375                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2376                                 rockchip,pins =
2377                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2378                         };
2379                 };
2380
2381         };
2382 };