2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "dt-bindings/pwm/pwm.h"
44 #include "rk3399.dtsi"
45 #include "rk3399-opp.dtsi"
48 compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
50 backlight: backlight {
51 compatible = "pwm-backlight";
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84 248 249 250 251 252 253 254 255>;
85 default-brightness-level = <200>;
86 pwms = <&pwm0 0 25000 0>;
89 clkin_gmac: external-gmac-clock {
90 compatible = "fixed-clock";
91 clock-frequency = <125000000>;
92 clock-output-names = "clkin_gmac";
97 compatible = "regulator-fixed";
98 regulator-name = "dc_12v";
101 regulator-min-microvolt = <12000000>;
102 regulator-max-microvolt = <12000000>;
105 /* switched by pmic_sleep */
106 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
107 compatible = "regulator-fixed";
108 regulator-name = "vcc1v8_s3";
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>;
113 vin-supply = <&vcc_1v8>;
116 vcc3v0_sd: vcc3v0-sd {
117 compatible = "regulator-fixed";
119 gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&sdmmc0_pwr_h>;
123 regulator-max-microvolt = <3000000>;
124 regulator-min-microvolt = <3000000>;
125 regulator-name = "vcc3v0_sd";
126 vin-supply = <&vcc3v3_sys>;
129 vcc3v3_sys: vcc3v3-sys {
130 compatible = "regulator-fixed";
131 regulator-name = "vcc3v3_sys";
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
136 vin-supply = <&vcc_sys>;
140 compatible = "regulator-fixed";
141 regulator-name = "vcc_sys";
144 regulator-min-microvolt = <5000000>;
145 regulator-max-microvolt = <5000000>;
146 vin-supply = <&dc_12v>;
149 vcc5v0_host: vcc5v0-host-regulator {
150 compatible = "regulator-fixed";
152 gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&vcc5v0_host_en>;
155 regulator-name = "vcc5v0_host";
157 vin-supply = <&vcc_sys>;
162 cpu-supply = <&vdd_cpu_l>;
166 cpu-supply = <&vdd_cpu_l>;
170 cpu-supply = <&vdd_cpu_l>;
174 cpu-supply = <&vdd_cpu_l>;
178 cpu-supply = <&vdd_cpu_b>;
182 cpu-supply = <&vdd_cpu_b>;
190 assigned-clocks = <&cru SCLK_RMII_SRC>;
191 assigned-clock-parents = <&clkin_gmac>;
192 clock_in_out = "input";
193 phy-supply = <&vcc_lan>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&rgmii_pins>;
197 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
198 snps,reset-active-low;
199 snps,reset-delays-us = <0 10000 50000>;
206 mali-supply = <&vdd_gpu>;
211 ddc-i2c-bus = <&i2c3>;
216 clock-frequency = <400000>;
217 i2c-scl-rising-time-ns = <168>;
218 i2c-scl-falling-time-ns = <4>;
222 compatible = "rockchip,rk808";
224 interrupt-parent = <&gpio1>;
225 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
227 clock-output-names = "xin32k", "rk808-clkout2";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
230 rockchip,system-power-controller;
233 vcc1-supply = <&vcc_sys>;
234 vcc2-supply = <&vcc_sys>;
235 vcc3-supply = <&vcc_sys>;
236 vcc4-supply = <&vcc_sys>;
237 vcc6-supply = <&vcc_sys>;
238 vcc7-supply = <&vcc_sys>;
239 vcc8-supply = <&vcc3v3_sys>;
240 vcc9-supply = <&vcc_sys>;
241 vcc10-supply = <&vcc_sys>;
242 vcc11-supply = <&vcc_sys>;
243 vcc12-supply = <&vcc3v3_sys>;
244 vddio-supply = <&vcc1v8_pmu>;
247 vdd_center: DCDC_REG1 {
248 regulator-name = "vdd_center";
251 regulator-min-microvolt = <750000>;
252 regulator-max-microvolt = <1350000>;
253 regulator-ramp-delay = <6001>;
254 regulator-state-mem {
255 regulator-off-in-suspend;
259 vdd_cpu_l: DCDC_REG2 {
260 regulator-name = "vdd_cpu_l";
263 regulator-min-microvolt = <750000>;
264 regulator-max-microvolt = <1350000>;
265 regulator-ramp-delay = <6001>;
266 regulator-state-mem {
267 regulator-off-in-suspend;
272 regulator-name = "vcc_ddr";
275 regulator-state-mem {
276 regulator-on-in-suspend;
281 regulator-name = "vcc_1v8";
284 regulator-min-microvolt = <1800000>;
285 regulator-max-microvolt = <1800000>;
286 regulator-state-mem {
287 regulator-on-in-suspend;
288 regulator-suspend-microvolt = <1800000>;
292 vcc1v8_dvp: LDO_REG1 {
293 regulator-name = "vcc1v8_dvp";
296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <1800000>;
298 regulator-state-mem {
299 regulator-off-in-suspend;
303 vcc3v0_tp: LDO_REG2 {
304 regulator-name = "vcc3v0_tp";
307 regulator-min-microvolt = <3000000>;
308 regulator-max-microvolt = <3000000>;
309 regulator-state-mem {
310 regulator-off-in-suspend;
314 vcc1v8_pmu: LDO_REG3 {
315 regulator-name = "vcc1v8_pmu";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <1800000>;
320 regulator-state-mem {
321 regulator-on-in-suspend;
322 regulator-suspend-microvolt = <1800000>;
327 regulator-name = "vcc_sdio";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-state-mem {
333 regulator-on-in-suspend;
334 regulator-suspend-microvolt = <3000000>;
338 vcca3v0_codec: LDO_REG5 {
339 regulator-name = "vcca3v0_codec";
342 regulator-min-microvolt = <3000000>;
343 regulator-max-microvolt = <3000000>;
344 regulator-state-mem {
345 regulator-off-in-suspend;
350 regulator-name = "vcc_1v5";
353 regulator-min-microvolt = <1500000>;
354 regulator-max-microvolt = <1500000>;
355 regulator-state-mem {
356 regulator-on-in-suspend;
357 regulator-suspend-microvolt = <1500000>;
361 vcca1v8_codec: LDO_REG7 {
362 regulator-name = "vcca1v8_codec";
365 regulator-min-microvolt = <1800000>;
366 regulator-max-microvolt = <1800000>;
367 regulator-state-mem {
368 regulator-off-in-suspend;
373 regulator-name = "vcc_3v0";
376 regulator-min-microvolt = <3000000>;
377 regulator-max-microvolt = <3000000>;
378 regulator-state-mem {
379 regulator-on-in-suspend;
380 regulator-suspend-microvolt = <3000000>;
384 vcc3v3_s3: vcc_lan: SWITCH_REG1 {
385 regulator-name = "vcc3v3_s3";
388 regulator-state-mem {
389 regulator-off-in-suspend;
393 vcc3v3_s0: SWITCH_REG2 {
394 regulator-name = "vcc3v3_s0";
397 regulator-state-mem {
398 regulator-off-in-suspend;
404 vdd_cpu_b: regulator@40 {
405 compatible = "silergy,syr827";
407 fcs,suspend-voltage-selector = <1>;
408 regulator-name = "vdd_cpu_b";
409 regulator-min-microvolt = <712500>;
410 regulator-max-microvolt = <1500000>;
411 regulator-ramp-delay = <1000>;
414 vin-supply = <&vcc_sys>;
416 regulator-state-mem {
417 regulator-off-in-suspend;
421 vdd_gpu: regulator@41 {
422 compatible = "silergy,syr828";
424 fcs,suspend-voltage-selector = <1>;
425 regulator-name = "vdd_gpu";
426 regulator-min-microvolt = <712500>;
427 regulator-max-microvolt = <1500000>;
428 regulator-ramp-delay = <1000>;
431 vin-supply = <&vcc_sys>;
433 regulator-state-mem {
434 regulator-off-in-suspend;
439 compatible = "pwm-regulator";
440 pwms = <&pwm2 0 25000 1>;
441 regulator-name = "vdd_log";
444 regulator-min-microvolt = <800000>;
445 regulator-max-microvolt = <1400000>;
446 vin-supply = <&vcc_sys>;
451 i2c-scl-rising-time-ns = <450>;
452 i2c-scl-falling-time-ns = <15>;
459 bt656-supply = <&vcc_3v0>;
460 audio-supply = <&vcca1v8_codec>;
461 sdmmc-supply = <&vcc_sdio>;
462 gpio1830-supply = <&vcc_3v0>;
470 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
471 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
472 assigned-clock-rates = <100000000>;
473 ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pcie_clkreqn_cpm>;
481 pmu1830-supply = <&vcc_3v0>;
487 pmic_int_l: pmic-int-l {
489 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
492 pmic_dvs2: pmic-dvs2 {
494 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
497 vsel1_gpio: vsel1-gpio {
498 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
501 vsel2_gpio: vsel2-gpio {
502 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
507 sdmmc0_pwr_h: sdmmc0-pwr-h {
509 <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
514 vcc5v0_host_en: vcc5v0-host-en {
516 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
530 vref-supply = <&vcca1v8_s3>;
536 keep-power-in-suspend;
538 mmc-hs400-enhanced-strobe;
547 clock-frequency = <50000000>;
549 keep-power-in-suspend;
550 max-frequency = <50000000>;
551 mmc-pwrseq = <&sdio_pwrseq>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
564 clock-frequency = <150000000>;
566 max-frequency = <150000000>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
569 vmmc-supply = <&vcc3v0_sd>;
570 vqmmc-supply = <&vcc_sdio>;
575 /* tshut mode 0:CRU 1:GPIO */
576 rockchip,hw-tshut-mode = <1>;
577 /* tshut polarity 0:LOW 1:HIGH */
578 rockchip,hw-tshut-polarity = <1>;
585 u2phy0_otg: otg-port {
589 u2phy0_host: host-port {
590 phy-supply = <&vcc5v0_host>;
598 u2phy1_otg: otg-port {
602 u2phy1_host: host-port {
603 phy-supply = <&vcc5v0_host>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&uart0_xfer &uart0_cts>;