1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Martijn Braam <martijn@brixit.nl>
4 * Copyright (c) 2021 Kamil TrzciĆski <ayufan@ayufan.eu>
8 * PinePhone Pro datasheet:
9 * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/linux-event-codes.h>
15 #include "rk3399.dtsi"
16 #include "rk3399-opp.dtsi"
19 model = "Pine64 PinePhonePro";
20 compatible = "pine64,pinephone-pro", "rockchip,rk3399";
21 chassis-type = "handset";
30 stdout-path = "serial2:115200n8";
34 compatible = "adc-keys";
35 io-channels = <&saradc 1>;
36 io-channel-names = "buttons";
37 keyup-threshold-microvolt = <1600000>;
38 poll-interval = <100>;
42 linux,code = <KEY_VOLUMEUP>;
43 press-threshold-microvolt = <100000>;
47 label = "Volume Down";
48 linux,code = <KEY_VOLUMEDOWN>;
49 press-threshold-microvolt = <600000>;
53 backlight: backlight {
54 compatible = "pwm-backlight";
55 pwms = <&pwm0 0 50000 0>;
59 compatible = "gpio-keys";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pwrbtn_pin>;
64 debounce-interval = <20>;
65 gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
67 linux,code = <KEY_POWER>;
72 vcc_sys: vcc-sys-regulator {
73 compatible = "regulator-fixed";
74 regulator-name = "vcc_sys";
79 vcc3v3_sys: vcc3v3-sys-regulator {
80 compatible = "regulator-fixed";
81 regulator-name = "vcc3v3_sys";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 vin-supply = <&vcc_sys>;
89 vcca1v8_s3: vcc1v8-s3-regulator {
90 compatible = "regulator-fixed";
91 regulator-name = "vcca1v8_s3";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 vin-supply = <&vcc3v3_sys>;
99 vcc1v8_codec: vcc1v8-codec-regulator {
100 compatible = "regulator-fixed";
102 gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&vcc1v8_codec_en>;
105 regulator-name = "vcc1v8_codec";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 vin-supply = <&vcc3v3_sys>;
111 wifi_pwrseq: sdio-wifi-pwrseq {
112 compatible = "mmc-pwrseq-simple";
114 clock-names = "ext_clock";
115 pinctrl-names = "default";
116 pinctrl-0 = <&wifi_enable_h_pin>;
118 * Wait between power-on and SDIO access for CYP43455
121 post-power-on-delay-ms = <110>;
123 * Wait between consecutive toggles for CYP43455 CBUCK
124 * regulator discharge.
126 power-off-delay-us = <10000>;
128 /* WL_REG_ON on module */
129 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
132 /* MIPI DSI panel 1.8v supply */
133 vcc1v8_lcd: vcc1v8-lcd {
134 compatible = "regulator-fixed";
136 regulator-name = "vcc1v8_lcd";
137 regulator-min-microvolt = <1800000>;
138 regulator-max-microvolt = <1800000>;
139 vin-supply = <&vcc3v3_sys>;
140 gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
141 pinctrl-names = "default";
144 /* MIPI DSI panel 2.8v supply */
145 vcc2v8_lcd: vcc2v8-lcd {
146 compatible = "regulator-fixed";
148 regulator-name = "vcc2v8_lcd";
149 regulator-min-microvolt = <2800000>;
150 regulator-max-microvolt = <2800000>;
151 vin-supply = <&vcc3v3_sys>;
152 gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
153 pinctrl-names = "default";
158 temperature = <65000>;
161 temperature = <68000>;
165 cpu-supply = <&vdd_cpu_l>;
169 cpu-supply = <&vdd_cpu_l>;
173 cpu-supply = <&vdd_cpu_l>;
177 cpu-supply = <&vdd_cpu_l>;
181 cpu-supply = <&vdd_cpu_b>;
185 cpu-supply = <&vdd_cpu_b>;
193 mali-supply = <&vdd_gpu>;
198 clock-frequency = <400000>;
199 i2c-scl-rising-time-ns = <168>;
200 i2c-scl-falling-time-ns = <4>;
204 compatible = "rockchip,rk818";
206 interrupt-parent = <&gpio1>;
207 interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
209 clock-output-names = "xin32k", "rk808-clkout2";
210 pinctrl-names = "default";
211 pinctrl-0 = <&pmic_int_l>;
212 rockchip,system-power-controller;
215 vcc1-supply = <&vcc_sys>;
216 vcc2-supply = <&vcc_sys>;
217 vcc3-supply = <&vcc_sys>;
218 vcc4-supply = <&vcc_sys>;
219 vcc6-supply = <&vcc_sys>;
220 vcc7-supply = <&vcc3v3_sys>;
221 vcc8-supply = <&vcc_sys>;
222 vcc9-supply = <&vcc3v3_sys>;
225 vdd_cpu_l: DCDC_REG1 {
226 regulator-name = "vdd_cpu_l";
229 regulator-min-microvolt = <875000>;
230 regulator-max-microvolt = <975000>;
231 regulator-ramp-delay = <6001>;
232 regulator-state-mem {
233 regulator-off-in-suspend;
237 vdd_center: DCDC_REG2 {
238 regulator-name = "vdd_center";
241 regulator-min-microvolt = <800000>;
242 regulator-max-microvolt = <1000000>;
243 regulator-ramp-delay = <6001>;
244 regulator-state-mem {
245 regulator-off-in-suspend;
250 regulator-name = "vcc_ddr";
253 regulator-state-mem {
254 regulator-on-in-suspend;
259 regulator-name = "vcc_1v8";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 regulator-state-mem {
265 regulator-on-in-suspend;
269 vcca3v0_codec: LDO_REG1 {
270 regulator-name = "vcca3v0_codec";
271 regulator-min-microvolt = <3000000>;
272 regulator-max-microvolt = <3000000>;
275 vcc3v0_touch: LDO_REG2 {
276 regulator-name = "vcc3v0_touch";
277 regulator-min-microvolt = <3000000>;
278 regulator-max-microvolt = <3000000>;
281 vcca1v8_codec: LDO_REG3 {
282 regulator-name = "vcca1v8_codec";
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <1800000>;
287 rk818_pwr_on: LDO_REG4 {
288 regulator-name = "rk818_pwr_on";
291 regulator-min-microvolt = <3300000>;
292 regulator-max-microvolt = <3300000>;
293 regulator-state-mem {
294 regulator-on-in-suspend;
299 regulator-name = "vcc_3v0";
302 regulator-min-microvolt = <3000000>;
303 regulator-max-microvolt = <3000000>;
304 regulator-state-mem {
305 regulator-on-in-suspend;
310 regulator-name = "vcc_1v5";
313 regulator-min-microvolt = <1500000>;
314 regulator-max-microvolt = <1500000>;
315 regulator-state-mem {
316 regulator-on-in-suspend;
320 vcc1v8_dvp: LDO_REG7 {
321 regulator-name = "vcc1v8_dvp";
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <1800000>;
326 vcc3v3_s3: LDO_REG8 {
327 regulator-name = "vcc3v3_s3";
330 regulator-min-microvolt = <3300000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-state-mem {
333 regulator-off-in-suspend;
338 regulator-name = "vccio_sd";
339 regulator-min-microvolt = <1800000>;
340 regulator-max-microvolt = <3300000>;
343 vcc3v3_s0: SWITCH_REG {
344 regulator-name = "vcc3v3_s0";
347 regulator-state-mem {
348 regulator-on-in-suspend;
354 vdd_cpu_b: regulator@40 {
355 compatible = "silergy,syr827";
357 fcs,suspend-voltage-selector = <1>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&vsel1_pin>;
360 regulator-name = "vdd_cpu_b";
361 regulator-min-microvolt = <875000>;
362 regulator-max-microvolt = <1150000>;
363 regulator-ramp-delay = <1000>;
367 regulator-state-mem {
368 regulator-off-in-suspend;
372 vdd_gpu: regulator@41 {
373 compatible = "silergy,syr828";
375 fcs,suspend-voltage-selector = <1>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&vsel2_pin>;
378 regulator-name = "vdd_gpu";
379 regulator-min-microvolt = <875000>;
380 regulator-max-microvolt = <975000>;
381 regulator-ramp-delay = <1000>;
385 regulator-state-mem {
386 regulator-off-in-suspend;
392 i2c-scl-rising-time-ns = <450>;
393 i2c-scl-falling-time-ns = <15>;
397 compatible = "goodix,gt1158";
399 interrupt-parent = <&gpio3>;
400 interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>;
401 irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
402 reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
403 AVDD28-supply = <&vcc3v0_touch>;
404 VDDIO-supply = <&vcc3v0_touch>;
405 touchscreen-size-x = <720>;
406 touchscreen-size-y = <1440>;
422 opp-hz = /bits/ 64 <1500000000>;
423 opp-microvolt = <1100000 1100000 1150000>;
432 bt656-supply = <&vcc1v8_dvp>;
433 audio-supply = <&vcca1v8_codec>;
434 sdmmc-supply = <&vccio_sd>;
435 gpio1830-supply = <&vcc_3v0>;
445 #address-cells = <0>;
449 mipi_out_panel: endpoint {
450 remote-endpoint = <&mipi_in_panel>;
456 compatible = "hannstar,hsd060bhw4";
458 backlight = <&backlight>;
459 reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
460 vcc-supply = <&vcc2v8_lcd>;
461 iovcc-supply = <&vcc1v8_lcd>;
462 pinctrl-names = "default";
465 mipi_in_panel: endpoint {
466 remote-endpoint = <&mipi_out_panel>;
473 pmu1830-supply = <&vcc_1v8>;
479 pwrbtn_pin: pwrbtn-pin {
480 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
485 pmic_int_l: pmic-int-l {
486 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
489 vsel1_pin: vsel1-pin {
490 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
493 vsel2_pin: vsel2-pin {
494 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
499 wifi_enable_h_pin: wifi-enable-h-pin {
500 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
505 vcc1v8_codec_en: vcc1v8-codec-en {
506 rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
511 bt_wake_pin: bt-wake-pin {
512 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
515 bt_host_wake_pin: bt-host-wake-pin {
516 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
519 bt_reset_pin: bt-reset-pin {
520 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
530 keep-power-in-suspend;
531 mmc-pwrseq = <&wifi_pwrseq>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
544 vref-supply = <&vcca1v8_s3>;
551 cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
553 max-frequency = <150000000>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
556 vmmc-supply = <&vcc3v3_sys>;
557 vqmmc-supply = <&vccio_sd>;
569 rockchip,hw-tshut-mode = <1>;
570 rockchip,hw-tshut-polarity = <1>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
581 compatible = "brcm,bcm4345c5";
584 device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
585 host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
586 max-speed = <1500000>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
589 shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
590 vbat-supply = <&vcc3v3_sys>;
591 vddio-supply = <&vcc_1v8>;
601 assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
602 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
603 assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
604 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
613 assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,
614 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
615 assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
616 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;