1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru (and derivatives) board device tree source
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 stdout-path = "serial2:115200n8";
20 * In general an attempt is made to include all rails called out by
21 * the schematic as long as those rails interact in some way with
23 * - Rails that only connect to the EC (or devices that the EC talks to)
25 * - Rails _are_ included if the rails go to the AP even if the AP
26 * doesn't currently care about them / they are always on. The idea
27 * here is that it makes it easier to map to the schematic or extend
30 * If two rails are substantially the same from the AP's point of
31 * view, though, we won't create a full fixed regulator. We'll just
32 * put the child rail as an alias of the parent rail. Sometimes rails
33 * look the same to the AP because one of these is true:
34 * - The EC controls the enable and the EC always enables a rail as
35 * long as the AP is running.
36 * - The rails are actually connected to each other by a jumper and
37 * the distinction is just there to add clarity/flexibility to the
41 ppvar_sys: ppvar-sys {
42 compatible = "regulator-fixed";
43 regulator-name = "ppvar_sys";
48 pp1200_lpddr: pp1200-lpddr {
49 compatible = "regulator-fixed";
50 regulator-name = "pp1200_lpddr";
52 /* EC turns on w/ lpddr_pwr_en; always on for AP */
55 regulator-min-microvolt = <1200000>;
56 regulator-max-microvolt = <1200000>;
58 vin-supply = <&ppvar_sys>;
62 compatible = "regulator-fixed";
63 regulator-name = "pp1800";
65 /* Always on when ppvar_sys shows power good */
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <1800000>;
71 vin-supply = <&ppvar_sys>;
75 compatible = "regulator-fixed";
76 regulator-name = "pp3300";
78 /* Always on; plain and simple */
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
84 vin-supply = <&ppvar_sys>;
88 compatible = "regulator-fixed";
89 regulator-name = "pp5000";
91 /* EC turns on w/ pp5000_en; always on for AP */
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
97 vin-supply = <&ppvar_sys>;
100 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
101 compatible = "pwm-regulator";
102 regulator-name = "ppvar_bigcpu_pwm";
104 pwms = <&pwm1 0 3337 0>;
105 pwm-supply = <&ppvar_sys>;
106 pwm-dutycycle-range = <100 0>;
107 pwm-dutycycle-unit = <100>;
109 /* EC turns on w/ ap_core_en; always on for AP */
112 regulator-min-microvolt = <800107>;
113 regulator-max-microvolt = <1302232>;
116 ppvar_bigcpu: ppvar-bigcpu {
117 compatible = "vctrl-regulator";
118 regulator-name = "ppvar_bigcpu";
120 regulator-min-microvolt = <800107>;
121 regulator-max-microvolt = <1302232>;
123 ctrl-supply = <&ppvar_bigcpu_pwm>;
124 ctrl-voltage-range = <800107 1302232>;
126 regulator-settling-time-up-us = <322>;
129 ppvar_litcpu_pwm: ppvar-litcpu-pwm {
130 compatible = "pwm-regulator";
131 regulator-name = "ppvar_litcpu_pwm";
133 pwms = <&pwm2 0 3337 0>;
134 pwm-supply = <&ppvar_sys>;
135 pwm-dutycycle-range = <100 0>;
136 pwm-dutycycle-unit = <100>;
138 /* EC turns on w/ ap_core_en; always on for AP */
141 regulator-min-microvolt = <797743>;
142 regulator-max-microvolt = <1307837>;
145 ppvar_litcpu: ppvar-litcpu {
146 compatible = "vctrl-regulator";
147 regulator-name = "ppvar_litcpu";
149 regulator-min-microvolt = <797743>;
150 regulator-max-microvolt = <1307837>;
152 ctrl-supply = <&ppvar_litcpu_pwm>;
153 ctrl-voltage-range = <797743 1307837>;
155 regulator-settling-time-up-us = <384>;
158 ppvar_gpu_pwm: ppvar-gpu-pwm {
159 compatible = "pwm-regulator";
160 regulator-name = "ppvar_gpu_pwm";
162 pwms = <&pwm0 0 3337 0>;
163 pwm-supply = <&ppvar_sys>;
164 pwm-dutycycle-range = <100 0>;
165 pwm-dutycycle-unit = <100>;
167 /* EC turns on w/ ap_core_en; always on for AP */
170 regulator-min-microvolt = <786384>;
171 regulator-max-microvolt = <1217747>;
174 ppvar_gpu: ppvar-gpu {
175 compatible = "vctrl-regulator";
176 regulator-name = "ppvar_gpu";
178 regulator-min-microvolt = <786384>;
179 regulator-max-microvolt = <1217747>;
181 ctrl-supply = <&ppvar_gpu_pwm>;
182 ctrl-voltage-range = <786384 1217747>;
184 regulator-settling-time-up-us = <390>;
187 /* EC turns on w/ pp900_ddrpll_en */
188 pp900_ddrpll: pp900-ap {
191 /* EC turns on w/ pp900_pll_en */
192 pp900_pll: pp900-ap {
195 /* EC turns on w/ pp900_pmu_en */
196 pp900_pmu: pp900-ap {
199 /* EC turns on w/ pp1800_s0_en_l */
200 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
203 /* EC turns on w/ pp1800_avdd_en_l */
204 pp1800_avdd: pp1800 {
207 /* EC turns on w/ pp1800_lid_en_l */
208 pp1800_lid: pp1800_mic: pp1800 {
211 /* EC turns on w/ lpddr_pwr_en */
212 pp1800_lpddr: pp1800 {
215 /* EC turns on w/ pp1800_pmu_en_l */
219 /* EC turns on w/ pp1800_usb_en_l */
223 pp3000_sd_slot: pp3000-sd-slot {
224 compatible = "regulator-fixed";
225 regulator-name = "pp3000_sd_slot";
226 pinctrl-names = "default";
227 pinctrl-0 = <&sd_slot_pwr_en>;
230 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
232 vin-supply = <&pp3000>;
236 * Technically, this is a small abuse of 'regulator-gpio'; this
237 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
238 * always on though, so it is sufficient to simply control the mux
241 ppvar_sd_card_io: ppvar-sd-card-io {
242 compatible = "regulator-gpio";
243 regulator-name = "ppvar_sd_card_io";
244 pinctrl-names = "default";
245 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
248 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
249 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
250 states = <1800000 0x1
253 regulator-min-microvolt = <1800000>;
254 regulator-max-microvolt = <3000000>;
257 /* EC turns on w/ pp3300_trackpad_en_l */
258 pp3300_trackpad: pp3300-trackpad {
261 /* EC turns on w/ usb_a_en */
262 pp5000_usb_a_vbus: pp5000 {
265 gpio_keys: gpio-keys {
266 compatible = "gpio-keys";
267 pinctrl-names = "default";
268 pinctrl-0 = <&bt_host_wake_l>;
270 wake_on_bt: wake-on-bt {
271 label = "Wake-on-Bluetooth";
272 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
273 linux,code = <KEY_WAKEUP>;
278 max98357a: max98357a {
279 compatible = "maxim,max98357a";
280 pinctrl-names = "default";
281 pinctrl-0 = <&sdmode_en>;
282 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
284 #sound-dai-cells = <0>;
289 compatible = "rockchip,rk3399-gru-sound";
290 rockchip,cpu = <&i2s0 &i2s2>;
299 * Set some suspend operating points to avoid OVP in suspend
301 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
302 * from wherever they're at back to the "default" operating point (whatever
303 * voltage we get when we set the PWM pins to "input").
305 * This quick transition under light load has the possibility to trigger the
306 * regulator "over voltage protection" (OVP).
308 * To make extra certain that we don't hit this OVP at suspend time, we'll
309 * transition to a voltage that's much closer to the default (~1.0 V) so that
310 * there will not be a big jump. Technically we only need to get within 200 mV
311 * of the default voltage, but the speed here should be fast enough and we need
312 * suspend/resume to be rock solid.
328 cpu-supply = <&ppvar_litcpu>;
332 cpu-supply = <&ppvar_litcpu>;
336 cpu-supply = <&ppvar_litcpu>;
340 cpu-supply = <&ppvar_litcpu>;
344 cpu-supply = <&ppvar_bigcpu>;
348 cpu-supply = <&ppvar_bigcpu>;
354 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
356 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
358 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
359 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
360 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
361 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
364 assigned-clock-rates =
365 <600000000>, <800000000>,
367 <150000000>, <75000000>,
369 <100000000>, <100000000>,
370 <50000000>, <800000000>,
371 <100000000>, <50000000>,
372 <400000000>, <400000000>,
382 mali-supply = <&ppvar_gpu>;
389 clock-frequency = <400000>;
391 /* These are relatively safe rise/fall times */
392 i2c-scl-falling-time-ns = <50>;
393 i2c-scl-rising-time-ns = <300>;
396 ap_i2c_audio: &i2c8 {
399 clock-frequency = <400000>;
401 /* These are relatively safe rise/fall times */
402 i2c-scl-falling-time-ns = <50>;
403 i2c-scl-rising-time-ns = <300>;
406 compatible = "dlg,da7219";
408 interrupt-parent = <&gpio1>;
409 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
410 clocks = <&cru SCLK_I2S_8CH_OUT>;
411 clock-names = "mclk";
412 dlg,micbias-lvl = <2600>;
413 dlg,mic-amp-in-sel = "diff";
414 pinctrl-names = "default";
415 pinctrl-0 = <&headset_int_l>;
416 VDD-supply = <&pp1800>;
417 VDDMIC-supply = <&pp3300>;
418 VDDIO-supply = <&pp1800>;
421 dlg,adc-1bit-rpt = <1>;
424 dlg,mic-det-thr = <500>;
425 dlg,jack-ins-deb = <20>;
426 dlg,jack-det-rate = "32ms_64ms";
427 dlg,jack-rem-deb = <1>;
429 dlg,a-d-btn-thr = <0xa>;
430 dlg,d-b-btn-thr = <0x16>;
431 dlg,b-c-btn-thr = <0x21>;
432 dlg,c-mic-btn-thr = <0x3E>;
448 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
449 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
450 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
451 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
457 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
460 vpcie3v3-supply = <&pp3300_wifi_bt>;
461 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
462 vpcie0v9-supply = <&pp900_pcie>;
464 pci_rootport: pcie@0,0 {
465 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
466 #address-cells = <3>;
479 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
500 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
501 * same (or nearly the same) performance for all eMMC that are intended
504 assigned-clock-rates = <150000000>;
508 mmc-hs400-enhanced-strobe;
517 * Note: configure "sdmmc_cd" as card detect even though it's actually
518 * hooked to ground. Because we specified "cd-gpios" below dw_mmc
519 * should be ignoring card detect anyway. Specifying the pin as
520 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
521 * turned on that the system will still make sure the port is
522 * configured as SDMMC and not JTAG.
524 pinctrl-names = "default";
525 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
531 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
537 vmmc-supply = <&pp3000_sd_slot>;
538 vqmmc-supply = <&ppvar_sd_card_io>;
544 pinctrl-names = "default", "sleep";
545 pinctrl-1 = <&spi1_sleep>;
548 compatible = "jedec,spi-nor";
551 /* May run faster once verified. */
552 spi-max-frequency = <10000000>;
564 compatible = "google,cros-ec-spi";
566 interrupt-parent = <&gpio0>;
567 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&ec_ap_int_l>;
570 spi-max-frequency = <3000000>;
572 i2c_tunnel: i2c-tunnel {
573 compatible = "google,cros-ec-i2c-tunnel";
574 google,remote-bus = <4>;
575 #address-cells = <1>;
579 usbc_extcon0: extcon@0 {
580 compatible = "google,extcon-usbc-cros-ec";
581 google,usb-port-id = <0>;
591 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
592 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
597 extcon = <&usbc_extcon0>;
630 extcon = <&usbc_extcon0>;
654 #include <arm/cros-ec-keyboard.dtsi>
655 #include <arm/cros-ec-sbs.dtsi>
659 * pinctrl settings for pins that have no real owners.
661 * At the moment settings are identical for S0 and S3, but if we later
662 * need to configure things differently for S3 we'll adjust here.
664 pinctrl-names = "default";
666 &ap_pwroff /* AP will auto-assert this when in S3 */
667 &clk_32k /* This pin is always 32k on gru boards */
670 pcfg_output_low: pcfg-output-low {
674 pcfg_output_high: pcfg-output-high {
678 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
680 drive-strength = <8>;
685 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
690 ec_ap_int_l: ec-ap-int-l {
691 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
695 discrete-regulators {
696 sd_io_pwr_en: sd-io-pwr-en {
697 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
701 sd_pwr_1800_sel: sd-pwr-1800-sel {
702 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
706 sd_slot_pwr_en: sd-slot-pwr-en {
707 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
713 /* Has external pullup */
714 headset_int_l: headset-int-l {
715 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
719 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
724 sdmode_en: sdmode-en {
725 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
730 pcie_clkreqn_cpm: pci-clkreqn-cpm {
732 * Since our pcie doesn't support ClockPM(CPM), we want
733 * to hack this as gpio, so the EP could be able to
734 * de-assert it along and make ClockPM(CPM) work.
736 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
742 * We run sdmmc at max speed; bump up drive strength.
743 * We also have external pulls, so disable the internal ones.
745 sdmmc_bus4: sdmmc-bus4 {
747 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
748 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
749 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
750 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
753 sdmmc_clk: sdmmc-clk {
755 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
758 sdmmc_cmd: sdmmc-cmd {
760 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
764 * In our case the official card detect is hooked to ground
765 * to avoid getting access to JTAG just by sticking something
766 * in the SD card slot (see the force_jtag bit in the TRM).
768 * We still configure it as card detect because it doesn't
769 * hurt and dw_mmc will ignore it. We make sure to disable
770 * the pull though so we don't burn needless power.
774 <0 7 RK_FUNC_1 &pcfg_pull_none>;
777 /* This is where we actually hook up CD; has external pull */
778 sdmmc_cd_gpio: sdmmc-cd-gpio {
779 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
784 spi1_sleep: spi1-sleep {
786 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
789 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
790 <1 10 RK_FUNC_GPIO &pcfg_pull_down>,
791 <1 7 RK_FUNC_GPIO &pcfg_pull_down>,
792 <1 8 RK_FUNC_GPIO &pcfg_pull_down>;
797 touch_int_l: touch-int-l {
798 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
801 touch_reset_l: touch-reset-l {
802 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
807 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
808 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
811 trackpad_int_l: trackpad-int-l {
812 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
817 wlan_module_reset_l: wlan-module-reset-l {
818 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
821 bt_host_wake_l: bt-host-wake-l {
822 /* Kevin has an external pull up, but Gru does not */
823 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
829 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;