1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru (and derivatives) board device tree source
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
25 * In general an attempt is made to include all rails called out by
26 * the schematic as long as those rails interact in some way with
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
31 * doesn't currently care about them / they are always on. The idea
32 * here is that it makes it easier to map to the schematic or extend
35 * If two rails are substantially the same from the AP's point of
36 * view, though, we won't create a full fixed regulator. We'll just
37 * put the child rail as an alias of the parent rail. Sometimes rails
38 * look the same to the AP because one of these is true:
39 * - The EC controls the enable and the EC always enables a rail as
40 * long as the AP is running.
41 * - The rails are actually connected to each other by a jumper and
42 * the distinction is just there to add clarity/flexibility to the
46 ppvar_sys: ppvar-sys {
47 compatible = "regulator-fixed";
48 regulator-name = "ppvar_sys";
53 pp1200_lpddr: pp1200-lpddr {
54 compatible = "regulator-fixed";
55 regulator-name = "pp1200_lpddr";
57 /* EC turns on w/ lpddr_pwr_en; always on for AP */
60 regulator-min-microvolt = <1200000>;
61 regulator-max-microvolt = <1200000>;
63 vin-supply = <&ppvar_sys>;
67 compatible = "regulator-fixed";
68 regulator-name = "pp1800";
70 /* Always on when ppvar_sys shows power good */
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <1800000>;
76 vin-supply = <&ppvar_sys>;
80 compatible = "regulator-fixed";
81 regulator-name = "pp3300";
83 /* Always on; plain and simple */
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
89 vin-supply = <&ppvar_sys>;
93 compatible = "regulator-fixed";
94 regulator-name = "pp5000";
96 /* EC turns on w/ pp5000_en; always on for AP */
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
102 vin-supply = <&ppvar_sys>;
105 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
106 compatible = "pwm-regulator";
107 regulator-name = "ppvar_bigcpu_pwm";
109 pwms = <&pwm1 0 3337 0>;
110 pwm-supply = <&ppvar_sys>;
111 pwm-dutycycle-range = <100 0>;
112 pwm-dutycycle-unit = <100>;
114 /* EC turns on w/ ap_core_en; always on for AP */
117 regulator-min-microvolt = <800107>;
118 regulator-max-microvolt = <1302232>;
121 ppvar_bigcpu: ppvar-bigcpu {
122 compatible = "vctrl-regulator";
123 regulator-name = "ppvar_bigcpu";
125 regulator-min-microvolt = <800107>;
126 regulator-max-microvolt = <1302232>;
128 ctrl-supply = <&ppvar_bigcpu_pwm>;
129 ctrl-voltage-range = <800107 1302232>;
131 regulator-settling-time-up-us = <322>;
134 ppvar_litcpu_pwm: ppvar-litcpu-pwm {
135 compatible = "pwm-regulator";
136 regulator-name = "ppvar_litcpu_pwm";
138 pwms = <&pwm2 0 3337 0>;
139 pwm-supply = <&ppvar_sys>;
140 pwm-dutycycle-range = <100 0>;
141 pwm-dutycycle-unit = <100>;
143 /* EC turns on w/ ap_core_en; always on for AP */
146 regulator-min-microvolt = <797743>;
147 regulator-max-microvolt = <1307837>;
150 ppvar_litcpu: ppvar-litcpu {
151 compatible = "vctrl-regulator";
152 regulator-name = "ppvar_litcpu";
154 regulator-min-microvolt = <797743>;
155 regulator-max-microvolt = <1307837>;
157 ctrl-supply = <&ppvar_litcpu_pwm>;
158 ctrl-voltage-range = <797743 1307837>;
160 regulator-settling-time-up-us = <384>;
163 ppvar_gpu_pwm: ppvar-gpu-pwm {
164 compatible = "pwm-regulator";
165 regulator-name = "ppvar_gpu_pwm";
167 pwms = <&pwm0 0 3337 0>;
168 pwm-supply = <&ppvar_sys>;
169 pwm-dutycycle-range = <100 0>;
170 pwm-dutycycle-unit = <100>;
172 /* EC turns on w/ ap_core_en; always on for AP */
175 regulator-min-microvolt = <786384>;
176 regulator-max-microvolt = <1217747>;
179 ppvar_gpu: ppvar-gpu {
180 compatible = "vctrl-regulator";
181 regulator-name = "ppvar_gpu";
183 regulator-min-microvolt = <786384>;
184 regulator-max-microvolt = <1217747>;
186 ctrl-supply = <&ppvar_gpu_pwm>;
187 ctrl-voltage-range = <786384 1217747>;
189 regulator-settling-time-up-us = <390>;
192 /* EC turns on w/ pp900_ddrpll_en */
193 pp900_ddrpll: pp900-ap {
196 /* EC turns on w/ pp900_pll_en */
197 pp900_pll: pp900-ap {
200 /* EC turns on w/ pp900_pmu_en */
201 pp900_pmu: pp900-ap {
204 /* EC turns on w/ pp1800_s0_en_l */
205 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
208 /* EC turns on w/ pp1800_avdd_en_l */
209 pp1800_avdd: pp1800 {
212 /* EC turns on w/ pp1800_lid_en_l */
213 pp1800_lid: pp1800_mic: pp1800 {
216 /* EC turns on w/ lpddr_pwr_en */
217 pp1800_lpddr: pp1800 {
220 /* EC turns on w/ pp1800_pmu_en_l */
224 /* EC turns on w/ pp1800_usb_en_l */
228 pp3000_sd_slot: pp3000-sd-slot {
229 compatible = "regulator-fixed";
230 regulator-name = "pp3000_sd_slot";
231 pinctrl-names = "default";
232 pinctrl-0 = <&sd_slot_pwr_en>;
235 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
237 vin-supply = <&pp3000>;
241 * Technically, this is a small abuse of 'regulator-gpio'; this
242 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
243 * always on though, so it is sufficient to simply control the mux
246 ppvar_sd_card_io: ppvar-sd-card-io {
247 compatible = "regulator-gpio";
248 regulator-name = "ppvar_sd_card_io";
249 pinctrl-names = "default";
250 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
253 enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
254 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
255 states = <1800000 0x1>,
258 regulator-min-microvolt = <1800000>;
259 regulator-max-microvolt = <3000000>;
262 /* EC turns on w/ pp3300_trackpad_en_l */
263 pp3300_trackpad: pp3300-trackpad {
266 /* EC turns on w/ usb_a_en */
267 pp5000_usb_a_vbus: pp5000 {
270 ap_rtc_clk: ap-rtc-clk {
271 compatible = "fixed-clock";
272 clock-frequency = <32768>;
273 clock-output-names = "xin32k";
277 max98357a: max98357a {
278 compatible = "maxim,max98357a";
279 pinctrl-names = "default";
280 pinctrl-0 = <&sdmode_en>;
281 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
283 #sound-dai-cells = <0>;
288 compatible = "rockchip,rk3399-gru-sound";
289 rockchip,cpu = <&i2s0 &spdif>;
298 * Set some suspend operating points to avoid OVP in suspend
300 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
301 * from wherever they're at back to the "default" operating point (whatever
302 * voltage we get when we set the PWM pins to "input").
304 * This quick transition under light load has the possibility to trigger the
305 * regulator "over voltage protection" (OVP).
307 * To make extra certain that we don't hit this OVP at suspend time, we'll
308 * transition to a voltage that's much closer to the default (~1.0 V) so that
309 * there will not be a big jump. Technically we only need to get within 200 mV
310 * of the default voltage, but the speed here should be fast enough and we need
311 * suspend/resume to be rock solid.
327 cpu-supply = <&ppvar_litcpu>;
331 cpu-supply = <&ppvar_litcpu>;
335 cpu-supply = <&ppvar_litcpu>;
339 cpu-supply = <&ppvar_litcpu>;
343 cpu-supply = <&ppvar_bigcpu>;
347 cpu-supply = <&ppvar_bigcpu>;
353 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
355 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
357 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
358 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
359 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
360 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
363 assigned-clock-rates =
364 <600000000>, <800000000>,
366 <150000000>, <75000000>,
368 <100000000>, <100000000>,
369 <50000000>, <800000000>,
370 <100000000>, <50000000>,
371 <400000000>, <400000000>,
383 rockchip,pd-idle-ns = <160>;
384 rockchip,sr-idle-ns = <10240>;
385 rockchip,sr-mc-gate-idle-ns = <40960>;
386 rockchip,srpd-lite-idle-ns = <61440>;
387 rockchip,standby-idle-ns = <81920>;
389 rockchip,ddr3_odt_dis_freq = <666000000>;
390 rockchip,lpddr3_odt_dis_freq = <666000000>;
391 rockchip,lpddr4_odt_dis_freq = <666000000>;
393 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
394 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
395 rockchip,standby-idle-dis-freq-hz = <928000000>;
409 mali-supply = <&ppvar_gpu>;
416 clock-frequency = <400000>;
418 /* These are relatively safe rise/fall times */
419 i2c-scl-falling-time-ns = <50>;
420 i2c-scl-rising-time-ns = <300>;
423 ap_i2c_audio: &i2c8 {
426 clock-frequency = <400000>;
428 /* These are relatively safe rise/fall times */
429 i2c-scl-falling-time-ns = <50>;
430 i2c-scl-rising-time-ns = <300>;
433 compatible = "dlg,da7219";
435 interrupt-parent = <&gpio1>;
436 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
437 clocks = <&cru SCLK_I2S_8CH_OUT>;
438 clock-names = "mclk";
439 dlg,micbias-lvl = <2600>;
440 dlg,mic-amp-in-sel = "diff";
441 pinctrl-names = "default";
442 pinctrl-0 = <&headset_int_l>;
443 VDD-supply = <&pp1800>;
444 VDDMIC-supply = <&pp3300>;
445 VDDIO-supply = <&pp1800>;
448 dlg,adc-1bit-rpt = <1>;
451 dlg,mic-det-thr = <500>;
452 dlg,jack-ins-deb = <20>;
453 dlg,jack-det-rate = "32ms_64ms";
454 dlg,jack-rem-deb = <1>;
456 dlg,a-d-btn-thr = <0xa>;
457 dlg,d-b-btn-thr = <0x16>;
458 dlg,b-c-btn-thr = <0x21>;
459 dlg,c-mic-btn-thr = <0x3E>;
471 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
472 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
473 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
474 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
480 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
483 vpcie3v3-supply = <&pp3300_wifi_bt>;
484 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
485 vpcie0v9-supply = <&pp900_pcie>;
487 pci_rootport: pcie@0,0 {
488 reg = <0x0000 0 0 0 0>;
489 #address-cells = <3>;
503 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
524 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
525 * same (or nearly the same) performance for all eMMC that are intended
528 assigned-clock-rates = <150000000>;
532 mmc-hs400-enhanced-strobe;
541 * Note: configure "sdmmc_cd" as card detect even though it's actually
542 * hooked to ground. Because we specified "cd-gpios" below dw_mmc
543 * should be ignoring card detect anyway. Specifying the pin as
544 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
545 * turned on that the system will still make sure the port is
546 * configured as SDMMC and not JTAG.
548 pinctrl-names = "default";
549 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
555 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
561 vmmc-supply = <&pp3000_sd_slot>;
562 vqmmc-supply = <&ppvar_sd_card_io>;
569 * SPDIF is routed internally to DP; we either don't use these pins, or
570 * mux them to something else.
572 /delete-property/ pinctrl-0;
573 /delete-property/ pinctrl-names;
579 pinctrl-names = "default", "sleep";
580 pinctrl-1 = <&spi1_sleep>;
583 compatible = "jedec,spi-nor";
586 /* May run faster once verified. */
587 spi-max-frequency = <10000000>;
599 compatible = "google,cros-ec-spi";
601 interrupt-parent = <&gpio0>;
602 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&ec_ap_int_l>;
605 spi-max-frequency = <3000000>;
607 i2c_tunnel: i2c-tunnel {
608 compatible = "google,cros-ec-i2c-tunnel";
609 google,remote-bus = <4>;
610 #address-cells = <1>;
614 usbc_extcon0: extcon0 {
615 compatible = "google,extcon-usbc-cros-ec";
616 google,usb-port-id = <0>;
624 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
625 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
630 extcon = <&usbc_extcon0>;
663 extcon = <&usbc_extcon0>;
687 #include <arm/cros-ec-keyboard.dtsi>
688 #include <arm/cros-ec-sbs.dtsi>
692 * pinctrl settings for pins that have no real owners.
694 * At the moment settings are identical for S0 and S3, but if we later
695 * need to configure things differently for S3 we'll adjust here.
697 pinctrl-names = "default";
699 &ap_pwroff /* AP will auto-assert this when in S3 */
700 &clk_32k /* This pin is always 32k on gru boards */
703 pcfg_output_low: pcfg-output-low {
707 pcfg_output_high: pcfg-output-high {
711 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
713 drive-strength = <8>;
718 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
723 ec_ap_int_l: ec-ap-int-l {
724 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
728 discrete-regulators {
729 sd_io_pwr_en: sd-io-pwr-en {
730 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
734 sd_pwr_1800_sel: sd-pwr-1800-sel {
735 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
739 sd_slot_pwr_en: sd-slot-pwr-en {
740 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
746 /* Has external pullup */
747 headset_int_l: headset-int-l {
748 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
752 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
757 sdmode_en: sdmode-en {
758 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
763 pcie_clkreqn_cpm: pci-clkreqn-cpm {
765 * Since our pcie doesn't support ClockPM(CPM), we want
766 * to hack this as gpio, so the EP could be able to
767 * de-assert it along and make ClockPM(CPM) work.
769 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
775 * We run sdmmc at max speed; bump up drive strength.
776 * We also have external pulls, so disable the internal ones.
778 sdmmc_bus4: sdmmc-bus4 {
780 <4 RK_PB0 1 &pcfg_pull_none_8ma>,
781 <4 RK_PB1 1 &pcfg_pull_none_8ma>,
782 <4 RK_PB2 1 &pcfg_pull_none_8ma>,
783 <4 RK_PB3 1 &pcfg_pull_none_8ma>;
786 sdmmc_clk: sdmmc-clk {
788 <4 RK_PB4 1 &pcfg_pull_none_8ma>;
791 sdmmc_cmd: sdmmc-cmd {
793 <4 RK_PB5 1 &pcfg_pull_none_8ma>;
797 * In our case the official card detect is hooked to ground
798 * to avoid getting access to JTAG just by sticking something
799 * in the SD card slot (see the force_jtag bit in the TRM).
801 * We still configure it as card detect because it doesn't
802 * hurt and dw_mmc will ignore it. We make sure to disable
803 * the pull though so we don't burn needless power.
807 <0 RK_PA7 1 &pcfg_pull_none>;
810 /* This is where we actually hook up CD; has external pull */
811 sdmmc_cd_pin: sdmmc-cd-pin {
812 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
817 spi1_sleep: spi1-sleep {
819 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
822 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
823 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
824 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
825 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
830 touch_int_l: touch-int-l {
831 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
834 touch_reset_l: touch-reset-l {
835 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
840 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
841 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
844 trackpad_int_l: trackpad-int-l {
845 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
850 wlan_module_reset_l: wlan-module-reset-l {
851 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
854 bt_host_wake_l: bt-host-wake-l {
855 /* Kevin has an external pull up, but Gru does not */
856 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
862 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;