1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>;
40 #address-cells = <0x2>;
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 #cooling-cells = <2>; /* min followed by max */
85 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 #cooling-cells = <2>; /* min followed by max */
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 #cooling-cells = <2>; /* min followed by max */
101 compatible = "arm,cortex-a53";
103 enable-method = "psci";
104 #cooling-cells = <2>; /* min followed by max */
109 compatible = "arm,cortex-a53";
111 enable-method = "psci";
112 #cooling-cells = <2>; /* min followed by max */
117 compatible = "arm,cortex-a53";
119 enable-method = "psci";
120 #cooling-cells = <2>; /* min followed by max */
125 compatible = "arm,cortex-a53";
127 enable-method = "psci";
128 #cooling-cells = <2>; /* min followed by max */
133 compatible = "arm,cortex-a53";
135 enable-method = "psci";
136 #cooling-cells = <2>; /* min followed by max */
141 compatible = "arm,armv8-pmuv3";
142 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
151 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
152 <&cpu_b2>, <&cpu_b3>;
156 compatible = "arm,psci-0.2";
161 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13
163 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
165 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173 compatible = "fixed-clock";
174 clock-frequency = <24000000>;
175 clock-output-names = "xin24m";
179 sdmmc: mmc@ff0c0000 {
180 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
181 reg = <0x0 0xff0c0000 0x0 0x4000>;
182 max-frequency = <150000000>;
183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
186 fifo-depth = <0x100>;
187 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
188 resets = <&cru SRST_MMC0>;
189 reset-names = "reset";
193 sdio0: mmc@ff0d0000 {
194 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
195 reg = <0x0 0xff0d0000 0x0 0x4000>;
196 max-frequency = <150000000>;
197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
199 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
200 fifo-depth = <0x100>;
201 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
202 resets = <&cru SRST_SDIO0>;
203 reset-names = "reset";
208 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
209 reg = <0x0 0xff0f0000 0x0 0x4000>;
210 max-frequency = <150000000>;
211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
216 resets = <&cru SRST_EMMC>;
217 reset-names = "reset";
221 saradc: saradc@ff100000 {
222 compatible = "rockchip,saradc";
223 reg = <0x0 0xff100000 0x0 0x100>;
224 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
225 #io-channel-cells = <1>;
226 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
227 clock-names = "saradc", "apb_pclk";
228 resets = <&cru SRST_SARADC>;
229 reset-names = "saradc-apb";
234 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
235 reg = <0x0 0xff110000 0x0 0x1000>;
236 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
237 clock-names = "spiclk", "apb_pclk";
238 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
241 #address-cells = <1>;
247 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
248 reg = <0x0 0xff120000 0x0 0x1000>;
249 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
250 clock-names = "spiclk", "apb_pclk";
251 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
254 #address-cells = <1>;
260 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
261 reg = <0x0 0xff130000 0x0 0x1000>;
262 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
263 clock-names = "spiclk", "apb_pclk";
264 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
267 #address-cells = <1>;
273 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
274 reg = <0x0 0xff140000 0x0 0x1000>;
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
279 clocks = <&cru PCLK_I2C2>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c2_xfer>;
286 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
287 reg = <0x0 0xff150000 0x0 0x1000>;
288 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
292 clocks = <&cru PCLK_I2C3>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c3_xfer>;
299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
300 reg = <0x0 0xff160000 0x0 0x1000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
305 clocks = <&cru PCLK_I2C4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c4_xfer>;
312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
313 reg = <0x0 0xff170000 0x0 0x1000>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
318 clocks = <&cru PCLK_I2C5>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c5_xfer>;
324 uart0: serial@ff180000 {
325 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
326 reg = <0x0 0xff180000 0x0 0x100>;
327 clock-frequency = <24000000>;
328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
329 clock-names = "baudclk", "apb_pclk";
330 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
336 uart1: serial@ff190000 {
337 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
338 reg = <0x0 0xff190000 0x0 0x100>;
339 clock-frequency = <24000000>;
340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
341 clock-names = "baudclk", "apb_pclk";
342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
348 uart3: serial@ff1b0000 {
349 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
350 reg = <0x0 0xff1b0000 0x0 0x100>;
351 clock-frequency = <24000000>;
352 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
353 clock-names = "baudclk", "apb_pclk";
354 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
360 uart4: serial@ff1c0000 {
361 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
362 reg = <0x0 0xff1c0000 0x0 0x100>;
363 clock-frequency = <24000000>;
364 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
365 clock-names = "baudclk", "apb_pclk";
366 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
372 dmac_peri: dma-controller@ff250000 {
373 compatible = "arm,pl330", "arm,primecell";
374 reg = <0x0 0xff250000 0x0 0x4000>;
375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
378 arm,pl330-broken-no-flushp;
379 arm,pl330-periph-burst;
380 clocks = <&cru ACLK_DMAC_PERI>;
381 clock-names = "apb_pclk";
385 cpu_thermal: cpu-thermal {
386 polling-delay-passive = <100>; /* milliseconds */
387 polling-delay = <5000>; /* milliseconds */
389 thermal-sensors = <&tsadc 0>;
392 cpu_alert0: cpu_alert0 {
393 temperature = <75000>; /* millicelsius */
394 hysteresis = <2000>; /* millicelsius */
397 cpu_alert1: cpu_alert1 {
398 temperature = <80000>; /* millicelsius */
399 hysteresis = <2000>; /* millicelsius */
403 temperature = <95000>; /* millicelsius */
404 hysteresis = <2000>; /* millicelsius */
411 trip = <&cpu_alert0>;
413 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
414 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
415 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
416 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
419 trip = <&cpu_alert1>;
421 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
422 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
423 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
424 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
429 gpu_thermal: gpu-thermal {
430 polling-delay-passive = <100>; /* milliseconds */
431 polling-delay = <5000>; /* milliseconds */
433 thermal-sensors = <&tsadc 1>;
436 gpu_alert0: gpu_alert0 {
437 temperature = <80000>; /* millicelsius */
438 hysteresis = <2000>; /* millicelsius */
442 temperature = <115000>; /* millicelsius */
443 hysteresis = <2000>; /* millicelsius */
450 trip = <&gpu_alert0>;
452 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
453 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
454 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
455 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
461 tsadc: tsadc@ff280000 {
462 compatible = "rockchip,rk3368-tsadc";
463 reg = <0x0 0xff280000 0x0 0x100>;
464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
466 clock-names = "tsadc", "apb_pclk";
467 resets = <&cru SRST_TSADC>;
468 reset-names = "tsadc-apb";
469 pinctrl-names = "init", "default", "sleep";
470 pinctrl-0 = <&otp_pin>;
471 pinctrl-1 = <&otp_out>;
472 pinctrl-2 = <&otp_pin>;
473 #thermal-sensor-cells = <1>;
474 rockchip,hw-tshut-temp = <95000>;
478 gmac: ethernet@ff290000 {
479 compatible = "rockchip,rk3368-gmac";
480 reg = <0x0 0xff290000 0x0 0x10000>;
481 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "macirq";
483 rockchip,grf = <&grf>;
484 clocks = <&cru SCLK_MAC>,
485 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
486 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
487 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
488 clock-names = "stmmaceth",
489 "mac_clk_rx", "mac_clk_tx",
490 "clk_mac_ref", "clk_mac_refout",
491 "aclk_mac", "pclk_mac";
495 usb_host0_ehci: usb@ff500000 {
496 compatible = "generic-ehci";
497 reg = <0x0 0xff500000 0x0 0x100>;
498 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&cru HCLK_HOST0>;
503 usb_otg: usb@ff580000 {
504 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
506 reg = <0x0 0xff580000 0x0 0x40000>;
507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru HCLK_OTG0>;
511 g-np-tx-fifo-size = <16>;
512 g-rx-fifo-size = <275>;
513 g-tx-fifo-size = <256 128 128 64 64 32>;
517 dmac_bus: dma-controller@ff600000 {
518 compatible = "arm,pl330", "arm,primecell";
519 reg = <0x0 0xff600000 0x0 0x4000>;
520 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
523 arm,pl330-broken-no-flushp;
524 arm,pl330-periph-burst;
525 clocks = <&cru ACLK_DMAC_BUS>;
526 clock-names = "apb_pclk";
530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
531 reg = <0x0 0xff650000 0x0 0x1000>;
532 clocks = <&cru PCLK_I2C0>;
534 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c0_xfer>;
537 #address-cells = <1>;
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544 reg = <0x0 0xff660000 0x0 0x1000>;
545 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
549 clocks = <&cru PCLK_I2C1>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c1_xfer>;
556 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
557 reg = <0x0 0xff680000 0x0 0x10>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm0_pin>;
561 clocks = <&cru PCLK_PWM1>;
566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
567 reg = <0x0 0xff680010 0x0 0x10>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pwm1_pin>;
571 clocks = <&cru PCLK_PWM1>;
576 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
577 reg = <0x0 0xff680020 0x0 0x10>;
579 clocks = <&cru PCLK_PWM1>;
584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
585 reg = <0x0 0xff680030 0x0 0x10>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm3_pin>;
589 clocks = <&cru PCLK_PWM1>;
593 uart2: serial@ff690000 {
594 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
595 reg = <0x0 0xff690000 0x0 0x100>;
596 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
597 clock-names = "baudclk", "apb_pclk";
598 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&uart2_xfer>;
606 mbox: mbox@ff6b0000 {
607 compatible = "rockchip,rk3368-mailbox";
608 reg = <0x0 0xff6b0000 0x0 0x1000>;
609 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cru PCLK_MAILBOX>;
614 clock-names = "pclk_mailbox";
619 pmu: power-management@ff730000 {
620 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
621 reg = <0x0 0xff730000 0x0 0x1000>;
623 power: power-controller {
624 compatible = "rockchip,rk3368-power-controller";
625 #power-domain-cells = <1>;
626 #address-cells = <1>;
630 * Note: Although SCLK_* are the working clocks
631 * of device without including on the NOC, needed for
634 * The clocks on the which NOC:
635 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
636 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
637 * ACLK_RGA is on ACLK_RGA_NIU.
638 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
640 * Which clock are device clocks:
642 * *_IEP IEP:Image Enhancement Processor
643 * *_ISP ISP:Image Signal Processing
644 * *_VIP VIP:Video Input Processor
645 * *_VOP* VOP:Visual Output Processor
652 power-domain@RK3368_PD_VIO {
653 reg = <RK3368_PD_VIO>;
654 clocks = <&cru ACLK_IEP>,
666 <&cru HCLK_VIO_HDCPMMU>,
667 <&cru PCLK_EDP_CTRL>,
668 <&cru PCLK_HDMI_CTRL>,
674 <&cru PCLK_MIPI_CSI>,
675 <&cru PCLK_MIPI_DSI0>,
676 <&cru SCLK_VOP0_PWM>,
682 <&cru SCLK_HDMI_CEC>,
683 <&cru SCLK_HDMI_HDCP>;
693 #power-domain-cells = <0>;
697 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
698 * (video endecoder & decoder) clocks that on the
699 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
701 power-domain@RK3368_PD_VIDEO {
702 reg = <RK3368_PD_VIDEO>;
703 clocks = <&cru ACLK_VIDEO>,
705 <&cru SCLK_HEVC_CABAC>,
706 <&cru SCLK_HEVC_CORE>;
707 pm_qos = <&qos_hevc_r>,
710 #power-domain-cells = <0>;
714 * Note: ACLK_GPU is the GPU clock,
715 * and on the ACLK_GPU_NIU (NOC).
717 power-domain@RK3368_PD_GPU_1 {
718 reg = <RK3368_PD_GPU_1>;
719 clocks = <&cru ACLK_GPU_CFG>,
721 <&cru SCLK_GPU_CORE>;
723 #power-domain-cells = <0>;
728 pmugrf: syscon@ff738000 {
729 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
730 reg = <0x0 0xff738000 0x0 0x1000>;
732 pmu_io_domains: io-domains {
733 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
738 compatible = "syscon-reboot-mode";
740 mode-normal = <BOOT_NORMAL>;
741 mode-recovery = <BOOT_RECOVERY>;
742 mode-bootloader = <BOOT_FASTBOOT>;
743 mode-loader = <BOOT_BL_DOWNLOAD>;
747 cru: clock-controller@ff760000 {
748 compatible = "rockchip,rk3368-cru";
749 reg = <0x0 0xff760000 0x0 0x1000>;
751 clock-names = "xin24m";
752 rockchip,grf = <&grf>;
757 grf: syscon@ff770000 {
758 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
759 reg = <0x0 0xff770000 0x0 0x1000>;
761 io_domains: io-domains {
762 compatible = "rockchip,rk3368-io-voltage-domain";
767 wdt: watchdog@ff800000 {
768 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
769 reg = <0x0 0xff800000 0x0 0x100>;
770 clocks = <&cru PCLK_WDT>;
771 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775 timer0: timer@ff810000 {
776 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
777 reg = <0x0 0xff810000 0x0 0x20>;
778 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
780 clock-names = "pclk", "timer";
783 spdif: spdif@ff880000 {
784 compatible = "rockchip,rk3368-spdif";
785 reg = <0x0 0xff880000 0x0 0x1000>;
786 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
788 clock-names = "mclk", "hclk";
789 dmas = <&dmac_bus 3>;
791 pinctrl-names = "default";
792 pinctrl-0 = <&spdif_tx>;
796 i2s_2ch: i2s-2ch@ff890000 {
797 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
798 reg = <0x0 0xff890000 0x0 0x1000>;
799 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
800 clock-names = "i2s_clk", "i2s_hclk";
801 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
802 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
803 dma-names = "tx", "rx";
807 i2s_8ch: i2s-8ch@ff898000 {
808 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
809 reg = <0x0 0xff898000 0x0 0x1000>;
810 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
811 clock-names = "i2s_clk", "i2s_hclk";
812 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
813 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
814 dma-names = "tx", "rx";
815 pinctrl-names = "default";
816 pinctrl-0 = <&i2s_8ch_bus>;
820 iep_mmu: iommu@ff900800 {
821 compatible = "rockchip,iommu";
822 reg = <0x0 0xff900800 0x0 0x100>;
823 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
825 clock-names = "aclk", "iface";
826 power-domains = <&power RK3368_PD_VIO>;
831 isp_mmu: iommu@ff914000 {
832 compatible = "rockchip,iommu";
833 reg = <0x0 0xff914000 0x0 0x100>,
834 <0x0 0xff915000 0x0 0x100>;
835 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
837 clock-names = "aclk", "iface";
839 power-domains = <&power RK3368_PD_VIO>;
840 rockchip,disable-mmu-reset;
844 vop_mmu: iommu@ff930300 {
845 compatible = "rockchip,iommu";
846 reg = <0x0 0xff930300 0x0 0x100>;
847 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
849 clock-names = "aclk", "iface";
850 power-domains = <&power RK3368_PD_VIO>;
855 hevc_mmu: iommu@ff9a0440 {
856 compatible = "rockchip,iommu";
857 reg = <0x0 0xff9a0440 0x0 0x40>,
858 <0x0 0xff9a0480 0x0 0x40>;
859 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
861 clock-names = "aclk", "iface";
866 vpu_mmu: iommu@ff9a0800 {
867 compatible = "rockchip,iommu";
868 reg = <0x0 0xff9a0800 0x0 0x100>;
869 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
872 clock-names = "aclk", "iface";
877 qos_iep: qos@ffad0000 {
878 compatible = "rockchip,rk3368-qos", "syscon";
879 reg = <0x0 0xffad0000 0x0 0x20>;
882 qos_isp_r0: qos@ffad0080 {
883 compatible = "rockchip,rk3368-qos", "syscon";
884 reg = <0x0 0xffad0080 0x0 0x20>;
887 qos_isp_r1: qos@ffad0100 {
888 compatible = "rockchip,rk3368-qos", "syscon";
889 reg = <0x0 0xffad0100 0x0 0x20>;
892 qos_isp_w0: qos@ffad0180 {
893 compatible = "rockchip,rk3368-qos", "syscon";
894 reg = <0x0 0xffad0180 0x0 0x20>;
897 qos_isp_w1: qos@ffad0200 {
898 compatible = "rockchip,rk3368-qos", "syscon";
899 reg = <0x0 0xffad0200 0x0 0x20>;
902 qos_vip: qos@ffad0280 {
903 compatible = "rockchip,rk3368-qos", "syscon";
904 reg = <0x0 0xffad0280 0x0 0x20>;
907 qos_vop: qos@ffad0300 {
908 compatible = "rockchip,rk3368-qos", "syscon";
909 reg = <0x0 0xffad0300 0x0 0x20>;
912 qos_rga_r: qos@ffad0380 {
913 compatible = "rockchip,rk3368-qos", "syscon";
914 reg = <0x0 0xffad0380 0x0 0x20>;
917 qos_rga_w: qos@ffad0400 {
918 compatible = "rockchip,rk3368-qos", "syscon";
919 reg = <0x0 0xffad0400 0x0 0x20>;
922 qos_hevc_r: qos@ffae0000 {
923 compatible = "rockchip,rk3368-qos", "syscon";
924 reg = <0x0 0xffae0000 0x0 0x20>;
927 qos_vpu_r: qos@ffae0100 {
928 compatible = "rockchip,rk3368-qos", "syscon";
929 reg = <0x0 0xffae0100 0x0 0x20>;
932 qos_vpu_w: qos@ffae0180 {
933 compatible = "rockchip,rk3368-qos", "syscon";
934 reg = <0x0 0xffae0180 0x0 0x20>;
937 qos_gpu: qos@ffaf0000 {
938 compatible = "rockchip,rk3368-qos", "syscon";
939 reg = <0x0 0xffaf0000 0x0 0x20>;
942 efuse256: efuse@ffb00000 {
943 compatible = "rockchip,rk3368-efuse";
944 reg = <0x0 0xffb00000 0x0 0x20>;
945 #address-cells = <1>;
947 clocks = <&cru PCLK_EFUSE256>;
948 clock-names = "pclk_efuse";
950 cpu_leakage: cpu-leakage@17 {
953 temp_adjust: temp-adjust@1f {
958 gic: interrupt-controller@ffb71000 {
959 compatible = "arm,gic-400";
960 interrupt-controller;
961 #interrupt-cells = <3>;
962 #address-cells = <0>;
964 reg = <0x0 0xffb71000 0x0 0x1000>,
965 <0x0 0xffb72000 0x0 0x2000>,
966 <0x0 0xffb74000 0x0 0x2000>,
967 <0x0 0xffb76000 0x0 0x2000>;
968 interrupts = <GIC_PPI 9
969 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
973 compatible = "rockchip,rk3368-pinctrl";
974 rockchip,grf = <&grf>;
975 rockchip,pmu = <&pmugrf>;
976 #address-cells = <0x2>;
980 gpio0: gpio@ff750000 {
981 compatible = "rockchip,gpio-bank";
982 reg = <0x0 0xff750000 0x0 0x100>;
983 clocks = <&cru PCLK_GPIO0>;
984 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
989 interrupt-controller;
990 #interrupt-cells = <0x2>;
993 gpio1: gpio@ff780000 {
994 compatible = "rockchip,gpio-bank";
995 reg = <0x0 0xff780000 0x0 0x100>;
996 clocks = <&cru PCLK_GPIO1>;
997 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1000 #gpio-cells = <0x2>;
1002 interrupt-controller;
1003 #interrupt-cells = <0x2>;
1006 gpio2: gpio@ff790000 {
1007 compatible = "rockchip,gpio-bank";
1008 reg = <0x0 0xff790000 0x0 0x100>;
1009 clocks = <&cru PCLK_GPIO2>;
1010 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1013 #gpio-cells = <0x2>;
1015 interrupt-controller;
1016 #interrupt-cells = <0x2>;
1019 gpio3: gpio@ff7a0000 {
1020 compatible = "rockchip,gpio-bank";
1021 reg = <0x0 0xff7a0000 0x0 0x100>;
1022 clocks = <&cru PCLK_GPIO3>;
1023 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1026 #gpio-cells = <0x2>;
1028 interrupt-controller;
1029 #interrupt-cells = <0x2>;
1032 pcfg_pull_up: pcfg-pull-up {
1036 pcfg_pull_down: pcfg-pull-down {
1040 pcfg_pull_none: pcfg-pull-none {
1044 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1046 drive-strength = <12>;
1050 emmc_clk: emmc-clk {
1051 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1054 emmc_cmd: emmc-cmd {
1055 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1058 emmc_pwr: emmc-pwr {
1059 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1062 emmc_bus1: emmc-bus1 {
1063 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1066 emmc_bus4: emmc-bus4 {
1067 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1068 <1 RK_PC3 2 &pcfg_pull_up>,
1069 <1 RK_PC4 2 &pcfg_pull_up>,
1070 <1 RK_PC5 2 &pcfg_pull_up>;
1073 emmc_bus8: emmc-bus8 {
1074 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1075 <1 RK_PC3 2 &pcfg_pull_up>,
1076 <1 RK_PC4 2 &pcfg_pull_up>,
1077 <1 RK_PC5 2 &pcfg_pull_up>,
1078 <1 RK_PC6 2 &pcfg_pull_up>,
1079 <1 RK_PC7 2 &pcfg_pull_up>,
1080 <1 RK_PD0 2 &pcfg_pull_up>,
1081 <1 RK_PD1 2 &pcfg_pull_up>;
1086 rgmii_pins: rgmii-pins {
1087 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1088 <3 RK_PD0 1 &pcfg_pull_none>,
1089 <3 RK_PC3 1 &pcfg_pull_none>,
1090 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1091 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1092 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1093 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1094 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1095 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1096 <3 RK_PB7 1 &pcfg_pull_none>,
1097 <3 RK_PC0 1 &pcfg_pull_none>,
1098 <3 RK_PC1 1 &pcfg_pull_none>,
1099 <3 RK_PC2 1 &pcfg_pull_none>,
1100 <3 RK_PD1 1 &pcfg_pull_none>,
1101 <3 RK_PC4 1 &pcfg_pull_none>;
1104 rmii_pins: rmii-pins {
1105 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1106 <3 RK_PD0 1 &pcfg_pull_none>,
1107 <3 RK_PC3 1 &pcfg_pull_none>,
1108 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1109 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1110 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1111 <3 RK_PB7 1 &pcfg_pull_none>,
1112 <3 RK_PC0 1 &pcfg_pull_none>,
1113 <3 RK_PC4 1 &pcfg_pull_none>,
1114 <3 RK_PC5 1 &pcfg_pull_none>;
1119 i2c0_xfer: i2c0-xfer {
1120 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1121 <0 RK_PA7 1 &pcfg_pull_none>;
1126 i2c1_xfer: i2c1-xfer {
1127 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1128 <2 RK_PC6 1 &pcfg_pull_none>;
1133 i2c2_xfer: i2c2-xfer {
1134 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1135 <3 RK_PD7 2 &pcfg_pull_none>;
1140 i2c3_xfer: i2c3-xfer {
1141 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1142 <1 RK_PC1 1 &pcfg_pull_none>;
1147 i2c4_xfer: i2c4-xfer {
1148 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1149 <3 RK_PD1 2 &pcfg_pull_none>;
1154 i2c5_xfer: i2c5-xfer {
1155 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1156 <3 RK_PD3 2 &pcfg_pull_none>;
1161 i2s_8ch_bus: i2s-8ch-bus {
1162 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1163 <2 RK_PB5 1 &pcfg_pull_none>,
1164 <2 RK_PB6 1 &pcfg_pull_none>,
1165 <2 RK_PB7 1 &pcfg_pull_none>,
1166 <2 RK_PC0 1 &pcfg_pull_none>,
1167 <2 RK_PC1 1 &pcfg_pull_none>,
1168 <2 RK_PC2 1 &pcfg_pull_none>,
1169 <2 RK_PC3 1 &pcfg_pull_none>,
1170 <2 RK_PC4 1 &pcfg_pull_none>;
1175 pwm0_pin: pwm0-pin {
1176 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1181 pwm1_pin: pwm1-pin {
1182 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1187 pwm3_pin: pwm3-pin {
1188 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1193 sdio0_bus1: sdio0-bus1 {
1194 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1197 sdio0_bus4: sdio0-bus4 {
1198 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1199 <2 RK_PD5 1 &pcfg_pull_up>,
1200 <2 RK_PD6 1 &pcfg_pull_up>,
1201 <2 RK_PD7 1 &pcfg_pull_up>;
1204 sdio0_cmd: sdio0-cmd {
1205 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1208 sdio0_clk: sdio0-clk {
1209 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1212 sdio0_cd: sdio0-cd {
1213 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1216 sdio0_wp: sdio0-wp {
1217 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1220 sdio0_pwr: sdio0-pwr {
1221 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1224 sdio0_bkpwr: sdio0-bkpwr {
1225 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1228 sdio0_int: sdio0-int {
1229 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1234 sdmmc_clk: sdmmc-clk {
1235 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1238 sdmmc_cmd: sdmmc-cmd {
1239 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1242 sdmmc_cd: sdmmc-cd {
1243 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1246 sdmmc_bus1: sdmmc-bus1 {
1247 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1250 sdmmc_bus4: sdmmc-bus4 {
1251 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1252 <2 RK_PA6 1 &pcfg_pull_up>,
1253 <2 RK_PA7 1 &pcfg_pull_up>,
1254 <2 RK_PB0 1 &pcfg_pull_up>;
1259 spdif_tx: spdif-tx {
1260 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1265 spi0_clk: spi0-clk {
1266 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1268 spi0_cs0: spi0-cs0 {
1269 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1271 spi0_cs1: spi0-cs1 {
1272 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1275 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1278 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1283 spi1_clk: spi1-clk {
1284 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1286 spi1_cs0: spi1-cs0 {
1287 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1289 spi1_cs1: spi1-cs1 {
1290 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1293 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1296 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1301 spi2_clk: spi2-clk {
1302 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1304 spi2_cs0: spi2-cs0 {
1305 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1308 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1311 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1317 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1321 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1326 uart0_xfer: uart0-xfer {
1327 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1328 <2 RK_PD1 1 &pcfg_pull_none>;
1331 uart0_cts: uart0-cts {
1332 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1335 uart0_rts: uart0-rts {
1336 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1341 uart1_xfer: uart1-xfer {
1342 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1343 <0 RK_PC5 3 &pcfg_pull_none>;
1346 uart1_cts: uart1-cts {
1347 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1350 uart1_rts: uart1-rts {
1351 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1356 uart2_xfer: uart2-xfer {
1357 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1358 <2 RK_PA5 2 &pcfg_pull_none>;
1360 /* no rts / cts for uart2 */
1364 uart3_xfer: uart3-xfer {
1365 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1366 <3 RK_PD6 3 &pcfg_pull_none>;
1369 uart3_cts: uart3-cts {
1370 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1373 uart3_rts: uart3-rts {
1374 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1379 uart4_xfer: uart4-xfer {
1380 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1381 <0 RK_PD2 3 &pcfg_pull_none>;
1384 uart4_cts: uart4-cts {
1385 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1388 uart4_rts: uart4-rts {
1389 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;