2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
76 #address-cells = <0x2>;
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
130 #cooling-cells = <2>; /* min followed by max */
135 compatible = "arm,cortex-a53", "arm,armv8";
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
143 compatible = "arm,cortex-a53", "arm,armv8";
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
159 compatible = "arm,cortex-a53", "arm,armv8";
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
169 compatible = "arm,cortex-a53", "arm,armv8";
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
185 compatible = "arm,cortex-a53", "arm,armv8";
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
193 compatible = "arm,armv8-pmuv3";
194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
204 <&cpu_b2>, <&cpu_b3>;
208 compatible = "arm,psci-0.2";
213 compatible = "arm,armv8-timer";
214 interrupts = <GIC_PPI 13
215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
233 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 clock-freq-min-max = <400000 150000000>;
235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
238 fifo-depth = <0x100>;
239 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x0 0xff0d0000 0x0 0x4000>;
246 clock-freq-min-max = <400000 150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x0 0xff0f0000 0x0 0x4000>;
258 clock-freq-min-max = <400000 150000000>;
259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
262 fifo-depth = <0x100>;
263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
267 saradc: saradc@ff100000 {
268 compatible = "rockchip,saradc";
269 reg = <0x0 0xff100000 0x0 0x100>;
270 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";
274 resets = <&cru SRST_SARADC>;
275 reset-names = "saradc-apb";
280 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
281 reg = <0x0 0xff110000 0x0 0x1000>;
282 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
283 clock-names = "spiclk", "apb_pclk";
284 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
287 #address-cells = <1>;
293 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
294 reg = <0x0 0xff120000 0x0 0x1000>;
295 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
296 clock-names = "spiclk", "apb_pclk";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 #address-cells = <1>;
306 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
307 reg = <0x0 0xff130000 0x0 0x1000>;
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
313 #address-cells = <1>;
319 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
320 reg = <0x0 0xff140000 0x0 0x1000>;
321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>;
325 clocks = <&cru PCLK_I2C1>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&i2c1_xfer>;
332 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
333 reg = <0x0 0xff150000 0x0 0x1000>;
334 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
338 clocks = <&cru PCLK_I2C3>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c3_xfer>;
345 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
346 reg = <0x0 0xff160000 0x0 0x1000>;
347 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
351 clocks = <&cru PCLK_I2C4>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c4_xfer>;
358 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
359 reg = <0x0 0xff170000 0x0 0x1000>;
360 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
364 clocks = <&cru PCLK_I2C5>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c5_xfer>;
370 uart0: serial@ff180000 {
371 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
372 reg = <0x0 0xff180000 0x0 0x100>;
373 clock-frequency = <24000000>;
374 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
375 clock-names = "baudclk", "apb_pclk";
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
382 uart1: serial@ff190000 {
383 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
384 reg = <0x0 0xff190000 0x0 0x100>;
385 clock-frequency = <24000000>;
386 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
387 clock-names = "baudclk", "apb_pclk";
388 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
394 uart3: serial@ff1b0000 {
395 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
396 reg = <0x0 0xff1b0000 0x0 0x100>;
397 clock-frequency = <24000000>;
398 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
399 clock-names = "baudclk", "apb_pclk";
400 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
406 uart4: serial@ff1c0000 {
407 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
408 reg = <0x0 0xff1c0000 0x0 0x100>;
409 clock-frequency = <24000000>;
410 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
411 clock-names = "baudclk", "apb_pclk";
412 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
420 polling-delay-passive = <100>; /* milliseconds */
421 polling-delay = <5000>; /* milliseconds */
423 thermal-sensors = <&tsadc 0>;
426 cpu_alert0: cpu_alert0 {
427 temperature = <75000>; /* millicelsius */
428 hysteresis = <2000>; /* millicelsius */
431 cpu_alert1: cpu_alert1 {
432 temperature = <80000>; /* millicelsius */
433 hysteresis = <2000>; /* millicelsius */
437 temperature = <95000>; /* millicelsius */
438 hysteresis = <2000>; /* millicelsius */
445 trip = <&cpu_alert0>;
447 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
450 trip = <&cpu_alert1>;
452 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
458 polling-delay-passive = <100>; /* milliseconds */
459 polling-delay = <5000>; /* milliseconds */
461 thermal-sensors = <&tsadc 1>;
464 gpu_alert0: gpu_alert0 {
465 temperature = <80000>; /* millicelsius */
466 hysteresis = <2000>; /* millicelsius */
470 temperature = <115000>; /* millicelsius */
471 hysteresis = <2000>; /* millicelsius */
478 trip = <&gpu_alert0>;
480 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
486 tsadc: tsadc@ff280000 {
487 compatible = "rockchip,rk3368-tsadc";
488 reg = <0x0 0xff280000 0x0 0x100>;
489 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
491 clock-names = "tsadc", "apb_pclk";
492 resets = <&cru SRST_TSADC>;
493 reset-names = "tsadc-apb";
494 pinctrl-names = "init", "default", "sleep";
495 pinctrl-0 = <&otp_gpio>;
496 pinctrl-1 = <&otp_out>;
497 pinctrl-2 = <&otp_gpio>;
498 #thermal-sensor-cells = <1>;
499 rockchip,hw-tshut-temp = <95000>;
503 gmac: ethernet@ff290000 {
504 compatible = "rockchip,rk3368-gmac";
505 reg = <0x0 0xff290000 0x0 0x10000>;
506 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
507 interrupt-names = "macirq";
508 rockchip,grf = <&grf>;
509 clocks = <&cru SCLK_MAC>,
510 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
511 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
512 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
513 clock-names = "stmmaceth",
514 "mac_clk_rx", "mac_clk_tx",
515 "clk_mac_ref", "clk_mac_refout",
516 "aclk_mac", "pclk_mac";
520 usb_host0_ehci: usb@ff500000 {
521 compatible = "generic-ehci";
522 reg = <0x0 0xff500000 0x0 0x100>;
523 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_HOST0>;
525 clock-names = "usbhost";
529 usb_otg: usb@ff580000 {
530 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
532 reg = <0x0 0xff580000 0x0 0x40000>;
533 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru HCLK_OTG0>;
537 g-np-tx-fifo-size = <16>;
538 g-rx-fifo-size = <275>;
539 g-tx-fifo-size = <256 128 128 64 64 32>;
545 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
546 reg = <0x0 0xff650000 0x0 0x1000>;
547 clocks = <&cru PCLK_I2C0>;
549 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c0_xfer>;
552 #address-cells = <1>;
558 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
559 reg = <0x0 0xff660000 0x0 0x1000>;
560 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 #address-cells = <1>;
564 clocks = <&cru PCLK_I2C2>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c2_xfer>;
571 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
572 reg = <0x0 0xff680000 0x0 0x10>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pwm0_pin>;
576 clocks = <&cru PCLK_PWM1>;
582 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
583 reg = <0x0 0xff680010 0x0 0x10>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pwm1_pin>;
587 clocks = <&cru PCLK_PWM1>;
593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
594 reg = <0x0 0xff680020 0x0 0x10>;
596 clocks = <&cru PCLK_PWM1>;
602 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
603 reg = <0x0 0xff680030 0x0 0x10>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&pwm3_pin>;
607 clocks = <&cru PCLK_PWM1>;
612 uart2: serial@ff690000 {
613 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
614 reg = <0x0 0xff690000 0x0 0x100>;
615 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
616 clock-names = "baudclk", "apb_pclk";
617 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart2_xfer>;
625 mbox: mbox@ff6b0000 {
626 compatible = "rockchip,rk3368-mailbox";
627 reg = <0x0 0xff6b0000 0x0 0x1000>;
628 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru PCLK_MAILBOX>;
633 clock-names = "pclk_mailbox";
637 pmugrf: syscon@ff738000 {
638 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
639 reg = <0x0 0xff738000 0x0 0x1000>;
641 pmu_io_domains: io-domains {
642 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
647 compatible = "syscon-reboot-mode";
649 mode-normal = <BOOT_NORMAL>;
650 mode-recovery = <BOOT_RECOVERY>;
651 mode-bootloader = <BOOT_FASTBOOT>;
652 mode-loader = <BOOT_BL_DOWNLOAD>;
656 cru: clock-controller@ff760000 {
657 compatible = "rockchip,rk3368-cru";
658 reg = <0x0 0xff760000 0x0 0x1000>;
659 rockchip,grf = <&grf>;
664 grf: syscon@ff770000 {
665 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
666 reg = <0x0 0xff770000 0x0 0x1000>;
668 io_domains: io-domains {
669 compatible = "rockchip,rk3368-io-voltage-domain";
674 wdt: watchdog@ff800000 {
675 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
676 reg = <0x0 0xff800000 0x0 0x100>;
677 clocks = <&cru PCLK_WDT>;
678 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
683 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
684 reg = <0x0 0xff810000 0x0 0x20>;
685 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
688 gic: interrupt-controller@ffb71000 {
689 compatible = "arm,gic-400";
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 #address-cells = <0>;
694 reg = <0x0 0xffb71000 0x0 0x1000>,
695 <0x0 0xffb72000 0x0 0x2000>,
696 <0x0 0xffb74000 0x0 0x2000>,
697 <0x0 0xffb76000 0x0 0x2000>;
698 interrupts = <GIC_PPI 9
699 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
703 compatible = "rockchip,rk3368-pinctrl";
704 rockchip,grf = <&grf>;
705 rockchip,pmu = <&pmugrf>;
706 #address-cells = <0x2>;
710 gpio0: gpio0@ff750000 {
711 compatible = "rockchip,gpio-bank";
712 reg = <0x0 0xff750000 0x0 0x100>;
713 clocks = <&cru PCLK_GPIO0>;
714 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
719 interrupt-controller;
720 #interrupt-cells = <0x2>;
723 gpio1: gpio1@ff780000 {
724 compatible = "rockchip,gpio-bank";
725 reg = <0x0 0xff780000 0x0 0x100>;
726 clocks = <&cru PCLK_GPIO1>;
727 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-controller;
733 #interrupt-cells = <0x2>;
736 gpio2: gpio2@ff790000 {
737 compatible = "rockchip,gpio-bank";
738 reg = <0x0 0xff790000 0x0 0x100>;
739 clocks = <&cru PCLK_GPIO2>;
740 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-controller;
746 #interrupt-cells = <0x2>;
749 gpio3: gpio3@ff7a0000 {
750 compatible = "rockchip,gpio-bank";
751 reg = <0x0 0xff7a0000 0x0 0x100>;
752 clocks = <&cru PCLK_GPIO3>;
753 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-controller;
759 #interrupt-cells = <0x2>;
762 pcfg_pull_up: pcfg-pull-up {
766 pcfg_pull_down: pcfg-pull-down {
770 pcfg_pull_none: pcfg-pull-none {
774 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
776 drive-strength = <12>;
781 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
785 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
789 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
792 emmc_bus1: emmc-bus1 {
793 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
796 emmc_bus4: emmc-bus4 {
797 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
798 <1 19 RK_FUNC_2 &pcfg_pull_up>,
799 <1 20 RK_FUNC_2 &pcfg_pull_up>,
800 <1 21 RK_FUNC_2 &pcfg_pull_up>;
803 emmc_bus8: emmc-bus8 {
804 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
805 <1 19 RK_FUNC_2 &pcfg_pull_up>,
806 <1 20 RK_FUNC_2 &pcfg_pull_up>,
807 <1 21 RK_FUNC_2 &pcfg_pull_up>,
808 <1 22 RK_FUNC_2 &pcfg_pull_up>,
809 <1 23 RK_FUNC_2 &pcfg_pull_up>,
810 <1 24 RK_FUNC_2 &pcfg_pull_up>,
811 <1 25 RK_FUNC_2 &pcfg_pull_up>;
816 rgmii_pins: rgmii-pins {
817 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
818 <3 24 RK_FUNC_1 &pcfg_pull_none>,
819 <3 19 RK_FUNC_1 &pcfg_pull_none>,
820 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
821 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
822 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
823 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
824 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
825 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
826 <3 15 RK_FUNC_1 &pcfg_pull_none>,
827 <3 16 RK_FUNC_1 &pcfg_pull_none>,
828 <3 17 RK_FUNC_1 &pcfg_pull_none>,
829 <3 18 RK_FUNC_1 &pcfg_pull_none>,
830 <3 25 RK_FUNC_1 &pcfg_pull_none>,
831 <3 20 RK_FUNC_1 &pcfg_pull_none>;
834 rmii_pins: rmii-pins {
835 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
836 <3 24 RK_FUNC_1 &pcfg_pull_none>,
837 <3 19 RK_FUNC_1 &pcfg_pull_none>,
838 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
839 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
840 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
841 <3 15 RK_FUNC_1 &pcfg_pull_none>,
842 <3 16 RK_FUNC_1 &pcfg_pull_none>,
843 <3 20 RK_FUNC_1 &pcfg_pull_none>,
844 <3 21 RK_FUNC_1 &pcfg_pull_none>;
849 i2c0_xfer: i2c0-xfer {
850 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
851 <0 7 RK_FUNC_1 &pcfg_pull_none>;
856 i2c1_xfer: i2c1-xfer {
857 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
858 <2 22 RK_FUNC_1 &pcfg_pull_none>;
863 i2c2_xfer: i2c2-xfer {
864 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
865 <3 31 RK_FUNC_2 &pcfg_pull_none>;
870 i2c3_xfer: i2c3-xfer {
871 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
872 <1 17 RK_FUNC_1 &pcfg_pull_none>;
877 i2c4_xfer: i2c4-xfer {
878 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
879 <3 25 RK_FUNC_2 &pcfg_pull_none>;
884 i2c5_xfer: i2c5-xfer {
885 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
886 <3 27 RK_FUNC_2 &pcfg_pull_none>;
892 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
898 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
904 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
909 sdio0_bus1: sdio0-bus1 {
910 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
913 sdio0_bus4: sdio0-bus4 {
914 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
915 <2 29 RK_FUNC_1 &pcfg_pull_up>,
916 <2 30 RK_FUNC_1 &pcfg_pull_up>,
917 <2 31 RK_FUNC_1 &pcfg_pull_up>;
920 sdio0_cmd: sdio0-cmd {
921 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
924 sdio0_clk: sdio0-clk {
925 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
929 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
933 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
936 sdio0_pwr: sdio0-pwr {
937 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
940 sdio0_bkpwr: sdio0-bkpwr {
941 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
944 sdio0_int: sdio0-int {
945 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
950 sdmmc_clk: sdmmc-clk {
951 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
954 sdmmc_cmd: sdmmc-cmd {
955 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
959 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
962 sdmmc_bus1: sdmmc-bus1 {
963 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
966 sdmmc_bus4: sdmmc-bus4 {
967 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
968 <2 6 RK_FUNC_1 &pcfg_pull_up>,
969 <2 7 RK_FUNC_1 &pcfg_pull_up>,
970 <2 8 RK_FUNC_1 &pcfg_pull_up>;
976 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
979 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
982 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
985 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
988 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
994 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
997 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1000 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1003 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1006 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1011 spi2_clk: spi2-clk {
1012 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1014 spi2_cs0: spi2-cs0 {
1015 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1018 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1021 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1026 otp_gpio: otp-gpio {
1027 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1031 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1036 uart0_xfer: uart0-xfer {
1037 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1038 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1041 uart0_cts: uart0-cts {
1042 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1045 uart0_rts: uart0-rts {
1046 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1051 uart1_xfer: uart1-xfer {
1052 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1053 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1056 uart1_cts: uart1-cts {
1057 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1060 uart1_rts: uart1-rts {
1061 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1066 uart2_xfer: uart2-xfer {
1067 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1068 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1070 /* no rts / cts for uart2 */
1074 uart3_xfer: uart3-xfer {
1075 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1076 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1079 uart3_cts: uart3-cts {
1080 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1083 uart3_rts: uart3-rts {
1084 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1089 uart4_xfer: uart4-xfer {
1090 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1091 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1094 uart4_cts: uart4-cts {
1095 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1098 uart4_rts: uart4-rts {
1099 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;