1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3328";
18 interrupt-parent = <&gic>;
31 ethernet1 = &gmac2phy;
40 compatible = "arm,cortex-a53";
42 clocks = <&cru ARMCLK>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
55 clocks = <&cru ARMCLK>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
68 clocks = <&cru ARMCLK>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
81 clocks = <&cru ARMCLK>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
104 compatible = "cache";
110 cpu0_opp_table: opp-table-0 {
111 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <950000>;
117 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <950000>;
123 clock-latency-ns = <40000>;
126 opp-hz = /bits/ 64 <816000000>;
127 opp-microvolt = <1000000>;
128 clock-latency-ns = <40000>;
131 opp-hz = /bits/ 64 <1008000000>;
132 opp-microvolt = <1100000>;
133 clock-latency-ns = <40000>;
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <1225000>;
138 clock-latency-ns = <40000>;
141 opp-hz = /bits/ 64 <1296000000>;
142 opp-microvolt = <1300000>;
143 clock-latency-ns = <40000>;
147 analog_sound: analog-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,format = "i2s";
150 simple-audio-card,mclk-fs = <256>;
151 simple-audio-card,name = "Analog";
154 simple-audio-card,cpu {
158 simple-audio-card,codec {
159 sound-dai = <&codec>;
164 compatible = "arm,cortex-a53-pmu";
165 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
172 display_subsystem: display-subsystem {
173 compatible = "rockchip,display-subsystem";
177 hdmi_sound: hdmi-sound {
178 compatible = "simple-audio-card";
179 simple-audio-card,format = "i2s";
180 simple-audio-card,mclk-fs = <128>;
181 simple-audio-card,name = "HDMI";
184 simple-audio-card,cpu {
188 simple-audio-card,codec {
194 compatible = "arm,psci-1.0", "arm,psci-0.2";
199 compatible = "arm,armv8-timer";
200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
202 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
203 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
207 compatible = "fixed-clock";
209 clock-frequency = <24000000>;
210 clock-output-names = "xin24m";
214 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
215 reg = <0x0 0xff000000 0x0 0x1000>;
216 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
218 clock-names = "i2s_clk", "i2s_hclk";
219 dmas = <&dmac 11>, <&dmac 12>;
220 dma-names = "tx", "rx";
221 #sound-dai-cells = <0>;
226 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
227 reg = <0x0 0xff010000 0x0 0x1000>;
228 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
230 clock-names = "i2s_clk", "i2s_hclk";
231 dmas = <&dmac 14>, <&dmac 15>;
232 dma-names = "tx", "rx";
233 #sound-dai-cells = <0>;
238 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
239 reg = <0x0 0xff020000 0x0 0x1000>;
240 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
242 clock-names = "i2s_clk", "i2s_hclk";
243 dmas = <&dmac 0>, <&dmac 1>;
244 dma-names = "tx", "rx";
245 #sound-dai-cells = <0>;
249 spdif: spdif@ff030000 {
250 compatible = "rockchip,rk3328-spdif";
251 reg = <0x0 0xff030000 0x0 0x1000>;
252 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
254 clock-names = "mclk", "hclk";
257 pinctrl-names = "default";
258 pinctrl-0 = <&spdifm2_tx>;
259 #sound-dai-cells = <0>;
264 compatible = "rockchip,pdm";
265 reg = <0x0 0xff040000 0x0 0x1000>;
266 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
267 clock-names = "pdm_clk", "pdm_hclk";
270 pinctrl-names = "default", "sleep";
271 pinctrl-0 = <&pdmm0_clk
276 pinctrl-1 = <&pdmm0_clk_sleep
284 grf: syscon@ff100000 {
285 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
286 reg = <0x0 0xff100000 0x0 0x1000>;
288 io_domains: io-domains {
289 compatible = "rockchip,rk3328-io-voltage-domain";
294 compatible = "rockchip,rk3328-grf-gpio";
299 power: power-controller {
300 compatible = "rockchip,rk3328-power-controller";
301 #power-domain-cells = <1>;
302 #address-cells = <1>;
305 power-domain@RK3328_PD_HEVC {
306 reg = <RK3328_PD_HEVC>;
307 #power-domain-cells = <0>;
309 power-domain@RK3328_PD_VIDEO {
310 reg = <RK3328_PD_VIDEO>;
311 clocks = <&cru ACLK_RKVDEC>,
313 <&cru SCLK_VDEC_CABAC>,
314 <&cru SCLK_VDEC_CORE>;
315 #power-domain-cells = <0>;
317 power-domain@RK3328_PD_VPU {
318 reg = <RK3328_PD_VPU>;
319 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
320 #power-domain-cells = <0>;
325 compatible = "syscon-reboot-mode";
327 mode-normal = <BOOT_NORMAL>;
328 mode-recovery = <BOOT_RECOVERY>;
329 mode-bootloader = <BOOT_FASTBOOT>;
330 mode-loader = <BOOT_BL_DOWNLOAD>;
334 uart0: serial@ff110000 {
335 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
336 reg = <0x0 0xff110000 0x0 0x100>;
337 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
339 clock-names = "baudclk", "apb_pclk";
340 dmas = <&dmac 2>, <&dmac 3>;
341 dma-names = "tx", "rx";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
349 uart1: serial@ff120000 {
350 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
351 reg = <0x0 0xff120000 0x0 0x100>;
352 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
354 clock-names = "baudclk", "apb_pclk";
355 dmas = <&dmac 4>, <&dmac 5>;
356 dma-names = "tx", "rx";
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
364 uart2: serial@ff130000 {
365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
366 reg = <0x0 0xff130000 0x0 0x100>;
367 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
369 clock-names = "baudclk", "apb_pclk";
370 dmas = <&dmac 6>, <&dmac 7>;
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart2m1_xfer>;
380 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
381 reg = <0x0 0xff150000 0x0 0x1000>;
382 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
385 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
393 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
394 reg = <0x0 0xff160000 0x0 0x1000>;
395 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
398 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
399 clock-names = "i2c", "pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c1_xfer>;
406 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
407 reg = <0x0 0xff170000 0x0 0x1000>;
408 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
409 #address-cells = <1>;
411 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
412 clock-names = "i2c", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&i2c2_xfer>;
419 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
420 reg = <0x0 0xff180000 0x0 0x1000>;
421 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
424 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
425 clock-names = "i2c", "pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c3_xfer>;
432 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
433 reg = <0x0 0xff190000 0x0 0x1000>;
434 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
437 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
438 clock-names = "spiclk", "apb_pclk";
439 dmas = <&dmac 8>, <&dmac 9>;
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
446 wdt: watchdog@ff1a0000 {
447 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
448 reg = <0x0 0xff1a0000 0x0 0x100>;
449 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&cru PCLK_WDT>;
454 compatible = "rockchip,rk3328-pwm";
455 reg = <0x0 0xff1b0000 0x0 0x10>;
456 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
457 clock-names = "pwm", "pclk";
458 pinctrl-names = "default";
459 pinctrl-0 = <&pwm0_pin>;
465 compatible = "rockchip,rk3328-pwm";
466 reg = <0x0 0xff1b0010 0x0 0x10>;
467 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
468 clock-names = "pwm", "pclk";
469 pinctrl-names = "default";
470 pinctrl-0 = <&pwm1_pin>;
476 compatible = "rockchip,rk3328-pwm";
477 reg = <0x0 0xff1b0020 0x0 0x10>;
478 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
479 clock-names = "pwm", "pclk";
480 pinctrl-names = "default";
481 pinctrl-0 = <&pwm2_pin>;
487 compatible = "rockchip,rk3328-pwm";
488 reg = <0x0 0xff1b0030 0x0 0x10>;
489 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
491 clock-names = "pwm", "pclk";
492 pinctrl-names = "default";
493 pinctrl-0 = <&pwmir_pin>;
498 dmac: dma-controller@ff1f0000 {
499 compatible = "arm,pl330", "arm,primecell";
500 reg = <0x0 0xff1f0000 0x0 0x4000>;
501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
503 arm,pl330-periph-burst;
504 clocks = <&cru ACLK_DMAC>;
505 clock-names = "apb_pclk";
510 soc_thermal: soc-thermal {
511 polling-delay-passive = <20>;
512 polling-delay = <1000>;
513 sustainable-power = <1000>;
515 thermal-sensors = <&tsadc 0>;
518 threshold: trip-point0 {
519 temperature = <70000>;
523 target: trip-point1 {
524 temperature = <85000>;
529 temperature = <95000>;
538 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
539 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
540 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
541 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
542 contribution = <4096>;
549 tsadc: tsadc@ff250000 {
550 compatible = "rockchip,rk3328-tsadc";
551 reg = <0x0 0xff250000 0x0 0x100>;
552 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
553 assigned-clocks = <&cru SCLK_TSADC>;
554 assigned-clock-rates = <50000>;
555 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
556 clock-names = "tsadc", "apb_pclk";
557 pinctrl-names = "init", "default", "sleep";
558 pinctrl-0 = <&otp_pin>;
559 pinctrl-1 = <&otp_out>;
560 pinctrl-2 = <&otp_pin>;
561 resets = <&cru SRST_TSADC>;
562 reset-names = "tsadc-apb";
563 rockchip,grf = <&grf>;
564 rockchip,hw-tshut-temp = <100000>;
565 #thermal-sensor-cells = <1>;
569 efuse: efuse@ff260000 {
570 compatible = "rockchip,rk3328-efuse";
571 reg = <0x0 0xff260000 0x0 0x50>;
572 #address-cells = <1>;
574 clocks = <&cru SCLK_EFUSE>;
575 clock-names = "pclk_efuse";
576 rockchip,efuse-size = <0x20>;
582 cpu_leakage: cpu-leakage@17 {
585 logic_leakage: logic-leakage@19 {
588 efuse_cpu_version: cpu-version@1a {
594 saradc: adc@ff280000 {
595 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
596 reg = <0x0 0xff280000 0x0 0x100>;
597 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
598 #io-channel-cells = <1>;
599 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
600 clock-names = "saradc", "apb_pclk";
601 resets = <&cru SRST_SARADC_P>;
602 reset-names = "saradc-apb";
607 compatible = "rockchip,rk3328-mali", "arm,mali-450";
608 reg = <0x0 0xff300000 0x0 0x30000>;
609 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
616 interrupt-names = "gp",
623 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
624 clock-names = "bus", "core";
625 resets = <&cru SRST_GPU_A>;
628 h265e_mmu: iommu@ff330200 {
629 compatible = "rockchip,iommu";
630 reg = <0x0 0xff330200 0 0x100>;
631 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
633 clock-names = "aclk", "iface";
638 vepu_mmu: iommu@ff340800 {
639 compatible = "rockchip,iommu";
640 reg = <0x0 0xff340800 0x0 0x40>;
641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
643 clock-names = "aclk", "iface";
648 vpu: video-codec@ff350000 {
649 compatible = "rockchip,rk3328-vpu";
650 reg = <0x0 0xff350000 0x0 0x800>;
651 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
652 interrupt-names = "vdpu";
653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
654 clock-names = "aclk", "hclk";
656 power-domains = <&power RK3328_PD_VPU>;
659 vpu_mmu: iommu@ff350800 {
660 compatible = "rockchip,iommu";
661 reg = <0x0 0xff350800 0x0 0x40>;
662 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
664 clock-names = "aclk", "iface";
666 power-domains = <&power RK3328_PD_VPU>;
669 vdec: video-codec@ff360000 {
670 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
671 reg = <0x0 0xff360000 0x0 0x480>;
672 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
674 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
675 clock-names = "axi", "ahb", "cabac", "core";
676 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
677 <&cru SCLK_VDEC_CORE>;
678 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
679 iommus = <&vdec_mmu>;
680 power-domains = <&power RK3328_PD_VIDEO>;
683 vdec_mmu: iommu@ff360480 {
684 compatible = "rockchip,iommu";
685 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
686 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
688 clock-names = "aclk", "iface";
690 power-domains = <&power RK3328_PD_VIDEO>;
694 compatible = "rockchip,rk3328-vop";
695 reg = <0x0 0xff370000 0x0 0x3efc>;
696 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
698 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
699 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
700 reset-names = "axi", "ahb", "dclk";
705 #address-cells = <1>;
708 vop_out_hdmi: endpoint@0 {
710 remote-endpoint = <&hdmi_in_vop>;
715 vop_mmu: iommu@ff373f00 {
716 compatible = "rockchip,iommu";
717 reg = <0x0 0xff373f00 0x0 0x100>;
718 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
720 clock-names = "aclk", "iface";
725 hdmi: hdmi@ff3c0000 {
726 compatible = "rockchip,rk3328-dw-hdmi";
727 reg = <0x0 0xff3c0000 0x0 0x20000>;
729 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cru PCLK_HDMI>,
732 <&cru SCLK_HDMI_SFC>,
734 clock-names = "iahb",
739 pinctrl-names = "default";
740 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
741 rockchip,grf = <&grf>;
742 #sound-dai-cells = <0>;
747 hdmi_in_vop: endpoint {
748 remote-endpoint = <&vop_out_hdmi>;
754 codec: codec@ff410000 {
755 compatible = "rockchip,rk3328-codec";
756 reg = <0x0 0xff410000 0x0 0x1000>;
757 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
758 clock-names = "pclk", "mclk";
759 rockchip,grf = <&grf>;
760 #sound-dai-cells = <0>;
764 hdmiphy: phy@ff430000 {
765 compatible = "rockchip,rk3328-hdmi-phy";
766 reg = <0x0 0xff430000 0x0 0x10000>;
767 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
769 clock-names = "sysclk", "refoclk", "refpclk";
770 clock-output-names = "hdmi_phy";
772 nvmem-cells = <&efuse_cpu_version>;
773 nvmem-cell-names = "cpu-version";
778 cru: clock-controller@ff440000 {
779 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
780 reg = <0x0 0xff440000 0x0 0x1000>;
781 rockchip,grf = <&grf>;
786 * CPLL should run at 1200, but that is to high for
787 * the initial dividers of most of its children.
788 * We need set cpll child clk div first,
789 * and then set the cpll frequency.
791 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
792 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
793 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
794 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
795 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
796 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
797 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
798 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
799 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
800 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
801 <&cru SCLK_WIFI>, <&cru ARMCLK>,
802 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
803 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
804 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
805 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
807 assigned-clock-parents =
808 <&cru HDMIPHY>, <&cru PLL_APLL>,
809 <&cru PLL_GPLL>, <&xin24m>,
810 <&xin24m>, <&xin24m>;
811 assigned-clock-rates =
814 <24000000>, <24000000>,
815 <15000000>, <15000000>,
816 <100000000>, <100000000>,
817 <100000000>, <100000000>,
818 <50000000>, <100000000>,
819 <100000000>, <100000000>,
820 <50000000>, <50000000>,
821 <50000000>, <50000000>,
822 <24000000>, <600000000>,
823 <491520000>, <1200000000>,
824 <150000000>, <75000000>,
825 <75000000>, <150000000>,
826 <75000000>, <75000000>,
830 usb2phy_grf: syscon@ff450000 {
831 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
833 reg = <0x0 0xff450000 0x0 0x10000>;
834 #address-cells = <1>;
838 compatible = "rockchip,rk3328-usb2phy";
841 clock-names = "phyclk";
842 clock-output-names = "usb480m_phy";
844 assigned-clocks = <&cru USB480M>;
845 assigned-clock-parents = <&u2phy>;
848 u2phy_otg: otg-port {
850 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
853 interrupt-names = "otg-bvalid", "otg-id",
858 u2phy_host: host-port {
860 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
861 interrupt-names = "linestate";
867 sdmmc: mmc@ff500000 {
868 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
869 reg = <0x0 0xff500000 0x0 0x4000>;
870 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
872 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
873 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
874 fifo-depth = <0x100>;
875 max-frequency = <150000000>;
880 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
881 reg = <0x0 0xff510000 0x0 0x4000>;
882 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
884 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
885 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
886 fifo-depth = <0x100>;
887 max-frequency = <150000000>;
892 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
893 reg = <0x0 0xff520000 0x0 0x4000>;
894 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
896 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
897 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
898 fifo-depth = <0x100>;
899 max-frequency = <150000000>;
903 gmac2io: ethernet@ff540000 {
904 compatible = "rockchip,rk3328-gmac";
905 reg = <0x0 0xff540000 0x0 0x10000>;
906 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
907 interrupt-names = "macirq";
908 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
909 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
910 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
912 clock-names = "stmmaceth", "mac_clk_rx",
913 "mac_clk_tx", "clk_mac_ref",
914 "clk_mac_refout", "aclk_mac",
916 resets = <&cru SRST_GMAC2IO_A>;
917 reset-names = "stmmaceth";
918 rockchip,grf = <&grf>;
923 gmac2phy: ethernet@ff550000 {
924 compatible = "rockchip,rk3328-gmac";
925 reg = <0x0 0xff550000 0x0 0x10000>;
926 rockchip,grf = <&grf>;
927 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
928 interrupt-names = "macirq";
929 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
930 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
931 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
932 <&cru SCLK_MAC2PHY_OUT>;
933 clock-names = "stmmaceth", "mac_clk_rx",
934 "mac_clk_tx", "clk_mac_ref",
935 "aclk_mac", "pclk_mac",
937 resets = <&cru SRST_GMAC2PHY_A>;
938 reset-names = "stmmaceth";
942 clock_in_out = "output";
946 compatible = "snps,dwmac-mdio";
947 #address-cells = <1>;
950 phy: ethernet-phy@0 {
951 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
953 clocks = <&cru SCLK_MAC2PHY_OUT>;
954 resets = <&cru SRST_MACPHY>;
955 pinctrl-names = "default";
956 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
962 usb20_otg: usb@ff580000 {
963 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
965 reg = <0x0 0xff580000 0x0 0x40000>;
966 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&cru HCLK_OTG>;
970 g-np-tx-fifo-size = <16>;
971 g-rx-fifo-size = <280>;
972 g-tx-fifo-size = <256 128 128 64 32 16>;
974 phy-names = "usb2-phy";
978 usb_host0_ehci: usb@ff5c0000 {
979 compatible = "generic-ehci";
980 reg = <0x0 0xff5c0000 0x0 0x10000>;
981 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cru HCLK_HOST0>, <&u2phy>;
983 phys = <&u2phy_host>;
988 usb_host0_ohci: usb@ff5d0000 {
989 compatible = "generic-ohci";
990 reg = <0x0 0xff5d0000 0x0 0x10000>;
991 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&cru HCLK_HOST0>, <&u2phy>;
993 phys = <&u2phy_host>;
998 usbdrd3: usb@ff600000 {
999 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1000 reg = <0x0 0xff600000 0x0 0x100000>;
1001 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1003 <&cru ACLK_USB3OTG>;
1004 clock-names = "ref_clk", "suspend_clk",
1007 phy_type = "utmi_wide";
1008 snps,dis-del-phy-power-chg-quirk;
1009 snps,dis_enblslpm_quirk;
1010 snps,dis-tx-ipgap-linecheck-quirk;
1011 snps,dis-u2-freeclk-exists-quirk;
1012 snps,dis_u2_susphy_quirk;
1013 snps,dis_u3_susphy_quirk;
1014 status = "disabled";
1017 gic: interrupt-controller@ff811000 {
1018 compatible = "arm,gic-400";
1019 #interrupt-cells = <3>;
1020 #address-cells = <0>;
1021 interrupt-controller;
1022 reg = <0x0 0xff811000 0 0x1000>,
1023 <0x0 0xff812000 0 0x2000>,
1024 <0x0 0xff814000 0 0x2000>,
1025 <0x0 0xff816000 0 0x2000>;
1026 interrupts = <GIC_PPI 9
1027 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1030 crypto: crypto@ff060000 {
1031 compatible = "rockchip,rk3328-crypto";
1032 reg = <0x0 0xff060000 0x0 0x4000>;
1033 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1036 clock-names = "hclk_master", "hclk_slave", "sclk";
1037 resets = <&cru SRST_CRYPTO>;
1038 reset-names = "crypto-rst";
1042 compatible = "rockchip,rk3328-pinctrl";
1043 rockchip,grf = <&grf>;
1044 #address-cells = <2>;
1048 gpio0: gpio@ff210000 {
1049 compatible = "rockchip,gpio-bank";
1050 reg = <0x0 0xff210000 0x0 0x100>;
1051 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&cru PCLK_GPIO0>;
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1061 gpio1: gpio@ff220000 {
1062 compatible = "rockchip,gpio-bank";
1063 reg = <0x0 0xff220000 0x0 0x100>;
1064 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cru PCLK_GPIO1>;
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1074 gpio2: gpio@ff230000 {
1075 compatible = "rockchip,gpio-bank";
1076 reg = <0x0 0xff230000 0x0 0x100>;
1077 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&cru PCLK_GPIO2>;
1083 interrupt-controller;
1084 #interrupt-cells = <2>;
1087 gpio3: gpio@ff240000 {
1088 compatible = "rockchip,gpio-bank";
1089 reg = <0x0 0xff240000 0x0 0x100>;
1090 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cru PCLK_GPIO3>;
1096 interrupt-controller;
1097 #interrupt-cells = <2>;
1100 pcfg_pull_up: pcfg-pull-up {
1104 pcfg_pull_down: pcfg-pull-down {
1108 pcfg_pull_none: pcfg-pull-none {
1112 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1114 drive-strength = <2>;
1117 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1119 drive-strength = <2>;
1122 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1124 drive-strength = <4>;
1127 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1129 drive-strength = <4>;
1132 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1134 drive-strength = <4>;
1137 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1139 drive-strength = <8>;
1142 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1144 drive-strength = <8>;
1147 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1149 drive-strength = <12>;
1152 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1154 drive-strength = <12>;
1157 pcfg_output_high: pcfg-output-high {
1161 pcfg_output_low: pcfg-output-low {
1165 pcfg_input_high: pcfg-input-high {
1170 pcfg_input: pcfg-input {
1175 i2c0_xfer: i2c0-xfer {
1176 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1177 <2 RK_PD1 1 &pcfg_pull_none>;
1182 i2c1_xfer: i2c1-xfer {
1183 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1184 <2 RK_PA5 2 &pcfg_pull_none>;
1189 i2c2_xfer: i2c2-xfer {
1190 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1191 <2 RK_PB6 1 &pcfg_pull_none>;
1196 i2c3_xfer: i2c3-xfer {
1197 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1198 <0 RK_PA6 2 &pcfg_pull_none>;
1200 i2c3_pins: i2c3-pins {
1202 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1203 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1208 hdmii2c_xfer: hdmii2c-xfer {
1209 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1210 <0 RK_PA6 1 &pcfg_pull_none>;
1215 pdmm0_clk: pdmm0-clk {
1216 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1219 pdmm0_fsync: pdmm0-fsync {
1220 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1223 pdmm0_sdi0: pdmm0-sdi0 {
1224 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1227 pdmm0_sdi1: pdmm0-sdi1 {
1228 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1231 pdmm0_sdi2: pdmm0-sdi2 {
1232 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1235 pdmm0_sdi3: pdmm0-sdi3 {
1236 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1239 pdmm0_clk_sleep: pdmm0-clk-sleep {
1241 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1244 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1246 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1249 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1251 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1254 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1256 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1259 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1261 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1264 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1266 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1272 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1276 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1281 uart0_xfer: uart0-xfer {
1282 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1283 <1 RK_PB0 1 &pcfg_pull_up>;
1286 uart0_cts: uart0-cts {
1287 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1290 uart0_rts: uart0-rts {
1291 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1294 uart0_rts_pin: uart0-rts-pin {
1295 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1300 uart1_xfer: uart1-xfer {
1301 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1302 <3 RK_PA6 4 &pcfg_pull_up>;
1305 uart1_cts: uart1-cts {
1306 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1309 uart1_rts: uart1-rts {
1310 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1313 uart1_rts_pin: uart1-rts-pin {
1314 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1319 uart2m0_xfer: uart2m0-xfer {
1320 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1321 <1 RK_PA1 2 &pcfg_pull_up>;
1326 uart2m1_xfer: uart2m1-xfer {
1327 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1328 <2 RK_PA1 1 &pcfg_pull_up>;
1333 spi0m0_clk: spi0m0-clk {
1334 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1337 spi0m0_cs0: spi0m0-cs0 {
1338 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1341 spi0m0_tx: spi0m0-tx {
1342 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1345 spi0m0_rx: spi0m0-rx {
1346 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1349 spi0m0_cs1: spi0m0-cs1 {
1350 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1355 spi0m1_clk: spi0m1-clk {
1356 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1359 spi0m1_cs0: spi0m1-cs0 {
1360 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1363 spi0m1_tx: spi0m1-tx {
1364 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1367 spi0m1_rx: spi0m1-rx {
1368 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1371 spi0m1_cs1: spi0m1-cs1 {
1372 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1377 spi0m2_clk: spi0m2-clk {
1378 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1381 spi0m2_cs0: spi0m2-cs0 {
1382 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1385 spi0m2_tx: spi0m2-tx {
1386 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1389 spi0m2_rx: spi0m2-rx {
1390 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1395 i2s1_mclk: i2s1-mclk {
1396 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1399 i2s1_sclk: i2s1-sclk {
1400 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1403 i2s1_lrckrx: i2s1-lrckrx {
1404 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1407 i2s1_lrcktx: i2s1-lrcktx {
1408 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1411 i2s1_sdi: i2s1-sdi {
1412 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1415 i2s1_sdo: i2s1-sdo {
1416 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1419 i2s1_sdio1: i2s1-sdio1 {
1420 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1423 i2s1_sdio2: i2s1-sdio2 {
1424 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1427 i2s1_sdio3: i2s1-sdio3 {
1428 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1431 i2s1_sleep: i2s1-sleep {
1433 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1434 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1435 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1436 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1437 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1438 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1439 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1440 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1441 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1446 i2s2m0_mclk: i2s2m0-mclk {
1447 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1450 i2s2m0_sclk: i2s2m0-sclk {
1451 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1454 i2s2m0_lrckrx: i2s2m0-lrckrx {
1455 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1458 i2s2m0_lrcktx: i2s2m0-lrcktx {
1459 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1462 i2s2m0_sdi: i2s2m0-sdi {
1463 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1466 i2s2m0_sdo: i2s2m0-sdo {
1467 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1470 i2s2m0_sleep: i2s2m0-sleep {
1472 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1473 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1474 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1475 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1476 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1477 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1482 i2s2m1_mclk: i2s2m1-mclk {
1483 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1486 i2s2m1_sclk: i2s2m1-sclk {
1487 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1490 i2s2m1_lrckrx: i2sm1-lrckrx {
1491 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1494 i2s2m1_lrcktx: i2s2m1-lrcktx {
1495 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1498 i2s2m1_sdi: i2s2m1-sdi {
1499 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1502 i2s2m1_sdo: i2s2m1-sdo {
1503 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1506 i2s2m1_sleep: i2s2m1-sleep {
1508 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1509 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1510 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1511 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1512 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1517 spdifm0_tx: spdifm0-tx {
1518 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1523 spdifm1_tx: spdifm1-tx {
1524 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1529 spdifm2_tx: spdifm2-tx {
1530 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1535 sdmmc0m0_pwren: sdmmc0m0-pwren {
1536 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1539 sdmmc0m0_pin: sdmmc0m0-pin {
1540 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1545 sdmmc0m1_pwren: sdmmc0m1-pwren {
1546 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1549 sdmmc0m1_pin: sdmmc0m1-pin {
1550 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1555 sdmmc0_clk: sdmmc0-clk {
1556 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1559 sdmmc0_cmd: sdmmc0-cmd {
1560 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1563 sdmmc0_dectn: sdmmc0-dectn {
1564 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1567 sdmmc0_wrprt: sdmmc0-wrprt {
1568 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1571 sdmmc0_bus1: sdmmc0-bus1 {
1572 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1575 sdmmc0_bus4: sdmmc0-bus4 {
1576 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1577 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1578 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1579 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1582 sdmmc0_pins: sdmmc0-pins {
1584 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1588 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1589 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1590 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1591 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1596 sdmmc0ext_clk: sdmmc0ext-clk {
1597 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1600 sdmmc0ext_cmd: sdmmc0ext-cmd {
1601 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1604 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1605 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1608 sdmmc0ext_dectn: sdmmc0ext-dectn {
1609 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1612 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1613 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1616 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1618 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1619 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1620 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1621 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1624 sdmmc0ext_pins: sdmmc0ext-pins {
1626 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1638 sdmmc1_clk: sdmmc1-clk {
1639 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1642 sdmmc1_cmd: sdmmc1-cmd {
1643 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1646 sdmmc1_pwren: sdmmc1-pwren {
1647 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1650 sdmmc1_wrprt: sdmmc1-wrprt {
1651 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1654 sdmmc1_dectn: sdmmc1-dectn {
1655 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1658 sdmmc1_bus1: sdmmc1-bus1 {
1659 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1662 sdmmc1_bus4: sdmmc1-bus4 {
1663 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1664 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1665 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1666 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1669 sdmmc1_pins: sdmmc1-pins {
1671 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1672 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1673 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1674 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1675 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1676 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1677 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1678 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1679 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1684 emmc_clk: emmc-clk {
1685 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1688 emmc_cmd: emmc-cmd {
1689 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1692 emmc_pwren: emmc-pwren {
1693 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1696 emmc_rstnout: emmc-rstnout {
1697 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1700 emmc_bus1: emmc-bus1 {
1701 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1704 emmc_bus4: emmc-bus4 {
1706 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1707 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1708 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1709 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1712 emmc_bus8: emmc-bus8 {
1714 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1715 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1716 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1717 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1718 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1719 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1720 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1721 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1726 pwm0_pin: pwm0-pin {
1727 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1732 pwm1_pin: pwm1-pin {
1733 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1738 pwm2_pin: pwm2-pin {
1739 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1744 pwmir_pin: pwmir-pin {
1745 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1750 rgmiim1_pins: rgmiim1-pins {
1753 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1755 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1757 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1759 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1761 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1763 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1765 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1767 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1769 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1771 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1773 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1775 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1777 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1779 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1781 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1784 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1786 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1788 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1790 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1792 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1794 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1796 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1799 rmiim1_pins: rmiim1-pins {
1802 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1804 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1806 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1808 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1810 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1812 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1814 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1816 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1818 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1820 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1823 <0 RK_PB3 1 &pcfg_pull_none>,
1825 <0 RK_PB4 1 &pcfg_pull_none>,
1827 <0 RK_PD0 1 &pcfg_pull_none>,
1829 <0 RK_PC3 1 &pcfg_pull_none>,
1831 <0 RK_PC0 1 &pcfg_pull_none>,
1833 <0 RK_PC1 1 &pcfg_pull_none>;
1838 fephyled_speed10: fephyled-speed10 {
1839 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1842 fephyled_duplex: fephyled-duplex {
1843 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1846 fephyled_rxm1: fephyled-rxm1 {
1847 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1850 fephyled_txm1: fephyled-txm1 {
1851 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1854 fephyled_linkm1: fephyled-linkm1 {
1855 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1860 tsadc_int: tsadc-int {
1861 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1863 tsadc_pin: tsadc-pin {
1864 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1869 hdmi_cec: hdmi-cec {
1870 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1873 hdmi_hpd: hdmi-hpd {
1874 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1879 dvp_d2d9_m0:dvp-d2d9-m0 {
1882 <3 RK_PA4 2 &pcfg_pull_none>,
1884 <3 RK_PA5 2 &pcfg_pull_none>,
1886 <3 RK_PA6 2 &pcfg_pull_none>,
1888 <3 RK_PA7 2 &pcfg_pull_none>,
1890 <3 RK_PB0 2 &pcfg_pull_none>,
1892 <3 RK_PB1 2 &pcfg_pull_none>,
1894 <3 RK_PB2 2 &pcfg_pull_none>,
1896 <3 RK_PB3 2 &pcfg_pull_none>,
1898 <3 RK_PA1 2 &pcfg_pull_none>,
1900 <3 RK_PA0 2 &pcfg_pull_none>,
1902 <3 RK_PA3 2 &pcfg_pull_none>,
1904 <3 RK_PA2 2 &pcfg_pull_none>;
1909 dvp_d2d9_m1:dvp-d2d9-m1 {
1912 <3 RK_PA4 2 &pcfg_pull_none>,
1914 <3 RK_PA5 2 &pcfg_pull_none>,
1916 <3 RK_PA6 2 &pcfg_pull_none>,
1918 <3 RK_PA7 2 &pcfg_pull_none>,
1920 <3 RK_PB0 2 &pcfg_pull_none>,
1922 <2 RK_PC0 4 &pcfg_pull_none>,
1924 <2 RK_PC1 4 &pcfg_pull_none>,
1926 <2 RK_PC2 4 &pcfg_pull_none>,
1928 <3 RK_PA1 2 &pcfg_pull_none>,
1930 <3 RK_PA0 2 &pcfg_pull_none>,
1932 <2 RK_PB7 4 &pcfg_pull_none>,
1934 <3 RK_PA2 2 &pcfg_pull_none>;