arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         dynamic-power-coefficient = <120>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53                         reg = <0x0 0x1>;
  54                         clocks = <&cru ARMCLK>;
  55                         #cooling-cells = <2>;
  56                         dynamic-power-coefficient = <120>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         reg = <0x0 0x2>;
  66                         clocks = <&cru ARMCLK>;
  67                         #cooling-cells = <2>;
  68                         dynamic-power-coefficient = <120>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&l2>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x0 0x3>;
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>;
  80                         dynamic-power-coefficient = <120>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&l2>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                 };
  85
  86                 l2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         cpu0_opp_table: opp_table0 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-408000000 {
  96                         opp-hz = /bits/ 64 <408000000>;
  97                         opp-microvolt = <950000>;
  98                         clock-latency-ns = <40000>;
  99                         opp-suspend;
 100                 };
 101                 opp-600000000 {
 102                         opp-hz = /bits/ 64 <600000000>;
 103                         opp-microvolt = <950000>;
 104                         clock-latency-ns = <40000>;
 105                 };
 106                 opp-816000000 {
 107                         opp-hz = /bits/ 64 <816000000>;
 108                         opp-microvolt = <1000000>;
 109                         clock-latency-ns = <40000>;
 110                 };
 111                 opp-1008000000 {
 112                         opp-hz = /bits/ 64 <1008000000>;
 113                         opp-microvolt = <1100000>;
 114                         clock-latency-ns = <40000>;
 115                 };
 116                 opp-1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1225000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp-1296000000 {
 122                         opp-hz = /bits/ 64 <1296000000>;
 123                         opp-microvolt = <1300000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126         };
 127
 128         amba {
 129                 compatible = "simple-bus";
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 dmac: dmac@ff1f0000 {
 135                         compatible = "arm,pl330", "arm,primecell";
 136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru ACLK_DMAC>;
 140                         clock-names = "apb_pclk";
 141                         #dma-cells = <1>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         display_subsystem: display-subsystem {
 155                 compatible = "rockchip,display-subsystem";
 156                 ports = <&vop_out>;
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv8-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 170         };
 171
 172         xin24m: xin24m {
 173                 compatible = "fixed-clock";
 174                 #clock-cells = <0>;
 175                 clock-frequency = <24000000>;
 176                 clock-output-names = "xin24m";
 177         };
 178
 179         i2s0: i2s@ff000000 {
 180                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 181                 reg = <0x0 0xff000000 0x0 0x1000>;
 182                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 184                 clock-names = "i2s_clk", "i2s_hclk";
 185                 dmas = <&dmac 11>, <&dmac 12>;
 186                 dma-names = "tx", "rx";
 187                 #sound-dai-cells = <0>;
 188                 status = "disabled";
 189         };
 190
 191         i2s1: i2s@ff010000 {
 192                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 193                 reg = <0x0 0xff010000 0x0 0x1000>;
 194                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 196                 clock-names = "i2s_clk", "i2s_hclk";
 197                 dmas = <&dmac 14>, <&dmac 15>;
 198                 dma-names = "tx", "rx";
 199                 #sound-dai-cells = <0>;
 200                 status = "disabled";
 201         };
 202
 203         i2s2: i2s@ff020000 {
 204                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 205                 reg = <0x0 0xff020000 0x0 0x1000>;
 206                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 208                 clock-names = "i2s_clk", "i2s_hclk";
 209                 dmas = <&dmac 0>, <&dmac 1>;
 210                 dma-names = "tx", "rx";
 211                 #sound-dai-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         spdif: spdif@ff030000 {
 216                 compatible = "rockchip,rk3328-spdif";
 217                 reg = <0x0 0xff030000 0x0 0x1000>;
 218                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 220                 clock-names = "mclk", "hclk";
 221                 dmas = <&dmac 10>;
 222                 dma-names = "tx";
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&spdifm2_tx>;
 225                 #sound-dai-cells = <0>;
 226                 status = "disabled";
 227         };
 228
 229         pdm: pdm@ff040000 {
 230                 compatible = "rockchip,pdm";
 231                 reg = <0x0 0xff040000 0x0 0x1000>;
 232                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 233                 clock-names = "pdm_clk", "pdm_hclk";
 234                 dmas = <&dmac 16>;
 235                 dma-names = "rx";
 236                 pinctrl-names = "default", "sleep";
 237                 pinctrl-0 = <&pdmm0_clk
 238                              &pdmm0_sdi0
 239                              &pdmm0_sdi1
 240                              &pdmm0_sdi2
 241                              &pdmm0_sdi3>;
 242                 pinctrl-1 = <&pdmm0_clk_sleep
 243                              &pdmm0_sdi0_sleep
 244                              &pdmm0_sdi1_sleep
 245                              &pdmm0_sdi2_sleep
 246                              &pdmm0_sdi3_sleep>;
 247                 status = "disabled";
 248         };
 249
 250         grf: syscon@ff100000 {
 251                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 252                 reg = <0x0 0xff100000 0x0 0x1000>;
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255
 256                 io_domains: io-domains {
 257                         compatible = "rockchip,rk3328-io-voltage-domain";
 258                         status = "disabled";
 259                 };
 260
 261                 grf_gpio: grf-gpio {
 262                         compatible = "rockchip,rk3328-grf-gpio";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                 };
 266
 267                 power: power-controller {
 268                         compatible = "rockchip,rk3328-power-controller";
 269                         #power-domain-cells = <1>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272
 273                         power-domain@RK3328_PD_HEVC {
 274                                 reg = <RK3328_PD_HEVC>;
 275                         };
 276                         power-domain@RK3328_PD_VIDEO {
 277                                 reg = <RK3328_PD_VIDEO>;
 278                         };
 279                         power-domain@RK3328_PD_VPU {
 280                                 reg = <RK3328_PD_VPU>;
 281                                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 282                         };
 283                 };
 284
 285                 reboot-mode {
 286                         compatible = "syscon-reboot-mode";
 287                         offset = <0x5c8>;
 288                         mode-normal = <BOOT_NORMAL>;
 289                         mode-recovery = <BOOT_RECOVERY>;
 290                         mode-bootloader = <BOOT_FASTBOOT>;
 291                         mode-loader = <BOOT_BL_DOWNLOAD>;
 292                 };
 293         };
 294
 295         uart0: serial@ff110000 {
 296                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 297                 reg = <0x0 0xff110000 0x0 0x100>;
 298                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 300                 clock-names = "baudclk", "apb_pclk";
 301                 dmas = <&dmac 2>, <&dmac 3>;
 302                 dma-names = "tx", "rx";
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 305                 reg-io-width = <4>;
 306                 reg-shift = <2>;
 307                 status = "disabled";
 308         };
 309
 310         uart1: serial@ff120000 {
 311                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 312                 reg = <0x0 0xff120000 0x0 0x100>;
 313                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 dmas = <&dmac 4>, <&dmac 5>;
 317                 dma-names = "tx", "rx";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 320                 reg-io-width = <4>;
 321                 reg-shift = <2>;
 322                 status = "disabled";
 323         };
 324
 325         uart2: serial@ff130000 {
 326                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 327                 reg = <0x0 0xff130000 0x0 0x100>;
 328                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 330                 clock-names = "baudclk", "apb_pclk";
 331                 dmas = <&dmac 6>, <&dmac 7>;
 332                 dma-names = "tx", "rx";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&uart2m1_xfer>;
 335                 reg-io-width = <4>;
 336                 reg-shift = <2>;
 337                 status = "disabled";
 338         };
 339
 340         i2c0: i2c@ff150000 {
 341                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 342                 reg = <0x0 0xff150000 0x0 0x1000>;
 343                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 347                 clock-names = "i2c", "pclk";
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&i2c0_xfer>;
 350                 status = "disabled";
 351         };
 352
 353         i2c1: i2c@ff160000 {
 354                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 355                 reg = <0x0 0xff160000 0x0 0x1000>;
 356                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 360                 clock-names = "i2c", "pclk";
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&i2c1_xfer>;
 363                 status = "disabled";
 364         };
 365
 366         i2c2: i2c@ff170000 {
 367                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 368                 reg = <0x0 0xff170000 0x0 0x1000>;
 369                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 373                 clock-names = "i2c", "pclk";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&i2c2_xfer>;
 376                 status = "disabled";
 377         };
 378
 379         i2c3: i2c@ff180000 {
 380                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 381                 reg = <0x0 0xff180000 0x0 0x1000>;
 382                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 386                 clock-names = "i2c", "pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&i2c3_xfer>;
 389                 status = "disabled";
 390         };
 391
 392         spi0: spi@ff190000 {
 393                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 394                 reg = <0x0 0xff190000 0x0 0x1000>;
 395                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 dmas = <&dmac 8>, <&dmac 9>;
 401                 dma-names = "tx", "rx";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 404                 status = "disabled";
 405         };
 406
 407         wdt: watchdog@ff1a0000 {
 408                 compatible = "snps,dw-wdt";
 409                 reg = <0x0 0xff1a0000 0x0 0x100>;
 410                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&cru PCLK_WDT>;
 412         };
 413
 414         pwm0: pwm@ff1b0000 {
 415                 compatible = "rockchip,rk3328-pwm";
 416                 reg = <0x0 0xff1b0000 0x0 0x10>;
 417                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 418                 clock-names = "pwm", "pclk";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&pwm0_pin>;
 421                 #pwm-cells = <3>;
 422                 status = "disabled";
 423         };
 424
 425         pwm1: pwm@ff1b0010 {
 426                 compatible = "rockchip,rk3328-pwm";
 427                 reg = <0x0 0xff1b0010 0x0 0x10>;
 428                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 429                 clock-names = "pwm", "pclk";
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pwm1_pin>;
 432                 #pwm-cells = <3>;
 433                 status = "disabled";
 434         };
 435
 436         pwm2: pwm@ff1b0020 {
 437                 compatible = "rockchip,rk3328-pwm";
 438                 reg = <0x0 0xff1b0020 0x0 0x10>;
 439                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 440                 clock-names = "pwm", "pclk";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&pwm2_pin>;
 443                 #pwm-cells = <3>;
 444                 status = "disabled";
 445         };
 446
 447         pwm3: pwm@ff1b0030 {
 448                 compatible = "rockchip,rk3328-pwm";
 449                 reg = <0x0 0xff1b0030 0x0 0x10>;
 450                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 452                 clock-names = "pwm", "pclk";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pwmir_pin>;
 455                 #pwm-cells = <3>;
 456                 status = "disabled";
 457         };
 458
 459         thermal-zones {
 460                 soc_thermal: soc-thermal {
 461                         polling-delay-passive = <20>;
 462                         polling-delay = <1000>;
 463                         sustainable-power = <1000>;
 464
 465                         thermal-sensors = <&tsadc 0>;
 466
 467                         trips {
 468                                 threshold: trip-point0 {
 469                                         temperature = <70000>;
 470                                         hysteresis = <2000>;
 471                                         type = "passive";
 472                                 };
 473                                 target: trip-point1 {
 474                                         temperature = <85000>;
 475                                         hysteresis = <2000>;
 476                                         type = "passive";
 477                                 };
 478                                 soc_crit: soc-crit {
 479                                         temperature = <95000>;
 480                                         hysteresis = <2000>;
 481                                         type = "critical";
 482                                 };
 483                         };
 484
 485                         cooling-maps {
 486                                 map0 {
 487                                         trip = <&target>;
 488                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 489                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 490                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 491                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 492                                         contribution = <4096>;
 493                                 };
 494                         };
 495                 };
 496
 497         };
 498
 499         tsadc: tsadc@ff250000 {
 500                 compatible = "rockchip,rk3328-tsadc";
 501                 reg = <0x0 0xff250000 0x0 0x100>;
 502                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 503                 assigned-clocks = <&cru SCLK_TSADC>;
 504                 assigned-clock-rates = <50000>;
 505                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 506                 clock-names = "tsadc", "apb_pclk";
 507                 pinctrl-names = "init", "default", "sleep";
 508                 pinctrl-0 = <&otp_gpio>;
 509                 pinctrl-1 = <&otp_out>;
 510                 pinctrl-2 = <&otp_gpio>;
 511                 resets = <&cru SRST_TSADC>;
 512                 reset-names = "tsadc-apb";
 513                 rockchip,grf = <&grf>;
 514                 rockchip,hw-tshut-temp = <100000>;
 515                 #thermal-sensor-cells = <1>;
 516                 status = "disabled";
 517         };
 518
 519         efuse: efuse@ff260000 {
 520                 compatible = "rockchip,rk3328-efuse";
 521                 reg = <0x0 0xff260000 0x0 0x50>;
 522                 #address-cells = <1>;
 523                 #size-cells = <1>;
 524                 clocks = <&cru SCLK_EFUSE>;
 525                 clock-names = "pclk_efuse";
 526                 rockchip,efuse-size = <0x20>;
 527
 528                 /* Data cells */
 529                 efuse_id: id@7 {
 530                         reg = <0x07 0x10>;
 531                 };
 532                 cpu_leakage: cpu-leakage@17 {
 533                         reg = <0x17 0x1>;
 534                 };
 535                 logic_leakage: logic-leakage@19 {
 536                         reg = <0x19 0x1>;
 537                 };
 538                 efuse_cpu_version: cpu-version@1a {
 539                         reg = <0x1a 0x1>;
 540                         bits = <3 3>;
 541                 };
 542         };
 543
 544         saradc: adc@ff280000 {
 545                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 546                 reg = <0x0 0xff280000 0x0 0x100>;
 547                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 548                 #io-channel-cells = <1>;
 549                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 550                 clock-names = "saradc", "apb_pclk";
 551                 resets = <&cru SRST_SARADC_P>;
 552                 reset-names = "saradc-apb";
 553                 status = "disabled";
 554         };
 555
 556         gpu: gpu@ff300000 {
 557                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 558                 reg = <0x0 0xff300000 0x0 0x30000>;
 559                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 560                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 561                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 562                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 563                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 564                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 565                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 566                 interrupt-names = "gp",
 567                                   "gpmmu",
 568                                   "pp",
 569                                   "pp0",
 570                                   "ppmmu0",
 571                                   "pp1",
 572                                   "ppmmu1";
 573                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 574                 clock-names = "bus", "core";
 575                 resets = <&cru SRST_GPU_A>;
 576         };
 577
 578         h265e_mmu: iommu@ff330200 {
 579                 compatible = "rockchip,iommu";
 580                 reg = <0x0 0xff330200 0 0x100>;
 581                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 582                 interrupt-names = "h265e_mmu";
 583                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 584                 clock-names = "aclk", "iface";
 585                 #iommu-cells = <0>;
 586                 status = "disabled";
 587         };
 588
 589         vepu_mmu: iommu@ff340800 {
 590                 compatible = "rockchip,iommu";
 591                 reg = <0x0 0xff340800 0x0 0x40>;
 592                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 593                 interrupt-names = "vepu_mmu";
 594                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 595                 clock-names = "aclk", "iface";
 596                 #iommu-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         vpu: video-codec@ff350000 {
 601                 compatible = "rockchip,rk3328-vpu";
 602                 reg = <0x0 0xff350000 0x0 0x800>;
 603                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 604                 interrupt-names = "vdpu";
 605                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 606                 clock-names = "aclk", "hclk";
 607                 iommus = <&vpu_mmu>;
 608                 power-domains = <&power RK3328_PD_VPU>;
 609         };
 610
 611         vpu_mmu: iommu@ff350800 {
 612                 compatible = "rockchip,iommu";
 613                 reg = <0x0 0xff350800 0x0 0x40>;
 614                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 615                 interrupt-names = "vpu_mmu";
 616                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 617                 clock-names = "aclk", "iface";
 618                 #iommu-cells = <0>;
 619                 power-domains = <&power RK3328_PD_VPU>;
 620         };
 621
 622         rkvdec_mmu: iommu@ff360480 {
 623                 compatible = "rockchip,iommu";
 624                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 625                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 626                 interrupt-names = "rkvdec_mmu";
 627                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 628                 clock-names = "aclk", "iface";
 629                 #iommu-cells = <0>;
 630                 status = "disabled";
 631         };
 632
 633         vop: vop@ff370000 {
 634                 compatible = "rockchip,rk3328-vop";
 635                 reg = <0x0 0xff370000 0x0 0x3efc>;
 636                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 638                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 639                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 640                 reset-names = "axi", "ahb", "dclk";
 641                 iommus = <&vop_mmu>;
 642                 status = "disabled";
 643
 644                 vop_out: port {
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647
 648                         vop_out_hdmi: endpoint@0 {
 649                                 reg = <0>;
 650                                 remote-endpoint = <&hdmi_in_vop>;
 651                         };
 652                 };
 653         };
 654
 655         vop_mmu: iommu@ff373f00 {
 656                 compatible = "rockchip,iommu";
 657                 reg = <0x0 0xff373f00 0x0 0x100>;
 658                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 659                 interrupt-names = "vop_mmu";
 660                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 661                 clock-names = "aclk", "iface";
 662                 #iommu-cells = <0>;
 663                 status = "disabled";
 664         };
 665
 666         hdmi: hdmi@ff3c0000 {
 667                 compatible = "rockchip,rk3328-dw-hdmi";
 668                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 669                 reg-io-width = <4>;
 670                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 671                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 672                 clocks = <&cru PCLK_HDMI>,
 673                          <&cru SCLK_HDMI_SFC>,
 674                          <&cru SCLK_RTC32K>;
 675                 clock-names = "iahb",
 676                               "isfr",
 677                               "cec";
 678                 phys = <&hdmiphy>;
 679                 phy-names = "hdmi";
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 682                 rockchip,grf = <&grf>;
 683                 #sound-dai-cells = <0>;
 684                 status = "disabled";
 685
 686                 ports {
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689
 690                         hdmi_in: port@0 {
 691                                 reg = <0>;
 692
 693                                 hdmi_in_vop: endpoint {
 694                                         remote-endpoint = <&vop_out_hdmi>;
 695                                 };
 696                         };
 697
 698                         hdmi_out: port@1 {
 699                                 reg = <1>;
 700                         };
 701                 };
 702         };
 703
 704         codec: codec@ff410000 {
 705                 compatible = "rockchip,rk3328-codec";
 706                 reg = <0x0 0xff410000 0x0 0x1000>;
 707                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 708                 clock-names = "pclk", "mclk";
 709                 rockchip,grf = <&grf>;
 710                 #sound-dai-cells = <0>;
 711                 status = "disabled";
 712         };
 713
 714         hdmiphy: phy@ff430000 {
 715                 compatible = "rockchip,rk3328-hdmi-phy";
 716                 reg = <0x0 0xff430000 0x0 0x10000>;
 717                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 718                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 719                 clock-names = "sysclk", "refoclk", "refpclk";
 720                 clock-output-names = "hdmi_phy";
 721                 #clock-cells = <0>;
 722                 nvmem-cells = <&efuse_cpu_version>;
 723                 nvmem-cell-names = "cpu-version";
 724                 #phy-cells = <0>;
 725                 status = "disabled";
 726         };
 727
 728         cru: clock-controller@ff440000 {
 729                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 730                 reg = <0x0 0xff440000 0x0 0x1000>;
 731                 rockchip,grf = <&grf>;
 732                 #clock-cells = <1>;
 733                 #reset-cells = <1>;
 734                 assigned-clocks =
 735                         /*
 736                          * CPLL should run at 1200, but that is to high for
 737                          * the initial dividers of most of its children.
 738                          * We need set cpll child clk div first,
 739                          * and then set the cpll frequency.
 740                          */
 741                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 742                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 743                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 744                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 745                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 746                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 747                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 748                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 749                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 750                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 751                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 752                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 753                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 754                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 755                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 756                         <&cru SCLK_RTC32K>;
 757                 assigned-clock-parents =
 758                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 759                         <&cru PLL_GPLL>, <&xin24m>,
 760                         <&xin24m>, <&xin24m>;
 761                 assigned-clock-rates =
 762                         <0>, <61440000>,
 763                         <0>, <24000000>,
 764                         <24000000>, <24000000>,
 765                         <15000000>, <15000000>,
 766                         <100000000>, <100000000>,
 767                         <100000000>, <100000000>,
 768                         <50000000>, <100000000>,
 769                         <100000000>, <100000000>,
 770                         <50000000>, <50000000>,
 771                         <50000000>, <50000000>,
 772                         <24000000>, <600000000>,
 773                         <491520000>, <1200000000>,
 774                         <150000000>, <75000000>,
 775                         <75000000>, <150000000>,
 776                         <75000000>, <75000000>,
 777                         <32768>;
 778         };
 779
 780         usb2phy_grf: syscon@ff450000 {
 781                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 782                              "simple-mfd";
 783                 reg = <0x0 0xff450000 0x0 0x10000>;
 784                 #address-cells = <1>;
 785                 #size-cells = <1>;
 786
 787                 u2phy: usb2-phy@100 {
 788                         compatible = "rockchip,rk3328-usb2phy";
 789                         reg = <0x100 0x10>;
 790                         clocks = <&xin24m>;
 791                         clock-names = "phyclk";
 792                         clock-output-names = "usb480m_phy";
 793                         #clock-cells = <0>;
 794                         assigned-clocks = <&cru USB480M>;
 795                         assigned-clock-parents = <&u2phy>;
 796                         status = "disabled";
 797
 798                         u2phy_otg: otg-port {
 799                                 #phy-cells = <0>;
 800                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 801                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 802                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 803                                 interrupt-names = "otg-bvalid", "otg-id",
 804                                                   "linestate";
 805                                 status = "disabled";
 806                         };
 807
 808                         u2phy_host: host-port {
 809                                 #phy-cells = <0>;
 810                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 811                                 interrupt-names = "linestate";
 812                                 status = "disabled";
 813                         };
 814                 };
 815         };
 816
 817         sdmmc: dwmmc@ff500000 {
 818                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 819                 reg = <0x0 0xff500000 0x0 0x4000>;
 820                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 821                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 822                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 823                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 824                 fifo-depth = <0x100>;
 825                 max-frequency = <150000000>;
 826                 status = "disabled";
 827         };
 828
 829         sdio: dwmmc@ff510000 {
 830                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 831                 reg = <0x0 0xff510000 0x0 0x4000>;
 832                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 833                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 834                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 835                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 836                 fifo-depth = <0x100>;
 837                 max-frequency = <150000000>;
 838                 status = "disabled";
 839         };
 840
 841         emmc: dwmmc@ff520000 {
 842                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 843                 reg = <0x0 0xff520000 0x0 0x4000>;
 844                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 845                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 846                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 847                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 848                 fifo-depth = <0x100>;
 849                 max-frequency = <150000000>;
 850                 status = "disabled";
 851         };
 852
 853         gmac2io: ethernet@ff540000 {
 854                 compatible = "rockchip,rk3328-gmac";
 855                 reg = <0x0 0xff540000 0x0 0x10000>;
 856                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 857                 interrupt-names = "macirq";
 858                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 859                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 860                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 861                          <&cru PCLK_MAC2IO>;
 862                 clock-names = "stmmaceth", "mac_clk_rx",
 863                               "mac_clk_tx", "clk_mac_ref",
 864                               "clk_mac_refout", "aclk_mac",
 865                               "pclk_mac";
 866                 resets = <&cru SRST_GMAC2IO_A>;
 867                 reset-names = "stmmaceth";
 868                 rockchip,grf = <&grf>;
 869                 status = "disabled";
 870         };
 871
 872         gmac2phy: ethernet@ff550000 {
 873                 compatible = "rockchip,rk3328-gmac";
 874                 reg = <0x0 0xff550000 0x0 0x10000>;
 875                 rockchip,grf = <&grf>;
 876                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 877                 interrupt-names = "macirq";
 878                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 879                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 880                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 881                          <&cru SCLK_MAC2PHY_OUT>;
 882                 clock-names = "stmmaceth", "mac_clk_rx",
 883                               "mac_clk_tx", "clk_mac_ref",
 884                               "aclk_mac", "pclk_mac",
 885                               "clk_macphy";
 886                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 887                 reset-names = "stmmaceth", "mac-phy";
 888                 phy-mode = "rmii";
 889                 phy-handle = <&phy>;
 890                 status = "disabled";
 891
 892                 mdio {
 893                         compatible = "snps,dwmac-mdio";
 894                         #address-cells = <1>;
 895                         #size-cells = <0>;
 896
 897                         phy: phy@0 {
 898                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 899                                 reg = <0>;
 900                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 901                                 resets = <&cru SRST_MACPHY>;
 902                                 pinctrl-names = "default";
 903                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 904                                 phy-is-integrated;
 905                         };
 906                 };
 907         };
 908
 909         usb20_otg: usb@ff580000 {
 910                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 911                              "snps,dwc2";
 912                 reg = <0x0 0xff580000 0x0 0x40000>;
 913                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 914                 clocks = <&cru HCLK_OTG>;
 915                 clock-names = "otg";
 916                 dr_mode = "otg";
 917                 g-np-tx-fifo-size = <16>;
 918                 g-rx-fifo-size = <280>;
 919                 g-tx-fifo-size = <256 128 128 64 32 16>;
 920                 g-use-dma;
 921                 phys = <&u2phy_otg>;
 922                 phy-names = "usb2-phy";
 923                 status = "disabled";
 924         };
 925
 926         usb_host0_ehci: usb@ff5c0000 {
 927                 compatible = "generic-ehci";
 928                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 929                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 930                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 931                 clock-names = "usbhost", "utmi";
 932                 phys = <&u2phy_host>;
 933                 phy-names = "usb";
 934                 status = "disabled";
 935         };
 936
 937         usb_host0_ohci: usb@ff5d0000 {
 938                 compatible = "generic-ohci";
 939                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 940                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 941                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 942                 clock-names = "usbhost", "utmi";
 943                 phys = <&u2phy_host>;
 944                 phy-names = "usb";
 945                 status = "disabled";
 946         };
 947
 948         gic: interrupt-controller@ff811000 {
 949                 compatible = "arm,gic-400";
 950                 #interrupt-cells = <3>;
 951                 #address-cells = <0>;
 952                 interrupt-controller;
 953                 reg = <0x0 0xff811000 0 0x1000>,
 954                       <0x0 0xff812000 0 0x2000>,
 955                       <0x0 0xff814000 0 0x2000>,
 956                       <0x0 0xff816000 0 0x2000>;
 957                 interrupts = <GIC_PPI 9
 958                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 959         };
 960
 961         pinctrl: pinctrl {
 962                 compatible = "rockchip,rk3328-pinctrl";
 963                 rockchip,grf = <&grf>;
 964                 #address-cells = <2>;
 965                 #size-cells = <2>;
 966                 ranges;
 967
 968                 gpio0: gpio0@ff210000 {
 969                         compatible = "rockchip,gpio-bank";
 970                         reg = <0x0 0xff210000 0x0 0x100>;
 971                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&cru PCLK_GPIO0>;
 973
 974                         gpio-controller;
 975                         #gpio-cells = <2>;
 976
 977                         interrupt-controller;
 978                         #interrupt-cells = <2>;
 979                 };
 980
 981                 gpio1: gpio1@ff220000 {
 982                         compatible = "rockchip,gpio-bank";
 983                         reg = <0x0 0xff220000 0x0 0x100>;
 984                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&cru PCLK_GPIO1>;
 986
 987                         gpio-controller;
 988                         #gpio-cells = <2>;
 989
 990                         interrupt-controller;
 991                         #interrupt-cells = <2>;
 992                 };
 993
 994                 gpio2: gpio2@ff230000 {
 995                         compatible = "rockchip,gpio-bank";
 996                         reg = <0x0 0xff230000 0x0 0x100>;
 997                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&cru PCLK_GPIO2>;
 999
1000                         gpio-controller;
1001                         #gpio-cells = <2>;
1002
1003                         interrupt-controller;
1004                         #interrupt-cells = <2>;
1005                 };
1006
1007                 gpio3: gpio3@ff240000 {
1008                         compatible = "rockchip,gpio-bank";
1009                         reg = <0x0 0xff240000 0x0 0x100>;
1010                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1011                         clocks = <&cru PCLK_GPIO3>;
1012
1013                         gpio-controller;
1014                         #gpio-cells = <2>;
1015
1016                         interrupt-controller;
1017                         #interrupt-cells = <2>;
1018                 };
1019
1020                 pcfg_pull_up: pcfg-pull-up {
1021                         bias-pull-up;
1022                 };
1023
1024                 pcfg_pull_down: pcfg-pull-down {
1025                         bias-pull-down;
1026                 };
1027
1028                 pcfg_pull_none: pcfg-pull-none {
1029                         bias-disable;
1030                 };
1031
1032                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1033                         bias-disable;
1034                         drive-strength = <2>;
1035                 };
1036
1037                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1038                         bias-pull-up;
1039                         drive-strength = <2>;
1040                 };
1041
1042                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1043                         bias-pull-up;
1044                         drive-strength = <4>;
1045                 };
1046
1047                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1048                         bias-disable;
1049                         drive-strength = <4>;
1050                 };
1051
1052                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1053                         bias-pull-down;
1054                         drive-strength = <4>;
1055                 };
1056
1057                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1058                         bias-disable;
1059                         drive-strength = <8>;
1060                 };
1061
1062                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1063                         bias-pull-up;
1064                         drive-strength = <8>;
1065                 };
1066
1067                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1068                         bias-disable;
1069                         drive-strength = <12>;
1070                 };
1071
1072                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1073                         bias-pull-up;
1074                         drive-strength = <12>;
1075                 };
1076
1077                 pcfg_output_high: pcfg-output-high {
1078                         output-high;
1079                 };
1080
1081                 pcfg_output_low: pcfg-output-low {
1082                         output-low;
1083                 };
1084
1085                 pcfg_input_high: pcfg-input-high {
1086                         bias-pull-up;
1087                         input-enable;
1088                 };
1089
1090                 pcfg_input: pcfg-input {
1091                         input-enable;
1092                 };
1093
1094                 i2c0 {
1095                         i2c0_xfer: i2c0-xfer {
1096                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1097                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1098                         };
1099                 };
1100
1101                 i2c1 {
1102                         i2c1_xfer: i2c1-xfer {
1103                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1104                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1105                         };
1106                 };
1107
1108                 i2c2 {
1109                         i2c2_xfer: i2c2-xfer {
1110                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1111                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 i2c3 {
1116                         i2c3_xfer: i2c3-xfer {
1117                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1118                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1119                         };
1120                         i2c3_gpio: i2c3-gpio {
1121                                 rockchip,pins =
1122                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1123                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1124                         };
1125                 };
1126
1127                 hdmi_i2c {
1128                         hdmii2c_xfer: hdmii2c-xfer {
1129                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1130                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1131                         };
1132                 };
1133
1134                 pdm-0 {
1135                         pdmm0_clk: pdmm0-clk {
1136                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1137                         };
1138
1139                         pdmm0_fsync: pdmm0-fsync {
1140                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1141                         };
1142
1143                         pdmm0_sdi0: pdmm0-sdi0 {
1144                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1145                         };
1146
1147                         pdmm0_sdi1: pdmm0-sdi1 {
1148                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1149                         };
1150
1151                         pdmm0_sdi2: pdmm0-sdi2 {
1152                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1153                         };
1154
1155                         pdmm0_sdi3: pdmm0-sdi3 {
1156                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1157                         };
1158
1159                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1160                                 rockchip,pins =
1161                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1162                         };
1163
1164                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1165                                 rockchip,pins =
1166                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1167                         };
1168
1169                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1170                                 rockchip,pins =
1171                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1172                         };
1173
1174                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1175                                 rockchip,pins =
1176                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1177                         };
1178
1179                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1180                                 rockchip,pins =
1181                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1182                         };
1183
1184                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1185                                 rockchip,pins =
1186                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1187                         };
1188                 };
1189
1190                 tsadc {
1191                         otp_gpio: otp-gpio {
1192                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1193                         };
1194
1195                         otp_out: otp-out {
1196                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1197                         };
1198                 };
1199
1200                 uart0 {
1201                         uart0_xfer: uart0-xfer {
1202                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1203                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1204                         };
1205
1206                         uart0_cts: uart0-cts {
1207                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1208                         };
1209
1210                         uart0_rts: uart0-rts {
1211                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1212                         };
1213
1214                         uart0_rts_gpio: uart0-rts-gpio {
1215                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1216                         };
1217                 };
1218
1219                 uart1 {
1220                         uart1_xfer: uart1-xfer {
1221                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1222                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1223                         };
1224
1225                         uart1_cts: uart1-cts {
1226                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1227                         };
1228
1229                         uart1_rts: uart1-rts {
1230                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1231                         };
1232
1233                         uart1_rts_gpio: uart1-rts-gpio {
1234                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1235                         };
1236                 };
1237
1238                 uart2-0 {
1239                         uart2m0_xfer: uart2m0-xfer {
1240                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1241                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1242                         };
1243                 };
1244
1245                 uart2-1 {
1246                         uart2m1_xfer: uart2m1-xfer {
1247                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1248                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1249                         };
1250                 };
1251
1252                 spi0-0 {
1253                         spi0m0_clk: spi0m0-clk {
1254                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1255                         };
1256
1257                         spi0m0_cs0: spi0m0-cs0 {
1258                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1259                         };
1260
1261                         spi0m0_tx: spi0m0-tx {
1262                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1263                         };
1264
1265                         spi0m0_rx: spi0m0-rx {
1266                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1267                         };
1268
1269                         spi0m0_cs1: spi0m0-cs1 {
1270                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1271                         };
1272                 };
1273
1274                 spi0-1 {
1275                         spi0m1_clk: spi0m1-clk {
1276                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1277                         };
1278
1279                         spi0m1_cs0: spi0m1-cs0 {
1280                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1281                         };
1282
1283                         spi0m1_tx: spi0m1-tx {
1284                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1285                         };
1286
1287                         spi0m1_rx: spi0m1-rx {
1288                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1289                         };
1290
1291                         spi0m1_cs1: spi0m1-cs1 {
1292                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1293                         };
1294                 };
1295
1296                 spi0-2 {
1297                         spi0m2_clk: spi0m2-clk {
1298                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1299                         };
1300
1301                         spi0m2_cs0: spi0m2-cs0 {
1302                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1303                         };
1304
1305                         spi0m2_tx: spi0m2-tx {
1306                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1307                         };
1308
1309                         spi0m2_rx: spi0m2-rx {
1310                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1311                         };
1312                 };
1313
1314                 i2s1 {
1315                         i2s1_mclk: i2s1-mclk {
1316                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1317                         };
1318
1319                         i2s1_sclk: i2s1-sclk {
1320                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1321                         };
1322
1323                         i2s1_lrckrx: i2s1-lrckrx {
1324                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1325                         };
1326
1327                         i2s1_lrcktx: i2s1-lrcktx {
1328                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1329                         };
1330
1331                         i2s1_sdi: i2s1-sdi {
1332                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1333                         };
1334
1335                         i2s1_sdo: i2s1-sdo {
1336                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1337                         };
1338
1339                         i2s1_sdio1: i2s1-sdio1 {
1340                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1341                         };
1342
1343                         i2s1_sdio2: i2s1-sdio2 {
1344                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1345                         };
1346
1347                         i2s1_sdio3: i2s1-sdio3 {
1348                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1349                         };
1350
1351                         i2s1_sleep: i2s1-sleep {
1352                                 rockchip,pins =
1353                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1354                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1355                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1356                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1357                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1358                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1359                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1360                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1361                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1362                         };
1363                 };
1364
1365                 i2s2-0 {
1366                         i2s2m0_mclk: i2s2m0-mclk {
1367                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1368                         };
1369
1370                         i2s2m0_sclk: i2s2m0-sclk {
1371                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1372                         };
1373
1374                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1375                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1376                         };
1377
1378                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1379                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1380                         };
1381
1382                         i2s2m0_sdi: i2s2m0-sdi {
1383                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1384                         };
1385
1386                         i2s2m0_sdo: i2s2m0-sdo {
1387                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1388                         };
1389
1390                         i2s2m0_sleep: i2s2m0-sleep {
1391                                 rockchip,pins =
1392                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1393                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1394                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1395                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1396                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1397                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1398                         };
1399                 };
1400
1401                 i2s2-1 {
1402                         i2s2m1_mclk: i2s2m1-mclk {
1403                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1404                         };
1405
1406                         i2s2m1_sclk: i2s2m1-sclk {
1407                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1408                         };
1409
1410                         i2s2m1_lrckrx: i2sm1-lrckrx {
1411                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1412                         };
1413
1414                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1415                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1416                         };
1417
1418                         i2s2m1_sdi: i2s2m1-sdi {
1419                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1420                         };
1421
1422                         i2s2m1_sdo: i2s2m1-sdo {
1423                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1424                         };
1425
1426                         i2s2m1_sleep: i2s2m1-sleep {
1427                                 rockchip,pins =
1428                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1429                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1430                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1431                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1432                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1433                         };
1434                 };
1435
1436                 spdif-0 {
1437                         spdifm0_tx: spdifm0-tx {
1438                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 spdif-1 {
1443                         spdifm1_tx: spdifm1-tx {
1444                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1445                         };
1446                 };
1447
1448                 spdif-2 {
1449                         spdifm2_tx: spdifm2-tx {
1450                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1451                         };
1452                 };
1453
1454                 sdmmc0-0 {
1455                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1456                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1457                         };
1458
1459                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1460                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1461                         };
1462                 };
1463
1464                 sdmmc0-1 {
1465                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1466                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1467                         };
1468
1469                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1470                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1471                         };
1472                 };
1473
1474                 sdmmc0 {
1475                         sdmmc0_clk: sdmmc0-clk {
1476                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1477                         };
1478
1479                         sdmmc0_cmd: sdmmc0-cmd {
1480                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1481                         };
1482
1483                         sdmmc0_dectn: sdmmc0-dectn {
1484                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1485                         };
1486
1487                         sdmmc0_wrprt: sdmmc0-wrprt {
1488                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1489                         };
1490
1491                         sdmmc0_bus1: sdmmc0-bus1 {
1492                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1493                         };
1494
1495                         sdmmc0_bus4: sdmmc0-bus4 {
1496                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1497                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1498                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1499                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1500                         };
1501
1502                         sdmmc0_gpio: sdmmc0-gpio {
1503                                 rockchip,pins =
1504                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1507                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1509                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1510                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1511                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1512                         };
1513                 };
1514
1515                 sdmmc0ext {
1516                         sdmmc0ext_clk: sdmmc0ext-clk {
1517                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1518                         };
1519
1520                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1521                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1522                         };
1523
1524                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1525                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1526                         };
1527
1528                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1529                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1530                         };
1531
1532                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1533                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1534                         };
1535
1536                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1537                                 rockchip,pins =
1538                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1539                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1540                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1541                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1542                         };
1543
1544                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1545                                 rockchip,pins =
1546                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1547                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1548                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1549                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1550                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1551                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1552                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1553                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1554                         };
1555                 };
1556
1557                 sdmmc1 {
1558                         sdmmc1_clk: sdmmc1-clk {
1559                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1560                         };
1561
1562                         sdmmc1_cmd: sdmmc1-cmd {
1563                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1564                         };
1565
1566                         sdmmc1_pwren: sdmmc1-pwren {
1567                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1568                         };
1569
1570                         sdmmc1_wrprt: sdmmc1-wrprt {
1571                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1572                         };
1573
1574                         sdmmc1_dectn: sdmmc1-dectn {
1575                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1576                         };
1577
1578                         sdmmc1_bus1: sdmmc1-bus1 {
1579                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1580                         };
1581
1582                         sdmmc1_bus4: sdmmc1-bus4 {
1583                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1584                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1585                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1586                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1587                         };
1588
1589                         sdmmc1_gpio: sdmmc1-gpio {
1590                                 rockchip,pins =
1591                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1592                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1593                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1594                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1595                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1596                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1597                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1598                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1599                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1600                         };
1601                 };
1602
1603                 emmc {
1604                         emmc_clk: emmc-clk {
1605                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1606                         };
1607
1608                         emmc_cmd: emmc-cmd {
1609                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1610                         };
1611
1612                         emmc_pwren: emmc-pwren {
1613                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1614                         };
1615
1616                         emmc_rstnout: emmc-rstnout {
1617                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1618                         };
1619
1620                         emmc_bus1: emmc-bus1 {
1621                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1622                         };
1623
1624                         emmc_bus4: emmc-bus4 {
1625                                 rockchip,pins =
1626                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1627                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1628                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1629                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1630                         };
1631
1632                         emmc_bus8: emmc-bus8 {
1633                                 rockchip,pins =
1634                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1635                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1636                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1637                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1638                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1639                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1640                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1641                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1642                         };
1643                 };
1644
1645                 pwm0 {
1646                         pwm0_pin: pwm0-pin {
1647                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 pwm1 {
1652                         pwm1_pin: pwm1-pin {
1653                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1654                         };
1655                 };
1656
1657                 pwm2 {
1658                         pwm2_pin: pwm2-pin {
1659                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1660                         };
1661                 };
1662
1663                 pwmir {
1664                         pwmir_pin: pwmir-pin {
1665                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1666                         };
1667                 };
1668
1669                 gmac-1 {
1670                         rgmiim1_pins: rgmiim1-pins {
1671                                 rockchip,pins =
1672                                         /* mac_txclk */
1673                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1674                                         /* mac_rxclk */
1675                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1676                                         /* mac_mdio */
1677                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1678                                         /* mac_txen */
1679                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1680                                         /* mac_clk */
1681                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1682                                         /* mac_rxdv */
1683                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1684                                         /* mac_mdc */
1685                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1686                                         /* mac_rxd1 */
1687                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1688                                         /* mac_rxd0 */
1689                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1690                                         /* mac_txd1 */
1691                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1692                                         /* mac_txd0 */
1693                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1694                                         /* mac_rxd3 */
1695                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1696                                         /* mac_rxd2 */
1697                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1698                                         /* mac_txd3 */
1699                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1700                                         /* mac_txd2 */
1701                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1702
1703                                         /* mac_txclk */
1704                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1705                                         /* mac_txen */
1706                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1707                                         /* mac_clk */
1708                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1709                                         /* mac_txd1 */
1710                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1711                                         /* mac_txd0 */
1712                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1713                                         /* mac_txd3 */
1714                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1715                                         /* mac_txd2 */
1716                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1717                         };
1718
1719                         rmiim1_pins: rmiim1-pins {
1720                                 rockchip,pins =
1721                                         /* mac_mdio */
1722                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1723                                         /* mac_txen */
1724                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1725                                         /* mac_clk */
1726                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1727                                         /* mac_rxer */
1728                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1729                                         /* mac_rxdv */
1730                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1731                                         /* mac_mdc */
1732                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1733                                         /* mac_rxd1 */
1734                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1735                                         /* mac_rxd0 */
1736                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1737                                         /* mac_txd1 */
1738                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1739                                         /* mac_txd0 */
1740                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1741
1742                                         /* mac_mdio */
1743                                         <0 RK_PB3 1 &pcfg_pull_none>,
1744                                         /* mac_txen */
1745                                         <0 RK_PB4 1 &pcfg_pull_none>,
1746                                         /* mac_clk */
1747                                         <0 RK_PD0 1 &pcfg_pull_none>,
1748                                         /* mac_mdc */
1749                                         <0 RK_PC3 1 &pcfg_pull_none>,
1750                                         /* mac_txd1 */
1751                                         <0 RK_PC0 1 &pcfg_pull_none>,
1752                                         /* mac_txd0 */
1753                                         <0 RK_PC1 1 &pcfg_pull_none>;
1754                         };
1755                 };
1756
1757                 gmac2phy {
1758                         fephyled_speed100: fephyled-speed100 {
1759                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1760                         };
1761
1762                         fephyled_speed10: fephyled-speed10 {
1763                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1764                         };
1765
1766                         fephyled_duplex: fephyled-duplex {
1767                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1768                         };
1769
1770                         fephyled_rxm0: fephyled-rxm0 {
1771                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1772                         };
1773
1774                         fephyled_txm0: fephyled-txm0 {
1775                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1776                         };
1777
1778                         fephyled_linkm0: fephyled-linkm0 {
1779                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1780                         };
1781
1782                         fephyled_rxm1: fephyled-rxm1 {
1783                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1784                         };
1785
1786                         fephyled_txm1: fephyled-txm1 {
1787                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1788                         };
1789
1790                         fephyled_linkm1: fephyled-linkm1 {
1791                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1792                         };
1793                 };
1794
1795                 tsadc_pin {
1796                         tsadc_int: tsadc-int {
1797                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1798                         };
1799                         tsadc_gpio: tsadc-gpio {
1800                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1801                         };
1802                 };
1803
1804                 hdmi_pin {
1805                         hdmi_cec: hdmi-cec {
1806                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1807                         };
1808
1809                         hdmi_hpd: hdmi-hpd {
1810                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1811                         };
1812                 };
1813
1814                 cif-0 {
1815                         dvp_d2d9_m0:dvp-d2d9-m0 {
1816                                 rockchip,pins =
1817                                         /* cif_d0 */
1818                                         <3 RK_PA4 2 &pcfg_pull_none>,
1819                                         /* cif_d1 */
1820                                         <3 RK_PA5 2 &pcfg_pull_none>,
1821                                         /* cif_d2 */
1822                                         <3 RK_PA6 2 &pcfg_pull_none>,
1823                                         /* cif_d3 */
1824                                         <3 RK_PA7 2 &pcfg_pull_none>,
1825                                         /* cif_d4 */
1826                                         <3 RK_PB0 2 &pcfg_pull_none>,
1827                                         /* cif_d5m0 */
1828                                         <3 RK_PB1 2 &pcfg_pull_none>,
1829                                         /* cif_d6m0 */
1830                                         <3 RK_PB2 2 &pcfg_pull_none>,
1831                                         /* cif_d7m0 */
1832                                         <3 RK_PB3 2 &pcfg_pull_none>,
1833                                         /* cif_href */
1834                                         <3 RK_PA1 2 &pcfg_pull_none>,
1835                                         /* cif_vsync */
1836                                         <3 RK_PA0 2 &pcfg_pull_none>,
1837                                         /* cif_clkoutm0 */
1838                                         <3 RK_PA3 2 &pcfg_pull_none>,
1839                                         /* cif_clkin */
1840                                         <3 RK_PA2 2 &pcfg_pull_none>;
1841                         };
1842                 };
1843
1844                 cif-1 {
1845                         dvp_d2d9_m1:dvp-d2d9-m1 {
1846                                 rockchip,pins =
1847                                         /* cif_d0 */
1848                                         <3 RK_PA4 2 &pcfg_pull_none>,
1849                                         /* cif_d1 */
1850                                         <3 RK_PA5 2 &pcfg_pull_none>,
1851                                         /* cif_d2 */
1852                                         <3 RK_PA6 2 &pcfg_pull_none>,
1853                                         /* cif_d3 */
1854                                         <3 RK_PA7 2 &pcfg_pull_none>,
1855                                         /* cif_d4 */
1856                                         <3 RK_PB0 2 &pcfg_pull_none>,
1857                                         /* cif_d5m1 */
1858                                         <2 RK_PC0 4 &pcfg_pull_none>,
1859                                         /* cif_d6m1 */
1860                                         <2 RK_PC1 4 &pcfg_pull_none>,
1861                                         /* cif_d7m1 */
1862                                         <2 RK_PC2 4 &pcfg_pull_none>,
1863                                         /* cif_href */
1864                                         <3 RK_PA1 2 &pcfg_pull_none>,
1865                                         /* cif_vsync */
1866                                         <3 RK_PA0 2 &pcfg_pull_none>,
1867                                         /* cif_clkoutm1 */
1868                                         <2 RK_PB7 4 &pcfg_pull_none>,
1869                                         /* cif_clkin */
1870                                         <3 RK_PA2 2 &pcfg_pull_none>;
1871                         };
1872                 };
1873         };
1874 };