arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         cpu-idle-states = <&CPU_SLEEP>;
  45                         dynamic-power-coefficient = <120>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                         operating-points-v2 = <&cpu0_opp_table>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x0 0x1>;
  55                         clocks = <&cru ARMCLK>;
  56                         #cooling-cells = <2>;
  57                         cpu-idle-states = <&CPU_SLEEP>;
  58                         dynamic-power-coefficient = <120>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&l2>;
  61                         operating-points-v2 = <&cpu0_opp_table>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x0 0x2>;
  68                         clocks = <&cru ARMCLK>;
  69                         #cooling-cells = <2>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         dynamic-power-coefficient = <120>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&l2>;
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53";
  80                         reg = <0x0 0x3>;
  81                         clocks = <&cru ARMCLK>;
  82                         #cooling-cells = <2>;
  83                         cpu-idle-states = <&CPU_SLEEP>;
  84                         dynamic-power-coefficient = <120>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&l2>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101                 };
 102
 103                 l2: l2-cache0 {
 104                         compatible = "cache";
 105                 };
 106         };
 107
 108         cpu0_opp_table: opp-table-0 {
 109                 compatible = "operating-points-v2";
 110                 opp-shared;
 111
 112                 opp-408000000 {
 113                         opp-hz = /bits/ 64 <408000000>;
 114                         opp-microvolt = <950000>;
 115                         clock-latency-ns = <40000>;
 116                         opp-suspend;
 117                 };
 118                 opp-600000000 {
 119                         opp-hz = /bits/ 64 <600000000>;
 120                         opp-microvolt = <950000>;
 121                         clock-latency-ns = <40000>;
 122                 };
 123                 opp-816000000 {
 124                         opp-hz = /bits/ 64 <816000000>;
 125                         opp-microvolt = <1000000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp-1008000000 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1100000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp-1200000000 {
 134                         opp-hz = /bits/ 64 <1200000000>;
 135                         opp-microvolt = <1225000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138                 opp-1296000000 {
 139                         opp-hz = /bits/ 64 <1296000000>;
 140                         opp-microvolt = <1300000>;
 141                         clock-latency-ns = <40000>;
 142                 };
 143         };
 144
 145         analog_sound: analog-sound {
 146                 compatible = "simple-audio-card";
 147                 simple-audio-card,format = "i2s";
 148                 simple-audio-card,mclk-fs = <256>;
 149                 simple-audio-card,name = "Analog";
 150                 status = "disabled";
 151
 152                 simple-audio-card,cpu {
 153                         sound-dai = <&i2s1>;
 154                 };
 155
 156                 simple-audio-card,codec {
 157                         sound-dai = <&codec>;
 158                 };
 159         };
 160
 161         arm-pmu {
 162                 compatible = "arm,cortex-a53-pmu";
 163                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 167                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 168         };
 169
 170         display_subsystem: display-subsystem {
 171                 compatible = "rockchip,display-subsystem";
 172                 ports = <&vop_out>;
 173         };
 174
 175         hdmi_sound: hdmi-sound {
 176                 compatible = "simple-audio-card";
 177                 simple-audio-card,format = "i2s";
 178                 simple-audio-card,mclk-fs = <128>;
 179                 simple-audio-card,name = "HDMI";
 180                 status = "disabled";
 181
 182                 simple-audio-card,cpu {
 183                         sound-dai = <&i2s0>;
 184                 };
 185
 186                 simple-audio-card,codec {
 187                         sound-dai = <&hdmi>;
 188                 };
 189         };
 190
 191         psci {
 192                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 193                 method = "smc";
 194         };
 195
 196         timer {
 197                 compatible = "arm,armv8-timer";
 198                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 199                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 200                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 201                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 202         };
 203
 204         xin24m: xin24m {
 205                 compatible = "fixed-clock";
 206                 #clock-cells = <0>;
 207                 clock-frequency = <24000000>;
 208                 clock-output-names = "xin24m";
 209         };
 210
 211         i2s0: i2s@ff000000 {
 212                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 213                 reg = <0x0 0xff000000 0x0 0x1000>;
 214                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 216                 clock-names = "i2s_clk", "i2s_hclk";
 217                 dmas = <&dmac 11>, <&dmac 12>;
 218                 dma-names = "tx", "rx";
 219                 #sound-dai-cells = <0>;
 220                 status = "disabled";
 221         };
 222
 223         i2s1: i2s@ff010000 {
 224                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 225                 reg = <0x0 0xff010000 0x0 0x1000>;
 226                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 228                 clock-names = "i2s_clk", "i2s_hclk";
 229                 dmas = <&dmac 14>, <&dmac 15>;
 230                 dma-names = "tx", "rx";
 231                 #sound-dai-cells = <0>;
 232                 status = "disabled";
 233         };
 234
 235         i2s2: i2s@ff020000 {
 236                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 237                 reg = <0x0 0xff020000 0x0 0x1000>;
 238                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 240                 clock-names = "i2s_clk", "i2s_hclk";
 241                 dmas = <&dmac 0>, <&dmac 1>;
 242                 dma-names = "tx", "rx";
 243                 #sound-dai-cells = <0>;
 244                 status = "disabled";
 245         };
 246
 247         spdif: spdif@ff030000 {
 248                 compatible = "rockchip,rk3328-spdif";
 249                 reg = <0x0 0xff030000 0x0 0x1000>;
 250                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 252                 clock-names = "mclk", "hclk";
 253                 dmas = <&dmac 10>;
 254                 dma-names = "tx";
 255                 pinctrl-names = "default";
 256                 pinctrl-0 = <&spdifm2_tx>;
 257                 #sound-dai-cells = <0>;
 258                 status = "disabled";
 259         };
 260
 261         pdm: pdm@ff040000 {
 262                 compatible = "rockchip,pdm";
 263                 reg = <0x0 0xff040000 0x0 0x1000>;
 264                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 265                 clock-names = "pdm_clk", "pdm_hclk";
 266                 dmas = <&dmac 16>;
 267                 dma-names = "rx";
 268                 pinctrl-names = "default", "sleep";
 269                 pinctrl-0 = <&pdmm0_clk
 270                              &pdmm0_sdi0
 271                              &pdmm0_sdi1
 272                              &pdmm0_sdi2
 273                              &pdmm0_sdi3>;
 274                 pinctrl-1 = <&pdmm0_clk_sleep
 275                              &pdmm0_sdi0_sleep
 276                              &pdmm0_sdi1_sleep
 277                              &pdmm0_sdi2_sleep
 278                              &pdmm0_sdi3_sleep>;
 279                 status = "disabled";
 280         };
 281
 282         grf: syscon@ff100000 {
 283                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 284                 reg = <0x0 0xff100000 0x0 0x1000>;
 285
 286                 io_domains: io-domains {
 287                         compatible = "rockchip,rk3328-io-voltage-domain";
 288                         status = "disabled";
 289                 };
 290
 291                 grf_gpio: gpio {
 292                         compatible = "rockchip,rk3328-grf-gpio";
 293                         gpio-controller;
 294                         #gpio-cells = <2>;
 295                 };
 296
 297                 power: power-controller {
 298                         compatible = "rockchip,rk3328-power-controller";
 299                         #power-domain-cells = <1>;
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302
 303                         power-domain@RK3328_PD_HEVC {
 304                                 reg = <RK3328_PD_HEVC>;
 305                                 #power-domain-cells = <0>;
 306                         };
 307                         power-domain@RK3328_PD_VIDEO {
 308                                 reg = <RK3328_PD_VIDEO>;
 309                                 clocks = <&cru ACLK_RKVDEC>,
 310                                          <&cru HCLK_RKVDEC>,
 311                                          <&cru SCLK_VDEC_CABAC>,
 312                                          <&cru SCLK_VDEC_CORE>;
 313                                 #power-domain-cells = <0>;
 314                         };
 315                         power-domain@RK3328_PD_VPU {
 316                                 reg = <RK3328_PD_VPU>;
 317                                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 318                                 #power-domain-cells = <0>;
 319                         };
 320                 };
 321
 322                 reboot-mode {
 323                         compatible = "syscon-reboot-mode";
 324                         offset = <0x5c8>;
 325                         mode-normal = <BOOT_NORMAL>;
 326                         mode-recovery = <BOOT_RECOVERY>;
 327                         mode-bootloader = <BOOT_FASTBOOT>;
 328                         mode-loader = <BOOT_BL_DOWNLOAD>;
 329                 };
 330         };
 331
 332         uart0: serial@ff110000 {
 333                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 334                 reg = <0x0 0xff110000 0x0 0x100>;
 335                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 337                 clock-names = "baudclk", "apb_pclk";
 338                 dmas = <&dmac 2>, <&dmac 3>;
 339                 dma-names = "tx", "rx";
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 342                 reg-io-width = <4>;
 343                 reg-shift = <2>;
 344                 status = "disabled";
 345         };
 346
 347         uart1: serial@ff120000 {
 348                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 349                 reg = <0x0 0xff120000 0x0 0x100>;
 350                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 352                 clock-names = "baudclk", "apb_pclk";
 353                 dmas = <&dmac 4>, <&dmac 5>;
 354                 dma-names = "tx", "rx";
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 357                 reg-io-width = <4>;
 358                 reg-shift = <2>;
 359                 status = "disabled";
 360         };
 361
 362         uart2: serial@ff130000 {
 363                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 364                 reg = <0x0 0xff130000 0x0 0x100>;
 365                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 367                 clock-names = "baudclk", "apb_pclk";
 368                 dmas = <&dmac 6>, <&dmac 7>;
 369                 dma-names = "tx", "rx";
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&uart2m1_xfer>;
 372                 reg-io-width = <4>;
 373                 reg-shift = <2>;
 374                 status = "disabled";
 375         };
 376
 377         i2c0: i2c@ff150000 {
 378                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 379                 reg = <0x0 0xff150000 0x0 0x1000>;
 380                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 384                 clock-names = "i2c", "pclk";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&i2c0_xfer>;
 387                 status = "disabled";
 388         };
 389
 390         i2c1: i2c@ff160000 {
 391                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 392                 reg = <0x0 0xff160000 0x0 0x1000>;
 393                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 397                 clock-names = "i2c", "pclk";
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&i2c1_xfer>;
 400                 status = "disabled";
 401         };
 402
 403         i2c2: i2c@ff170000 {
 404                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 405                 reg = <0x0 0xff170000 0x0 0x1000>;
 406                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 410                 clock-names = "i2c", "pclk";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c2_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         i2c3: i2c@ff180000 {
 417                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 418                 reg = <0x0 0xff180000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 423                 clock-names = "i2c", "pclk";
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&i2c3_xfer>;
 426                 status = "disabled";
 427         };
 428
 429         spi0: spi@ff190000 {
 430                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 431                 reg = <0x0 0xff190000 0x0 0x1000>;
 432                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 436                 clock-names = "spiclk", "apb_pclk";
 437                 dmas = <&dmac 8>, <&dmac 9>;
 438                 dma-names = "tx", "rx";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 441                 status = "disabled";
 442         };
 443
 444         wdt: watchdog@ff1a0000 {
 445                 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
 446                 reg = <0x0 0xff1a0000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&cru PCLK_WDT>;
 449         };
 450
 451         pwm0: pwm@ff1b0000 {
 452                 compatible = "rockchip,rk3328-pwm";
 453                 reg = <0x0 0xff1b0000 0x0 0x10>;
 454                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 455                 clock-names = "pwm", "pclk";
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pwm0_pin>;
 458                 #pwm-cells = <3>;
 459                 status = "disabled";
 460         };
 461
 462         pwm1: pwm@ff1b0010 {
 463                 compatible = "rockchip,rk3328-pwm";
 464                 reg = <0x0 0xff1b0010 0x0 0x10>;
 465                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 466                 clock-names = "pwm", "pclk";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&pwm1_pin>;
 469                 #pwm-cells = <3>;
 470                 status = "disabled";
 471         };
 472
 473         pwm2: pwm@ff1b0020 {
 474                 compatible = "rockchip,rk3328-pwm";
 475                 reg = <0x0 0xff1b0020 0x0 0x10>;
 476                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 477                 clock-names = "pwm", "pclk";
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm2_pin>;
 480                 #pwm-cells = <3>;
 481                 status = "disabled";
 482         };
 483
 484         pwm3: pwm@ff1b0030 {
 485                 compatible = "rockchip,rk3328-pwm";
 486                 reg = <0x0 0xff1b0030 0x0 0x10>;
 487                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 489                 clock-names = "pwm", "pclk";
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&pwmir_pin>;
 492                 #pwm-cells = <3>;
 493                 status = "disabled";
 494         };
 495
 496         dmac: dma-controller@ff1f0000 {
 497                 compatible = "arm,pl330", "arm,primecell";
 498                 reg = <0x0 0xff1f0000 0x0 0x4000>;
 499                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 500                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 501                 arm,pl330-periph-burst;
 502                 clocks = <&cru ACLK_DMAC>;
 503                 clock-names = "apb_pclk";
 504                 #dma-cells = <1>;
 505         };
 506
 507         thermal-zones {
 508                 soc_thermal: soc-thermal {
 509                         polling-delay-passive = <20>;
 510                         polling-delay = <1000>;
 511                         sustainable-power = <1000>;
 512
 513                         thermal-sensors = <&tsadc 0>;
 514
 515                         trips {
 516                                 threshold: trip-point0 {
 517                                         temperature = <70000>;
 518                                         hysteresis = <2000>;
 519                                         type = "passive";
 520                                 };
 521                                 target: trip-point1 {
 522                                         temperature = <85000>;
 523                                         hysteresis = <2000>;
 524                                         type = "passive";
 525                                 };
 526                                 soc_crit: soc-crit {
 527                                         temperature = <95000>;
 528                                         hysteresis = <2000>;
 529                                         type = "critical";
 530                                 };
 531                         };
 532
 533                         cooling-maps {
 534                                 map0 {
 535                                         trip = <&target>;
 536                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 537                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 538                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 539                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 540                                         contribution = <4096>;
 541                                 };
 542                         };
 543                 };
 544
 545         };
 546
 547         tsadc: tsadc@ff250000 {
 548                 compatible = "rockchip,rk3328-tsadc";
 549                 reg = <0x0 0xff250000 0x0 0x100>;
 550                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 551                 assigned-clocks = <&cru SCLK_TSADC>;
 552                 assigned-clock-rates = <50000>;
 553                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 554                 clock-names = "tsadc", "apb_pclk";
 555                 pinctrl-names = "init", "default", "sleep";
 556                 pinctrl-0 = <&otp_pin>;
 557                 pinctrl-1 = <&otp_out>;
 558                 pinctrl-2 = <&otp_pin>;
 559                 resets = <&cru SRST_TSADC>;
 560                 reset-names = "tsadc-apb";
 561                 rockchip,grf = <&grf>;
 562                 rockchip,hw-tshut-temp = <100000>;
 563                 #thermal-sensor-cells = <1>;
 564                 status = "disabled";
 565         };
 566
 567         efuse: efuse@ff260000 {
 568                 compatible = "rockchip,rk3328-efuse";
 569                 reg = <0x0 0xff260000 0x0 0x50>;
 570                 #address-cells = <1>;
 571                 #size-cells = <1>;
 572                 clocks = <&cru SCLK_EFUSE>;
 573                 clock-names = "pclk_efuse";
 574                 rockchip,efuse-size = <0x20>;
 575
 576                 /* Data cells */
 577                 efuse_id: id@7 {
 578                         reg = <0x07 0x10>;
 579                 };
 580                 cpu_leakage: cpu-leakage@17 {
 581                         reg = <0x17 0x1>;
 582                 };
 583                 logic_leakage: logic-leakage@19 {
 584                         reg = <0x19 0x1>;
 585                 };
 586                 efuse_cpu_version: cpu-version@1a {
 587                         reg = <0x1a 0x1>;
 588                         bits = <3 3>;
 589                 };
 590         };
 591
 592         saradc: adc@ff280000 {
 593                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 594                 reg = <0x0 0xff280000 0x0 0x100>;
 595                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 596                 #io-channel-cells = <1>;
 597                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 598                 clock-names = "saradc", "apb_pclk";
 599                 resets = <&cru SRST_SARADC_P>;
 600                 reset-names = "saradc-apb";
 601                 status = "disabled";
 602         };
 603
 604         gpu: gpu@ff300000 {
 605                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 606                 reg = <0x0 0xff300000 0x0 0x30000>;
 607                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 608                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 609                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 610                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 611                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 612                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 613                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 614                 interrupt-names = "gp",
 615                                   "gpmmu",
 616                                   "pp",
 617                                   "pp0",
 618                                   "ppmmu0",
 619                                   "pp1",
 620                                   "ppmmu1";
 621                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 622                 clock-names = "bus", "core";
 623                 resets = <&cru SRST_GPU_A>;
 624         };
 625
 626         h265e_mmu: iommu@ff330200 {
 627                 compatible = "rockchip,iommu";
 628                 reg = <0x0 0xff330200 0 0x100>;
 629                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 631                 clock-names = "aclk", "iface";
 632                 #iommu-cells = <0>;
 633                 status = "disabled";
 634         };
 635
 636         vepu_mmu: iommu@ff340800 {
 637                 compatible = "rockchip,iommu";
 638                 reg = <0x0 0xff340800 0x0 0x40>;
 639                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 641                 clock-names = "aclk", "iface";
 642                 #iommu-cells = <0>;
 643                 status = "disabled";
 644         };
 645
 646         vpu: video-codec@ff350000 {
 647                 compatible = "rockchip,rk3328-vpu";
 648                 reg = <0x0 0xff350000 0x0 0x800>;
 649                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 650                 interrupt-names = "vdpu";
 651                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 652                 clock-names = "aclk", "hclk";
 653                 iommus = <&vpu_mmu>;
 654                 power-domains = <&power RK3328_PD_VPU>;
 655         };
 656
 657         vpu_mmu: iommu@ff350800 {
 658                 compatible = "rockchip,iommu";
 659                 reg = <0x0 0xff350800 0x0 0x40>;
 660                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 662                 clock-names = "aclk", "iface";
 663                 #iommu-cells = <0>;
 664                 power-domains = <&power RK3328_PD_VPU>;
 665         };
 666
 667         vdec: video-codec@ff360000 {
 668                 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
 669                 reg = <0x0 0xff360000 0x0 0x480>;
 670                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 671                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
 672                          <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
 673                 clock-names = "axi", "ahb", "cabac", "core";
 674                 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
 675                                   <&cru SCLK_VDEC_CORE>;
 676                 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
 677                 iommus = <&vdec_mmu>;
 678                 power-domains = <&power RK3328_PD_VIDEO>;
 679         };
 680
 681         vdec_mmu: iommu@ff360480 {
 682                 compatible = "rockchip,iommu";
 683                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 684                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 685                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 686                 clock-names = "aclk", "iface";
 687                 #iommu-cells = <0>;
 688                 power-domains = <&power RK3328_PD_VIDEO>;
 689         };
 690
 691         vop: vop@ff370000 {
 692                 compatible = "rockchip,rk3328-vop";
 693                 reg = <0x0 0xff370000 0x0 0x3efc>;
 694                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 696                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 697                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 698                 reset-names = "axi", "ahb", "dclk";
 699                 iommus = <&vop_mmu>;
 700                 status = "disabled";
 701
 702                 vop_out: port {
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705
 706                         vop_out_hdmi: endpoint@0 {
 707                                 reg = <0>;
 708                                 remote-endpoint = <&hdmi_in_vop>;
 709                         };
 710                 };
 711         };
 712
 713         vop_mmu: iommu@ff373f00 {
 714                 compatible = "rockchip,iommu";
 715                 reg = <0x0 0xff373f00 0x0 0x100>;
 716                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 718                 clock-names = "aclk", "iface";
 719                 #iommu-cells = <0>;
 720                 status = "disabled";
 721         };
 722
 723         hdmi: hdmi@ff3c0000 {
 724                 compatible = "rockchip,rk3328-dw-hdmi";
 725                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 726                 reg-io-width = <4>;
 727                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 728                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&cru PCLK_HDMI>,
 730                          <&cru SCLK_HDMI_SFC>,
 731                          <&cru SCLK_RTC32K>;
 732                 clock-names = "iahb",
 733                               "isfr",
 734                               "cec";
 735                 phys = <&hdmiphy>;
 736                 phy-names = "hdmi";
 737                 pinctrl-names = "default";
 738                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 739                 rockchip,grf = <&grf>;
 740                 #sound-dai-cells = <0>;
 741                 status = "disabled";
 742
 743                 ports {
 744                         #address-cells = <1>;
 745                         #size-cells = <0>;
 746
 747                         hdmi_in: port@0 {
 748                                 reg = <0>;
 749
 750                                 hdmi_in_vop: endpoint {
 751                                         remote-endpoint = <&vop_out_hdmi>;
 752                                 };
 753                         };
 754
 755                         hdmi_out: port@1 {
 756                                 reg = <1>;
 757                         };
 758                 };
 759         };
 760
 761         codec: codec@ff410000 {
 762                 compatible = "rockchip,rk3328-codec";
 763                 reg = <0x0 0xff410000 0x0 0x1000>;
 764                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 765                 clock-names = "pclk", "mclk";
 766                 rockchip,grf = <&grf>;
 767                 #sound-dai-cells = <0>;
 768                 status = "disabled";
 769         };
 770
 771         hdmiphy: phy@ff430000 {
 772                 compatible = "rockchip,rk3328-hdmi-phy";
 773                 reg = <0x0 0xff430000 0x0 0x10000>;
 774                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 775                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 776                 clock-names = "sysclk", "refoclk", "refpclk";
 777                 clock-output-names = "hdmi_phy";
 778                 #clock-cells = <0>;
 779                 nvmem-cells = <&efuse_cpu_version>;
 780                 nvmem-cell-names = "cpu-version";
 781                 #phy-cells = <0>;
 782                 status = "disabled";
 783         };
 784
 785         cru: clock-controller@ff440000 {
 786                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 787                 reg = <0x0 0xff440000 0x0 0x1000>;
 788                 rockchip,grf = <&grf>;
 789                 #clock-cells = <1>;
 790                 #reset-cells = <1>;
 791                 assigned-clocks =
 792                         /*
 793                          * CPLL should run at 1200, but that is to high for
 794                          * the initial dividers of most of its children.
 795                          * We need set cpll child clk div first,
 796                          * and then set the cpll frequency.
 797                          */
 798                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 799                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 800                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 801                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 802                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 803                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 804                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 805                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 806                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 807                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 808                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 809                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 810                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 811                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 812                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 813                         <&cru SCLK_RTC32K>;
 814                 assigned-clock-parents =
 815                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 816                         <&cru PLL_GPLL>, <&xin24m>,
 817                         <&xin24m>, <&xin24m>;
 818                 assigned-clock-rates =
 819                         <0>, <61440000>,
 820                         <0>, <24000000>,
 821                         <24000000>, <24000000>,
 822                         <15000000>, <15000000>,
 823                         <100000000>, <100000000>,
 824                         <100000000>, <100000000>,
 825                         <50000000>, <100000000>,
 826                         <100000000>, <100000000>,
 827                         <50000000>, <50000000>,
 828                         <50000000>, <50000000>,
 829                         <24000000>, <600000000>,
 830                         <491520000>, <1200000000>,
 831                         <150000000>, <75000000>,
 832                         <75000000>, <150000000>,
 833                         <75000000>, <75000000>,
 834                         <32768>;
 835         };
 836
 837         usb2phy_grf: syscon@ff450000 {
 838                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 839                              "simple-mfd";
 840                 reg = <0x0 0xff450000 0x0 0x10000>;
 841                 #address-cells = <1>;
 842                 #size-cells = <1>;
 843
 844                 u2phy: usb2phy@100 {
 845                         compatible = "rockchip,rk3328-usb2phy";
 846                         reg = <0x100 0x10>;
 847                         clocks = <&xin24m>;
 848                         clock-names = "phyclk";
 849                         clock-output-names = "usb480m_phy";
 850                         #clock-cells = <0>;
 851                         assigned-clocks = <&cru USB480M>;
 852                         assigned-clock-parents = <&u2phy>;
 853                         status = "disabled";
 854
 855                         u2phy_otg: otg-port {
 856                                 #phy-cells = <0>;
 857                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 858                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 859                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 860                                 interrupt-names = "otg-bvalid", "otg-id",
 861                                                   "linestate";
 862                                 status = "disabled";
 863                         };
 864
 865                         u2phy_host: host-port {
 866                                 #phy-cells = <0>;
 867                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 868                                 interrupt-names = "linestate";
 869                                 status = "disabled";
 870                         };
 871                 };
 872         };
 873
 874         sdmmc: mmc@ff500000 {
 875                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 876                 reg = <0x0 0xff500000 0x0 0x4000>;
 877                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 878                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 879                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 880                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 881                 fifo-depth = <0x100>;
 882                 max-frequency = <150000000>;
 883                 status = "disabled";
 884         };
 885
 886         sdio: mmc@ff510000 {
 887                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 888                 reg = <0x0 0xff510000 0x0 0x4000>;
 889                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 890                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 891                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 892                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 893                 fifo-depth = <0x100>;
 894                 max-frequency = <150000000>;
 895                 status = "disabled";
 896         };
 897
 898         emmc: mmc@ff520000 {
 899                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 900                 reg = <0x0 0xff520000 0x0 0x4000>;
 901                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 902                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 903                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 904                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 905                 fifo-depth = <0x100>;
 906                 max-frequency = <150000000>;
 907                 status = "disabled";
 908         };
 909
 910         gmac2io: ethernet@ff540000 {
 911                 compatible = "rockchip,rk3328-gmac";
 912                 reg = <0x0 0xff540000 0x0 0x10000>;
 913                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 914                 interrupt-names = "macirq";
 915                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 916                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 917                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 918                          <&cru PCLK_MAC2IO>;
 919                 clock-names = "stmmaceth", "mac_clk_rx",
 920                               "mac_clk_tx", "clk_mac_ref",
 921                               "clk_mac_refout", "aclk_mac",
 922                               "pclk_mac";
 923                 resets = <&cru SRST_GMAC2IO_A>;
 924                 reset-names = "stmmaceth";
 925                 rockchip,grf = <&grf>;
 926                 snps,txpbl = <0x4>;
 927                 status = "disabled";
 928         };
 929
 930         gmac2phy: ethernet@ff550000 {
 931                 compatible = "rockchip,rk3328-gmac";
 932                 reg = <0x0 0xff550000 0x0 0x10000>;
 933                 rockchip,grf = <&grf>;
 934                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 935                 interrupt-names = "macirq";
 936                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 937                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 938                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 939                          <&cru SCLK_MAC2PHY_OUT>;
 940                 clock-names = "stmmaceth", "mac_clk_rx",
 941                               "mac_clk_tx", "clk_mac_ref",
 942                               "aclk_mac", "pclk_mac",
 943                               "clk_macphy";
 944                 resets = <&cru SRST_GMAC2PHY_A>;
 945                 reset-names = "stmmaceth";
 946                 phy-mode = "rmii";
 947                 phy-handle = <&phy>;
 948                 snps,txpbl = <0x4>;
 949                 clock_in_out = "output";
 950                 status = "disabled";
 951
 952                 mdio {
 953                         compatible = "snps,dwmac-mdio";
 954                         #address-cells = <1>;
 955                         #size-cells = <0>;
 956
 957                         phy: ethernet-phy@0 {
 958                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 959                                 reg = <0>;
 960                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 961                                 resets = <&cru SRST_MACPHY>;
 962                                 pinctrl-names = "default";
 963                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 964                                 phy-is-integrated;
 965                         };
 966                 };
 967         };
 968
 969         usb20_otg: usb@ff580000 {
 970                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 971                              "snps,dwc2";
 972                 reg = <0x0 0xff580000 0x0 0x40000>;
 973                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 974                 clocks = <&cru HCLK_OTG>;
 975                 clock-names = "otg";
 976                 dr_mode = "otg";
 977                 g-np-tx-fifo-size = <16>;
 978                 g-rx-fifo-size = <280>;
 979                 g-tx-fifo-size = <256 128 128 64 32 16>;
 980                 phys = <&u2phy_otg>;
 981                 phy-names = "usb2-phy";
 982                 status = "disabled";
 983         };
 984
 985         usb_host0_ehci: usb@ff5c0000 {
 986                 compatible = "generic-ehci";
 987                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 988                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 989                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 990                 phys = <&u2phy_host>;
 991                 phy-names = "usb";
 992                 status = "disabled";
 993         };
 994
 995         usb_host0_ohci: usb@ff5d0000 {
 996                 compatible = "generic-ohci";
 997                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 998                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 999                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1000                 phys = <&u2phy_host>;
1001                 phy-names = "usb";
1002                 status = "disabled";
1003         };
1004
1005         usbdrd3: usb@ff600000 {
1006                 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1007                 reg = <0x0 0xff600000 0x0 0x100000>;
1008                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1009                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1010                          <&cru ACLK_USB3OTG>;
1011                 clock-names = "ref_clk", "suspend_clk",
1012                               "bus_clk";
1013                 dr_mode = "otg";
1014                 phy_type = "utmi_wide";
1015                 snps,dis-del-phy-power-chg-quirk;
1016                 snps,dis_enblslpm_quirk;
1017                 snps,dis-tx-ipgap-linecheck-quirk;
1018                 snps,dis-u2-freeclk-exists-quirk;
1019                 snps,dis_u2_susphy_quirk;
1020                 snps,dis_u3_susphy_quirk;
1021                 status = "disabled";
1022         };
1023
1024         gic: interrupt-controller@ff811000 {
1025                 compatible = "arm,gic-400";
1026                 #interrupt-cells = <3>;
1027                 #address-cells = <0>;
1028                 interrupt-controller;
1029                 reg = <0x0 0xff811000 0 0x1000>,
1030                       <0x0 0xff812000 0 0x2000>,
1031                       <0x0 0xff814000 0 0x2000>,
1032                       <0x0 0xff816000 0 0x2000>;
1033                 interrupts = <GIC_PPI 9
1034                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1035         };
1036
1037         pinctrl: pinctrl {
1038                 compatible = "rockchip,rk3328-pinctrl";
1039                 rockchip,grf = <&grf>;
1040                 #address-cells = <2>;
1041                 #size-cells = <2>;
1042                 ranges;
1043
1044                 gpio0: gpio@ff210000 {
1045                         compatible = "rockchip,gpio-bank";
1046                         reg = <0x0 0xff210000 0x0 0x100>;
1047                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1048                         clocks = <&cru PCLK_GPIO0>;
1049
1050                         gpio-controller;
1051                         #gpio-cells = <2>;
1052
1053                         interrupt-controller;
1054                         #interrupt-cells = <2>;
1055                 };
1056
1057                 gpio1: gpio@ff220000 {
1058                         compatible = "rockchip,gpio-bank";
1059                         reg = <0x0 0xff220000 0x0 0x100>;
1060                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1061                         clocks = <&cru PCLK_GPIO1>;
1062
1063                         gpio-controller;
1064                         #gpio-cells = <2>;
1065
1066                         interrupt-controller;
1067                         #interrupt-cells = <2>;
1068                 };
1069
1070                 gpio2: gpio@ff230000 {
1071                         compatible = "rockchip,gpio-bank";
1072                         reg = <0x0 0xff230000 0x0 0x100>;
1073                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1074                         clocks = <&cru PCLK_GPIO2>;
1075
1076                         gpio-controller;
1077                         #gpio-cells = <2>;
1078
1079                         interrupt-controller;
1080                         #interrupt-cells = <2>;
1081                 };
1082
1083                 gpio3: gpio@ff240000 {
1084                         compatible = "rockchip,gpio-bank";
1085                         reg = <0x0 0xff240000 0x0 0x100>;
1086                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1087                         clocks = <&cru PCLK_GPIO3>;
1088
1089                         gpio-controller;
1090                         #gpio-cells = <2>;
1091
1092                         interrupt-controller;
1093                         #interrupt-cells = <2>;
1094                 };
1095
1096                 pcfg_pull_up: pcfg-pull-up {
1097                         bias-pull-up;
1098                 };
1099
1100                 pcfg_pull_down: pcfg-pull-down {
1101                         bias-pull-down;
1102                 };
1103
1104                 pcfg_pull_none: pcfg-pull-none {
1105                         bias-disable;
1106                 };
1107
1108                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1109                         bias-disable;
1110                         drive-strength = <2>;
1111                 };
1112
1113                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1114                         bias-pull-up;
1115                         drive-strength = <2>;
1116                 };
1117
1118                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1119                         bias-pull-up;
1120                         drive-strength = <4>;
1121                 };
1122
1123                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1124                         bias-disable;
1125                         drive-strength = <4>;
1126                 };
1127
1128                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1129                         bias-pull-down;
1130                         drive-strength = <4>;
1131                 };
1132
1133                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1134                         bias-disable;
1135                         drive-strength = <8>;
1136                 };
1137
1138                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1139                         bias-pull-up;
1140                         drive-strength = <8>;
1141                 };
1142
1143                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1144                         bias-disable;
1145                         drive-strength = <12>;
1146                 };
1147
1148                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1149                         bias-pull-up;
1150                         drive-strength = <12>;
1151                 };
1152
1153                 pcfg_output_high: pcfg-output-high {
1154                         output-high;
1155                 };
1156
1157                 pcfg_output_low: pcfg-output-low {
1158                         output-low;
1159                 };
1160
1161                 pcfg_input_high: pcfg-input-high {
1162                         bias-pull-up;
1163                         input-enable;
1164                 };
1165
1166                 pcfg_input: pcfg-input {
1167                         input-enable;
1168                 };
1169
1170                 i2c0 {
1171                         i2c0_xfer: i2c0-xfer {
1172                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1173                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1174                         };
1175                 };
1176
1177                 i2c1 {
1178                         i2c1_xfer: i2c1-xfer {
1179                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1180                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1181                         };
1182                 };
1183
1184                 i2c2 {
1185                         i2c2_xfer: i2c2-xfer {
1186                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1187                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1188                         };
1189                 };
1190
1191                 i2c3 {
1192                         i2c3_xfer: i2c3-xfer {
1193                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1194                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1195                         };
1196                         i2c3_pins: i2c3-pins {
1197                                 rockchip,pins =
1198                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1199                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1200                         };
1201                 };
1202
1203                 hdmi_i2c {
1204                         hdmii2c_xfer: hdmii2c-xfer {
1205                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1206                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 pdm-0 {
1211                         pdmm0_clk: pdmm0-clk {
1212                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1213                         };
1214
1215                         pdmm0_fsync: pdmm0-fsync {
1216                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1217                         };
1218
1219                         pdmm0_sdi0: pdmm0-sdi0 {
1220                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1221                         };
1222
1223                         pdmm0_sdi1: pdmm0-sdi1 {
1224                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1225                         };
1226
1227                         pdmm0_sdi2: pdmm0-sdi2 {
1228                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1229                         };
1230
1231                         pdmm0_sdi3: pdmm0-sdi3 {
1232                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1233                         };
1234
1235                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1236                                 rockchip,pins =
1237                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1238                         };
1239
1240                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1241                                 rockchip,pins =
1242                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1243                         };
1244
1245                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1246                                 rockchip,pins =
1247                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1248                         };
1249
1250                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1251                                 rockchip,pins =
1252                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1253                         };
1254
1255                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1256                                 rockchip,pins =
1257                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1258                         };
1259
1260                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1261                                 rockchip,pins =
1262                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1263                         };
1264                 };
1265
1266                 tsadc {
1267                         otp_pin: otp-pin {
1268                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1269                         };
1270
1271                         otp_out: otp-out {
1272                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 uart0 {
1277                         uart0_xfer: uart0-xfer {
1278                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1279                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1280                         };
1281
1282                         uart0_cts: uart0-cts {
1283                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1284                         };
1285
1286                         uart0_rts: uart0-rts {
1287                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1288                         };
1289
1290                         uart0_rts_pin: uart0-rts-pin {
1291                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1292                         };
1293                 };
1294
1295                 uart1 {
1296                         uart1_xfer: uart1-xfer {
1297                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1298                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1299                         };
1300
1301                         uart1_cts: uart1-cts {
1302                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1303                         };
1304
1305                         uart1_rts: uart1-rts {
1306                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1307                         };
1308
1309                         uart1_rts_pin: uart1-rts-pin {
1310                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1311                         };
1312                 };
1313
1314                 uart2-0 {
1315                         uart2m0_xfer: uart2m0-xfer {
1316                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1317                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1318                         };
1319                 };
1320
1321                 uart2-1 {
1322                         uart2m1_xfer: uart2m1-xfer {
1323                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1324                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1325                         };
1326                 };
1327
1328                 spi0-0 {
1329                         spi0m0_clk: spi0m0-clk {
1330                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1331                         };
1332
1333                         spi0m0_cs0: spi0m0-cs0 {
1334                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1335                         };
1336
1337                         spi0m0_tx: spi0m0-tx {
1338                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1339                         };
1340
1341                         spi0m0_rx: spi0m0-rx {
1342                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1343                         };
1344
1345                         spi0m0_cs1: spi0m0-cs1 {
1346                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1347                         };
1348                 };
1349
1350                 spi0-1 {
1351                         spi0m1_clk: spi0m1-clk {
1352                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1353                         };
1354
1355                         spi0m1_cs0: spi0m1-cs0 {
1356                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1357                         };
1358
1359                         spi0m1_tx: spi0m1-tx {
1360                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1361                         };
1362
1363                         spi0m1_rx: spi0m1-rx {
1364                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1365                         };
1366
1367                         spi0m1_cs1: spi0m1-cs1 {
1368                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1369                         };
1370                 };
1371
1372                 spi0-2 {
1373                         spi0m2_clk: spi0m2-clk {
1374                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1375                         };
1376
1377                         spi0m2_cs0: spi0m2-cs0 {
1378                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1379                         };
1380
1381                         spi0m2_tx: spi0m2-tx {
1382                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1383                         };
1384
1385                         spi0m2_rx: spi0m2-rx {
1386                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1387                         };
1388                 };
1389
1390                 i2s1 {
1391                         i2s1_mclk: i2s1-mclk {
1392                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1393                         };
1394
1395                         i2s1_sclk: i2s1-sclk {
1396                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1397                         };
1398
1399                         i2s1_lrckrx: i2s1-lrckrx {
1400                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1401                         };
1402
1403                         i2s1_lrcktx: i2s1-lrcktx {
1404                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1405                         };
1406
1407                         i2s1_sdi: i2s1-sdi {
1408                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1409                         };
1410
1411                         i2s1_sdo: i2s1-sdo {
1412                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1413                         };
1414
1415                         i2s1_sdio1: i2s1-sdio1 {
1416                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1417                         };
1418
1419                         i2s1_sdio2: i2s1-sdio2 {
1420                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1421                         };
1422
1423                         i2s1_sdio3: i2s1-sdio3 {
1424                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1425                         };
1426
1427                         i2s1_sleep: i2s1-sleep {
1428                                 rockchip,pins =
1429                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1430                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1431                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1432                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1433                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1434                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1435                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1436                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1437                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1438                         };
1439                 };
1440
1441                 i2s2-0 {
1442                         i2s2m0_mclk: i2s2m0-mclk {
1443                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1444                         };
1445
1446                         i2s2m0_sclk: i2s2m0-sclk {
1447                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1448                         };
1449
1450                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1451                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1452                         };
1453
1454                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1455                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1456                         };
1457
1458                         i2s2m0_sdi: i2s2m0-sdi {
1459                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1460                         };
1461
1462                         i2s2m0_sdo: i2s2m0-sdo {
1463                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1464                         };
1465
1466                         i2s2m0_sleep: i2s2m0-sleep {
1467                                 rockchip,pins =
1468                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1469                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1470                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1471                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1472                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1473                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1474                         };
1475                 };
1476
1477                 i2s2-1 {
1478                         i2s2m1_mclk: i2s2m1-mclk {
1479                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1480                         };
1481
1482                         i2s2m1_sclk: i2s2m1-sclk {
1483                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1484                         };
1485
1486                         i2s2m1_lrckrx: i2sm1-lrckrx {
1487                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1488                         };
1489
1490                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1491                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1492                         };
1493
1494                         i2s2m1_sdi: i2s2m1-sdi {
1495                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1496                         };
1497
1498                         i2s2m1_sdo: i2s2m1-sdo {
1499                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1500                         };
1501
1502                         i2s2m1_sleep: i2s2m1-sleep {
1503                                 rockchip,pins =
1504                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1505                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1506                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1507                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1508                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1509                         };
1510                 };
1511
1512                 spdif-0 {
1513                         spdifm0_tx: spdifm0-tx {
1514                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1515                         };
1516                 };
1517
1518                 spdif-1 {
1519                         spdifm1_tx: spdifm1-tx {
1520                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1521                         };
1522                 };
1523
1524                 spdif-2 {
1525                         spdifm2_tx: spdifm2-tx {
1526                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1527                         };
1528                 };
1529
1530                 sdmmc0-0 {
1531                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1532                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1533                         };
1534
1535                         sdmmc0m0_pin: sdmmc0m0-pin {
1536                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1537                         };
1538                 };
1539
1540                 sdmmc0-1 {
1541                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1542                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1543                         };
1544
1545                         sdmmc0m1_pin: sdmmc0m1-pin {
1546                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1547                         };
1548                 };
1549
1550                 sdmmc0 {
1551                         sdmmc0_clk: sdmmc0-clk {
1552                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1553                         };
1554
1555                         sdmmc0_cmd: sdmmc0-cmd {
1556                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1557                         };
1558
1559                         sdmmc0_dectn: sdmmc0-dectn {
1560                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1561                         };
1562
1563                         sdmmc0_wrprt: sdmmc0-wrprt {
1564                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1565                         };
1566
1567                         sdmmc0_bus1: sdmmc0-bus1 {
1568                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1569                         };
1570
1571                         sdmmc0_bus4: sdmmc0-bus4 {
1572                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1573                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1574                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1575                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1576                         };
1577
1578                         sdmmc0_pins: sdmmc0-pins {
1579                                 rockchip,pins =
1580                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1581                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1582                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1583                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1584                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1588                         };
1589                 };
1590
1591                 sdmmc0ext {
1592                         sdmmc0ext_clk: sdmmc0ext-clk {
1593                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1594                         };
1595
1596                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1597                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1598                         };
1599
1600                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1601                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1602                         };
1603
1604                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1605                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1606                         };
1607
1608                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1609                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1610                         };
1611
1612                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1613                                 rockchip,pins =
1614                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1615                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1616                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1617                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1618                         };
1619
1620                         sdmmc0ext_pins: sdmmc0ext-pins {
1621                                 rockchip,pins =
1622                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1623                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1624                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1625                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1626                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1630                         };
1631                 };
1632
1633                 sdmmc1 {
1634                         sdmmc1_clk: sdmmc1-clk {
1635                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1636                         };
1637
1638                         sdmmc1_cmd: sdmmc1-cmd {
1639                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1640                         };
1641
1642                         sdmmc1_pwren: sdmmc1-pwren {
1643                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1644                         };
1645
1646                         sdmmc1_wrprt: sdmmc1-wrprt {
1647                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1648                         };
1649
1650                         sdmmc1_dectn: sdmmc1-dectn {
1651                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1652                         };
1653
1654                         sdmmc1_bus1: sdmmc1-bus1 {
1655                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1656                         };
1657
1658                         sdmmc1_bus4: sdmmc1-bus4 {
1659                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1660                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1661                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1662                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1663                         };
1664
1665                         sdmmc1_pins: sdmmc1-pins {
1666                                 rockchip,pins =
1667                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1668                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1669                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1670                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1671                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1672                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1673                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1674                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1675                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1676                         };
1677                 };
1678
1679                 emmc {
1680                         emmc_clk: emmc-clk {
1681                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1682                         };
1683
1684                         emmc_cmd: emmc-cmd {
1685                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1686                         };
1687
1688                         emmc_pwren: emmc-pwren {
1689                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1690                         };
1691
1692                         emmc_rstnout: emmc-rstnout {
1693                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1694                         };
1695
1696                         emmc_bus1: emmc-bus1 {
1697                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1698                         };
1699
1700                         emmc_bus4: emmc-bus4 {
1701                                 rockchip,pins =
1702                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1703                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1704                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1705                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1706                         };
1707
1708                         emmc_bus8: emmc-bus8 {
1709                                 rockchip,pins =
1710                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1711                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1712                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1713                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1714                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1715                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1716                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1717                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1718                         };
1719                 };
1720
1721                 pwm0 {
1722                         pwm0_pin: pwm0-pin {
1723                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1724                         };
1725                 };
1726
1727                 pwm1 {
1728                         pwm1_pin: pwm1-pin {
1729                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 pwm2 {
1734                         pwm2_pin: pwm2-pin {
1735                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1736                         };
1737                 };
1738
1739                 pwmir {
1740                         pwmir_pin: pwmir-pin {
1741                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1742                         };
1743                 };
1744
1745                 gmac-1 {
1746                         rgmiim1_pins: rgmiim1-pins {
1747                                 rockchip,pins =
1748                                         /* mac_txclk */
1749                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1750                                         /* mac_rxclk */
1751                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1752                                         /* mac_mdio */
1753                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1754                                         /* mac_txen */
1755                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1756                                         /* mac_clk */
1757                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1758                                         /* mac_rxdv */
1759                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1760                                         /* mac_mdc */
1761                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1762                                         /* mac_rxd1 */
1763                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1764                                         /* mac_rxd0 */
1765                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1766                                         /* mac_txd1 */
1767                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1768                                         /* mac_txd0 */
1769                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1770                                         /* mac_rxd3 */
1771                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1772                                         /* mac_rxd2 */
1773                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1774                                         /* mac_txd3 */
1775                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1776                                         /* mac_txd2 */
1777                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1778
1779                                         /* mac_txclk */
1780                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1781                                         /* mac_txen */
1782                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1783                                         /* mac_clk */
1784                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1785                                         /* mac_txd1 */
1786                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1787                                         /* mac_txd0 */
1788                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1789                                         /* mac_txd3 */
1790                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1791                                         /* mac_txd2 */
1792                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1793                         };
1794
1795                         rmiim1_pins: rmiim1-pins {
1796                                 rockchip,pins =
1797                                         /* mac_mdio */
1798                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1799                                         /* mac_txen */
1800                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1801                                         /* mac_clk */
1802                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1803                                         /* mac_rxer */
1804                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1805                                         /* mac_rxdv */
1806                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1807                                         /* mac_mdc */
1808                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1809                                         /* mac_rxd1 */
1810                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1811                                         /* mac_rxd0 */
1812                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1813                                         /* mac_txd1 */
1814                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1815                                         /* mac_txd0 */
1816                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1817
1818                                         /* mac_mdio */
1819                                         <0 RK_PB3 1 &pcfg_pull_none>,
1820                                         /* mac_txen */
1821                                         <0 RK_PB4 1 &pcfg_pull_none>,
1822                                         /* mac_clk */
1823                                         <0 RK_PD0 1 &pcfg_pull_none>,
1824                                         /* mac_mdc */
1825                                         <0 RK_PC3 1 &pcfg_pull_none>,
1826                                         /* mac_txd1 */
1827                                         <0 RK_PC0 1 &pcfg_pull_none>,
1828                                         /* mac_txd0 */
1829                                         <0 RK_PC1 1 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 gmac2phy {
1834                         fephyled_speed10: fephyled-speed10 {
1835                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1836                         };
1837
1838                         fephyled_duplex: fephyled-duplex {
1839                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1840                         };
1841
1842                         fephyled_rxm1: fephyled-rxm1 {
1843                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1844                         };
1845
1846                         fephyled_txm1: fephyled-txm1 {
1847                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1848                         };
1849
1850                         fephyled_linkm1: fephyled-linkm1 {
1851                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1852                         };
1853                 };
1854
1855                 tsadc_pin {
1856                         tsadc_int: tsadc-int {
1857                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1858                         };
1859                         tsadc_pin: tsadc-pin {
1860                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1861                         };
1862                 };
1863
1864                 hdmi_pin {
1865                         hdmi_cec: hdmi-cec {
1866                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1867                         };
1868
1869                         hdmi_hpd: hdmi-hpd {
1870                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1871                         };
1872                 };
1873
1874                 cif-0 {
1875                         dvp_d2d9_m0:dvp-d2d9-m0 {
1876                                 rockchip,pins =
1877                                         /* cif_d0 */
1878                                         <3 RK_PA4 2 &pcfg_pull_none>,
1879                                         /* cif_d1 */
1880                                         <3 RK_PA5 2 &pcfg_pull_none>,
1881                                         /* cif_d2 */
1882                                         <3 RK_PA6 2 &pcfg_pull_none>,
1883                                         /* cif_d3 */
1884                                         <3 RK_PA7 2 &pcfg_pull_none>,
1885                                         /* cif_d4 */
1886                                         <3 RK_PB0 2 &pcfg_pull_none>,
1887                                         /* cif_d5m0 */
1888                                         <3 RK_PB1 2 &pcfg_pull_none>,
1889                                         /* cif_d6m0 */
1890                                         <3 RK_PB2 2 &pcfg_pull_none>,
1891                                         /* cif_d7m0 */
1892                                         <3 RK_PB3 2 &pcfg_pull_none>,
1893                                         /* cif_href */
1894                                         <3 RK_PA1 2 &pcfg_pull_none>,
1895                                         /* cif_vsync */
1896                                         <3 RK_PA0 2 &pcfg_pull_none>,
1897                                         /* cif_clkoutm0 */
1898                                         <3 RK_PA3 2 &pcfg_pull_none>,
1899                                         /* cif_clkin */
1900                                         <3 RK_PA2 2 &pcfg_pull_none>;
1901                         };
1902                 };
1903
1904                 cif-1 {
1905                         dvp_d2d9_m1:dvp-d2d9-m1 {
1906                                 rockchip,pins =
1907                                         /* cif_d0 */
1908                                         <3 RK_PA4 2 &pcfg_pull_none>,
1909                                         /* cif_d1 */
1910                                         <3 RK_PA5 2 &pcfg_pull_none>,
1911                                         /* cif_d2 */
1912                                         <3 RK_PA6 2 &pcfg_pull_none>,
1913                                         /* cif_d3 */
1914                                         <3 RK_PA7 2 &pcfg_pull_none>,
1915                                         /* cif_d4 */
1916                                         <3 RK_PB0 2 &pcfg_pull_none>,
1917                                         /* cif_d5m1 */
1918                                         <2 RK_PC0 4 &pcfg_pull_none>,
1919                                         /* cif_d6m1 */
1920                                         <2 RK_PC1 4 &pcfg_pull_none>,
1921                                         /* cif_d7m1 */
1922                                         <2 RK_PC2 4 &pcfg_pull_none>,
1923                                         /* cif_href */
1924                                         <3 RK_PA1 2 &pcfg_pull_none>,
1925                                         /* cif_vsync */
1926                                         <3 RK_PA0 2 &pcfg_pull_none>,
1927                                         /* cif_clkoutm1 */
1928                                         <2 RK_PB7 4 &pcfg_pull_none>,
1929                                         /* cif_clkin */
1930                                         <3 RK_PA2 2 &pcfg_pull_none>;
1931                         };
1932                 };
1933         };
1934 };