arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         cpu-idle-states = <&CPU_SLEEP>;
  45                         dynamic-power-coefficient = <120>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                         operating-points-v2 = <&cpu0_opp_table>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x0 0x1>;
  55                         clocks = <&cru ARMCLK>;
  56                         #cooling-cells = <2>;
  57                         cpu-idle-states = <&CPU_SLEEP>;
  58                         dynamic-power-coefficient = <120>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&l2>;
  61                         operating-points-v2 = <&cpu0_opp_table>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x0 0x2>;
  68                         clocks = <&cru ARMCLK>;
  69                         #cooling-cells = <2>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         dynamic-power-coefficient = <120>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&l2>;
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53";
  80                         reg = <0x0 0x3>;
  81                         clocks = <&cru ARMCLK>;
  82                         #cooling-cells = <2>;
  83                         cpu-idle-states = <&CPU_SLEEP>;
  84                         dynamic-power-coefficient = <120>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&l2>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101                 };
 102
 103                 l2: l2-cache0 {
 104                         compatible = "cache";
 105                         cache-level = <2>;
 106                         cache-unified;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp-table-0 {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp-408000000 {
 115                         opp-hz = /bits/ 64 <408000000>;
 116                         opp-microvolt = <950000>;
 117                         clock-latency-ns = <40000>;
 118                         opp-suspend;
 119                 };
 120                 opp-600000000 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <950000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp-816000000 {
 126                         opp-hz = /bits/ 64 <816000000>;
 127                         opp-microvolt = <1000000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp-1008000000 {
 131                         opp-hz = /bits/ 64 <1008000000>;
 132                         opp-microvolt = <1100000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135                 opp-1200000000 {
 136                         opp-hz = /bits/ 64 <1200000000>;
 137                         opp-microvolt = <1225000>;
 138                         clock-latency-ns = <40000>;
 139                 };
 140                 opp-1296000000 {
 141                         opp-hz = /bits/ 64 <1296000000>;
 142                         opp-microvolt = <1300000>;
 143                         clock-latency-ns = <40000>;
 144                 };
 145         };
 146
 147         analog_sound: analog-sound {
 148                 compatible = "simple-audio-card";
 149                 simple-audio-card,format = "i2s";
 150                 simple-audio-card,mclk-fs = <256>;
 151                 simple-audio-card,name = "Analog";
 152                 status = "disabled";
 153
 154                 simple-audio-card,cpu {
 155                         sound-dai = <&i2s1>;
 156                 };
 157
 158                 simple-audio-card,codec {
 159                         sound-dai = <&codec>;
 160                 };
 161         };
 162
 163         arm-pmu {
 164                 compatible = "arm,cortex-a53-pmu";
 165                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 169                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 170         };
 171
 172         display_subsystem: display-subsystem {
 173                 compatible = "rockchip,display-subsystem";
 174                 ports = <&vop_out>;
 175         };
 176
 177         hdmi_sound: hdmi-sound {
 178                 compatible = "simple-audio-card";
 179                 simple-audio-card,format = "i2s";
 180                 simple-audio-card,mclk-fs = <128>;
 181                 simple-audio-card,name = "HDMI";
 182                 status = "disabled";
 183
 184                 simple-audio-card,cpu {
 185                         sound-dai = <&i2s0>;
 186                 };
 187
 188                 simple-audio-card,codec {
 189                         sound-dai = <&hdmi>;
 190                 };
 191         };
 192
 193         psci {
 194                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 195                 method = "smc";
 196         };
 197
 198         timer {
 199                 compatible = "arm,armv8-timer";
 200                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 201                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 202                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 203                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 204         };
 205
 206         xin24m: xin24m {
 207                 compatible = "fixed-clock";
 208                 #clock-cells = <0>;
 209                 clock-frequency = <24000000>;
 210                 clock-output-names = "xin24m";
 211         };
 212
 213         i2s0: i2s@ff000000 {
 214                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 215                 reg = <0x0 0xff000000 0x0 0x1000>;
 216                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 218                 clock-names = "i2s_clk", "i2s_hclk";
 219                 dmas = <&dmac 11>, <&dmac 12>;
 220                 dma-names = "tx", "rx";
 221                 #sound-dai-cells = <0>;
 222                 status = "disabled";
 223         };
 224
 225         i2s1: i2s@ff010000 {
 226                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 227                 reg = <0x0 0xff010000 0x0 0x1000>;
 228                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 230                 clock-names = "i2s_clk", "i2s_hclk";
 231                 dmas = <&dmac 14>, <&dmac 15>;
 232                 dma-names = "tx", "rx";
 233                 #sound-dai-cells = <0>;
 234                 status = "disabled";
 235         };
 236
 237         i2s2: i2s@ff020000 {
 238                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 239                 reg = <0x0 0xff020000 0x0 0x1000>;
 240                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 242                 clock-names = "i2s_clk", "i2s_hclk";
 243                 dmas = <&dmac 0>, <&dmac 1>;
 244                 dma-names = "tx", "rx";
 245                 #sound-dai-cells = <0>;
 246                 status = "disabled";
 247         };
 248
 249         spdif: spdif@ff030000 {
 250                 compatible = "rockchip,rk3328-spdif";
 251                 reg = <0x0 0xff030000 0x0 0x1000>;
 252                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 254                 clock-names = "mclk", "hclk";
 255                 dmas = <&dmac 10>;
 256                 dma-names = "tx";
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&spdifm2_tx>;
 259                 #sound-dai-cells = <0>;
 260                 status = "disabled";
 261         };
 262
 263         pdm: pdm@ff040000 {
 264                 compatible = "rockchip,pdm";
 265                 reg = <0x0 0xff040000 0x0 0x1000>;
 266                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 267                 clock-names = "pdm_clk", "pdm_hclk";
 268                 dmas = <&dmac 16>;
 269                 dma-names = "rx";
 270                 pinctrl-names = "default", "sleep";
 271                 pinctrl-0 = <&pdmm0_clk
 272                              &pdmm0_sdi0
 273                              &pdmm0_sdi1
 274                              &pdmm0_sdi2
 275                              &pdmm0_sdi3>;
 276                 pinctrl-1 = <&pdmm0_clk_sleep
 277                              &pdmm0_sdi0_sleep
 278                              &pdmm0_sdi1_sleep
 279                              &pdmm0_sdi2_sleep
 280                              &pdmm0_sdi3_sleep>;
 281                 status = "disabled";
 282         };
 283
 284         grf: syscon@ff100000 {
 285                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 286                 reg = <0x0 0xff100000 0x0 0x1000>;
 287
 288                 io_domains: io-domains {
 289                         compatible = "rockchip,rk3328-io-voltage-domain";
 290                         status = "disabled";
 291                 };
 292
 293                 grf_gpio: gpio {
 294                         compatible = "rockchip,rk3328-grf-gpio";
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                 };
 298
 299                 power: power-controller {
 300                         compatible = "rockchip,rk3328-power-controller";
 301                         #power-domain-cells = <1>;
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304
 305                         power-domain@RK3328_PD_HEVC {
 306                                 reg = <RK3328_PD_HEVC>;
 307                                 #power-domain-cells = <0>;
 308                         };
 309                         power-domain@RK3328_PD_VIDEO {
 310                                 reg = <RK3328_PD_VIDEO>;
 311                                 clocks = <&cru ACLK_RKVDEC>,
 312                                          <&cru HCLK_RKVDEC>,
 313                                          <&cru SCLK_VDEC_CABAC>,
 314                                          <&cru SCLK_VDEC_CORE>;
 315                                 #power-domain-cells = <0>;
 316                         };
 317                         power-domain@RK3328_PD_VPU {
 318                                 reg = <RK3328_PD_VPU>;
 319                                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 320                                 #power-domain-cells = <0>;
 321                         };
 322                 };
 323
 324                 reboot-mode {
 325                         compatible = "syscon-reboot-mode";
 326                         offset = <0x5c8>;
 327                         mode-normal = <BOOT_NORMAL>;
 328                         mode-recovery = <BOOT_RECOVERY>;
 329                         mode-bootloader = <BOOT_FASTBOOT>;
 330                         mode-loader = <BOOT_BL_DOWNLOAD>;
 331                 };
 332         };
 333
 334         uart0: serial@ff110000 {
 335                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 336                 reg = <0x0 0xff110000 0x0 0x100>;
 337                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 339                 clock-names = "baudclk", "apb_pclk";
 340                 dmas = <&dmac 2>, <&dmac 3>;
 341                 dma-names = "tx", "rx";
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 344                 reg-io-width = <4>;
 345                 reg-shift = <2>;
 346                 status = "disabled";
 347         };
 348
 349         uart1: serial@ff120000 {
 350                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 351                 reg = <0x0 0xff120000 0x0 0x100>;
 352                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 354                 clock-names = "baudclk", "apb_pclk";
 355                 dmas = <&dmac 4>, <&dmac 5>;
 356                 dma-names = "tx", "rx";
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 359                 reg-io-width = <4>;
 360                 reg-shift = <2>;
 361                 status = "disabled";
 362         };
 363
 364         uart2: serial@ff130000 {
 365                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 366                 reg = <0x0 0xff130000 0x0 0x100>;
 367                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 369                 clock-names = "baudclk", "apb_pclk";
 370                 dmas = <&dmac 6>, <&dmac 7>;
 371                 dma-names = "tx", "rx";
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&uart2m1_xfer>;
 374                 reg-io-width = <4>;
 375                 reg-shift = <2>;
 376                 status = "disabled";
 377         };
 378
 379         i2c0: i2c@ff150000 {
 380                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 381                 reg = <0x0 0xff150000 0x0 0x1000>;
 382                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 386                 clock-names = "i2c", "pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&i2c0_xfer>;
 389                 status = "disabled";
 390         };
 391
 392         i2c1: i2c@ff160000 {
 393                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 394                 reg = <0x0 0xff160000 0x0 0x1000>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 399                 clock-names = "i2c", "pclk";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&i2c1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         i2c2: i2c@ff170000 {
 406                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 407                 reg = <0x0 0xff170000 0x0 0x1000>;
 408                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 412                 clock-names = "i2c", "pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2c2_xfer>;
 415                 status = "disabled";
 416         };
 417
 418         i2c3: i2c@ff180000 {
 419                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 420                 reg = <0x0 0xff180000 0x0 0x1000>;
 421                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 425                 clock-names = "i2c", "pclk";
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&i2c3_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         spi0: spi@ff190000 {
 432                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 433                 reg = <0x0 0xff190000 0x0 0x1000>;
 434                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 438                 clock-names = "spiclk", "apb_pclk";
 439                 dmas = <&dmac 8>, <&dmac 9>;
 440                 dma-names = "tx", "rx";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 443                 status = "disabled";
 444         };
 445
 446         wdt: watchdog@ff1a0000 {
 447                 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
 448                 reg = <0x0 0xff1a0000 0x0 0x100>;
 449                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&cru PCLK_WDT>;
 451         };
 452
 453         pwm0: pwm@ff1b0000 {
 454                 compatible = "rockchip,rk3328-pwm";
 455                 reg = <0x0 0xff1b0000 0x0 0x10>;
 456                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 457                 clock-names = "pwm", "pclk";
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&pwm0_pin>;
 460                 #pwm-cells = <3>;
 461                 status = "disabled";
 462         };
 463
 464         pwm1: pwm@ff1b0010 {
 465                 compatible = "rockchip,rk3328-pwm";
 466                 reg = <0x0 0xff1b0010 0x0 0x10>;
 467                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 468                 clock-names = "pwm", "pclk";
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm1_pin>;
 471                 #pwm-cells = <3>;
 472                 status = "disabled";
 473         };
 474
 475         pwm2: pwm@ff1b0020 {
 476                 compatible = "rockchip,rk3328-pwm";
 477                 reg = <0x0 0xff1b0020 0x0 0x10>;
 478                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 479                 clock-names = "pwm", "pclk";
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&pwm2_pin>;
 482                 #pwm-cells = <3>;
 483                 status = "disabled";
 484         };
 485
 486         pwm3: pwm@ff1b0030 {
 487                 compatible = "rockchip,rk3328-pwm";
 488                 reg = <0x0 0xff1b0030 0x0 0x10>;
 489                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 491                 clock-names = "pwm", "pclk";
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&pwmir_pin>;
 494                 #pwm-cells = <3>;
 495                 status = "disabled";
 496         };
 497
 498         dmac: dma-controller@ff1f0000 {
 499                 compatible = "arm,pl330", "arm,primecell";
 500                 reg = <0x0 0xff1f0000 0x0 0x4000>;
 501                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 502                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 503                 arm,pl330-periph-burst;
 504                 clocks = <&cru ACLK_DMAC>;
 505                 clock-names = "apb_pclk";
 506                 #dma-cells = <1>;
 507         };
 508
 509         thermal-zones {
 510                 soc_thermal: soc-thermal {
 511                         polling-delay-passive = <20>;
 512                         polling-delay = <1000>;
 513                         sustainable-power = <1000>;
 514
 515                         thermal-sensors = <&tsadc 0>;
 516
 517                         trips {
 518                                 threshold: trip-point0 {
 519                                         temperature = <70000>;
 520                                         hysteresis = <2000>;
 521                                         type = "passive";
 522                                 };
 523                                 target: trip-point1 {
 524                                         temperature = <85000>;
 525                                         hysteresis = <2000>;
 526                                         type = "passive";
 527                                 };
 528                                 soc_crit: soc-crit {
 529                                         temperature = <95000>;
 530                                         hysteresis = <2000>;
 531                                         type = "critical";
 532                                 };
 533                         };
 534
 535                         cooling-maps {
 536                                 map0 {
 537                                         trip = <&target>;
 538                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 539                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 540                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 541                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 542                                         contribution = <4096>;
 543                                 };
 544                         };
 545                 };
 546
 547         };
 548
 549         tsadc: tsadc@ff250000 {
 550                 compatible = "rockchip,rk3328-tsadc";
 551                 reg = <0x0 0xff250000 0x0 0x100>;
 552                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 553                 assigned-clocks = <&cru SCLK_TSADC>;
 554                 assigned-clock-rates = <50000>;
 555                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 556                 clock-names = "tsadc", "apb_pclk";
 557                 pinctrl-names = "init", "default", "sleep";
 558                 pinctrl-0 = <&otp_pin>;
 559                 pinctrl-1 = <&otp_out>;
 560                 pinctrl-2 = <&otp_pin>;
 561                 resets = <&cru SRST_TSADC>;
 562                 reset-names = "tsadc-apb";
 563                 rockchip,grf = <&grf>;
 564                 rockchip,hw-tshut-temp = <100000>;
 565                 #thermal-sensor-cells = <1>;
 566                 status = "disabled";
 567         };
 568
 569         efuse: efuse@ff260000 {
 570                 compatible = "rockchip,rk3328-efuse";
 571                 reg = <0x0 0xff260000 0x0 0x50>;
 572                 #address-cells = <1>;
 573                 #size-cells = <1>;
 574                 clocks = <&cru SCLK_EFUSE>;
 575                 clock-names = "pclk_efuse";
 576                 rockchip,efuse-size = <0x20>;
 577
 578                 /* Data cells */
 579                 efuse_id: id@7 {
 580                         reg = <0x07 0x10>;
 581                 };
 582                 cpu_leakage: cpu-leakage@17 {
 583                         reg = <0x17 0x1>;
 584                 };
 585                 logic_leakage: logic-leakage@19 {
 586                         reg = <0x19 0x1>;
 587                 };
 588                 efuse_cpu_version: cpu-version@1a {
 589                         reg = <0x1a 0x1>;
 590                         bits = <3 3>;
 591                 };
 592         };
 593
 594         saradc: adc@ff280000 {
 595                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 596                 reg = <0x0 0xff280000 0x0 0x100>;
 597                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 598                 #io-channel-cells = <1>;
 599                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 600                 clock-names = "saradc", "apb_pclk";
 601                 resets = <&cru SRST_SARADC_P>;
 602                 reset-names = "saradc-apb";
 603                 status = "disabled";
 604         };
 605
 606         gpu: gpu@ff300000 {
 607                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 608                 reg = <0x0 0xff300000 0x0 0x30000>;
 609                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 610                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 611                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 612                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 613                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 614                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 615                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 616                 interrupt-names = "gp",
 617                                   "gpmmu",
 618                                   "pp",
 619                                   "pp0",
 620                                   "ppmmu0",
 621                                   "pp1",
 622                                   "ppmmu1";
 623                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 624                 clock-names = "bus", "core";
 625                 resets = <&cru SRST_GPU_A>;
 626         };
 627
 628         h265e_mmu: iommu@ff330200 {
 629                 compatible = "rockchip,iommu";
 630                 reg = <0x0 0xff330200 0 0x100>;
 631                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 633                 clock-names = "aclk", "iface";
 634                 #iommu-cells = <0>;
 635                 status = "disabled";
 636         };
 637
 638         vepu_mmu: iommu@ff340800 {
 639                 compatible = "rockchip,iommu";
 640                 reg = <0x0 0xff340800 0x0 0x40>;
 641                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 643                 clock-names = "aclk", "iface";
 644                 #iommu-cells = <0>;
 645                 status = "disabled";
 646         };
 647
 648         vpu: video-codec@ff350000 {
 649                 compatible = "rockchip,rk3328-vpu";
 650                 reg = <0x0 0xff350000 0x0 0x800>;
 651                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 652                 interrupt-names = "vdpu";
 653                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 654                 clock-names = "aclk", "hclk";
 655                 iommus = <&vpu_mmu>;
 656                 power-domains = <&power RK3328_PD_VPU>;
 657         };
 658
 659         vpu_mmu: iommu@ff350800 {
 660                 compatible = "rockchip,iommu";
 661                 reg = <0x0 0xff350800 0x0 0x40>;
 662                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 663                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 664                 clock-names = "aclk", "iface";
 665                 #iommu-cells = <0>;
 666                 power-domains = <&power RK3328_PD_VPU>;
 667         };
 668
 669         vdec: video-codec@ff360000 {
 670                 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
 671                 reg = <0x0 0xff360000 0x0 0x480>;
 672                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 673                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
 674                          <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
 675                 clock-names = "axi", "ahb", "cabac", "core";
 676                 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
 677                                   <&cru SCLK_VDEC_CORE>;
 678                 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
 679                 iommus = <&vdec_mmu>;
 680                 power-domains = <&power RK3328_PD_VIDEO>;
 681         };
 682
 683         vdec_mmu: iommu@ff360480 {
 684                 compatible = "rockchip,iommu";
 685                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 686                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 687                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 688                 clock-names = "aclk", "iface";
 689                 #iommu-cells = <0>;
 690                 power-domains = <&power RK3328_PD_VIDEO>;
 691         };
 692
 693         vop: vop@ff370000 {
 694                 compatible = "rockchip,rk3328-vop";
 695                 reg = <0x0 0xff370000 0x0 0x3efc>;
 696                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 697                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 698                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 699                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 700                 reset-names = "axi", "ahb", "dclk";
 701                 iommus = <&vop_mmu>;
 702                 status = "disabled";
 703
 704                 vop_out: port {
 705                         #address-cells = <1>;
 706                         #size-cells = <0>;
 707
 708                         vop_out_hdmi: endpoint@0 {
 709                                 reg = <0>;
 710                                 remote-endpoint = <&hdmi_in_vop>;
 711                         };
 712                 };
 713         };
 714
 715         vop_mmu: iommu@ff373f00 {
 716                 compatible = "rockchip,iommu";
 717                 reg = <0x0 0xff373f00 0x0 0x100>;
 718                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 720                 clock-names = "aclk", "iface";
 721                 #iommu-cells = <0>;
 722                 status = "disabled";
 723         };
 724
 725         hdmi: hdmi@ff3c0000 {
 726                 compatible = "rockchip,rk3328-dw-hdmi";
 727                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 728                 reg-io-width = <4>;
 729                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 730                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&cru PCLK_HDMI>,
 732                          <&cru SCLK_HDMI_SFC>,
 733                          <&cru SCLK_RTC32K>;
 734                 clock-names = "iahb",
 735                               "isfr",
 736                               "cec";
 737                 phys = <&hdmiphy>;
 738                 phy-names = "hdmi";
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 741                 rockchip,grf = <&grf>;
 742                 #sound-dai-cells = <0>;
 743                 status = "disabled";
 744
 745                 ports {
 746                         hdmi_in: port {
 747                                 hdmi_in_vop: endpoint {
 748                                         remote-endpoint = <&vop_out_hdmi>;
 749                                 };
 750                         };
 751                 };
 752         };
 753
 754         codec: codec@ff410000 {
 755                 compatible = "rockchip,rk3328-codec";
 756                 reg = <0x0 0xff410000 0x0 0x1000>;
 757                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 758                 clock-names = "pclk", "mclk";
 759                 rockchip,grf = <&grf>;
 760                 #sound-dai-cells = <0>;
 761                 status = "disabled";
 762         };
 763
 764         hdmiphy: phy@ff430000 {
 765                 compatible = "rockchip,rk3328-hdmi-phy";
 766                 reg = <0x0 0xff430000 0x0 0x10000>;
 767                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 768                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 769                 clock-names = "sysclk", "refoclk", "refpclk";
 770                 clock-output-names = "hdmi_phy";
 771                 #clock-cells = <0>;
 772                 nvmem-cells = <&efuse_cpu_version>;
 773                 nvmem-cell-names = "cpu-version";
 774                 #phy-cells = <0>;
 775                 status = "disabled";
 776         };
 777
 778         cru: clock-controller@ff440000 {
 779                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 780                 reg = <0x0 0xff440000 0x0 0x1000>;
 781                 rockchip,grf = <&grf>;
 782                 #clock-cells = <1>;
 783                 #reset-cells = <1>;
 784                 assigned-clocks =
 785                         /*
 786                          * CPLL should run at 1200, but that is to high for
 787                          * the initial dividers of most of its children.
 788                          * We need set cpll child clk div first,
 789                          * and then set the cpll frequency.
 790                          */
 791                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 792                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 793                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 794                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 795                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 796                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 797                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 798                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 799                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 800                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 801                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 802                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 803                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 804                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 805                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 806                         <&cru SCLK_RTC32K>;
 807                 assigned-clock-parents =
 808                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 809                         <&cru PLL_GPLL>, <&xin24m>,
 810                         <&xin24m>, <&xin24m>;
 811                 assigned-clock-rates =
 812                         <0>, <61440000>,
 813                         <0>, <24000000>,
 814                         <24000000>, <24000000>,
 815                         <15000000>, <15000000>,
 816                         <100000000>, <100000000>,
 817                         <100000000>, <100000000>,
 818                         <50000000>, <100000000>,
 819                         <100000000>, <100000000>,
 820                         <50000000>, <50000000>,
 821                         <50000000>, <50000000>,
 822                         <24000000>, <600000000>,
 823                         <491520000>, <1200000000>,
 824                         <150000000>, <75000000>,
 825                         <75000000>, <150000000>,
 826                         <75000000>, <75000000>,
 827                         <32768>;
 828         };
 829
 830         usb2phy_grf: syscon@ff450000 {
 831                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 832                              "simple-mfd";
 833                 reg = <0x0 0xff450000 0x0 0x10000>;
 834                 #address-cells = <1>;
 835                 #size-cells = <1>;
 836
 837                 u2phy: usb2phy@100 {
 838                         compatible = "rockchip,rk3328-usb2phy";
 839                         reg = <0x100 0x10>;
 840                         clocks = <&xin24m>;
 841                         clock-names = "phyclk";
 842                         clock-output-names = "usb480m_phy";
 843                         #clock-cells = <0>;
 844                         assigned-clocks = <&cru USB480M>;
 845                         assigned-clock-parents = <&u2phy>;
 846                         status = "disabled";
 847
 848                         u2phy_otg: otg-port {
 849                                 #phy-cells = <0>;
 850                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 851                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 852                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 853                                 interrupt-names = "otg-bvalid", "otg-id",
 854                                                   "linestate";
 855                                 status = "disabled";
 856                         };
 857
 858                         u2phy_host: host-port {
 859                                 #phy-cells = <0>;
 860                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 861                                 interrupt-names = "linestate";
 862                                 status = "disabled";
 863                         };
 864                 };
 865         };
 866
 867         sdmmc: mmc@ff500000 {
 868                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 869                 reg = <0x0 0xff500000 0x0 0x4000>;
 870                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 871                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 872                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 873                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 874                 fifo-depth = <0x100>;
 875                 max-frequency = <150000000>;
 876                 status = "disabled";
 877         };
 878
 879         sdio: mmc@ff510000 {
 880                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 881                 reg = <0x0 0xff510000 0x0 0x4000>;
 882                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 883                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 884                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 885                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 886                 fifo-depth = <0x100>;
 887                 max-frequency = <150000000>;
 888                 status = "disabled";
 889         };
 890
 891         emmc: mmc@ff520000 {
 892                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 893                 reg = <0x0 0xff520000 0x0 0x4000>;
 894                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 895                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 896                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 897                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 898                 fifo-depth = <0x100>;
 899                 max-frequency = <150000000>;
 900                 status = "disabled";
 901         };
 902
 903         gmac2io: ethernet@ff540000 {
 904                 compatible = "rockchip,rk3328-gmac";
 905                 reg = <0x0 0xff540000 0x0 0x10000>;
 906                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 907                 interrupt-names = "macirq";
 908                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 909                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 910                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 911                          <&cru PCLK_MAC2IO>;
 912                 clock-names = "stmmaceth", "mac_clk_rx",
 913                               "mac_clk_tx", "clk_mac_ref",
 914                               "clk_mac_refout", "aclk_mac",
 915                               "pclk_mac";
 916                 resets = <&cru SRST_GMAC2IO_A>;
 917                 reset-names = "stmmaceth";
 918                 rockchip,grf = <&grf>;
 919                 snps,txpbl = <0x4>;
 920                 status = "disabled";
 921         };
 922
 923         gmac2phy: ethernet@ff550000 {
 924                 compatible = "rockchip,rk3328-gmac";
 925                 reg = <0x0 0xff550000 0x0 0x10000>;
 926                 rockchip,grf = <&grf>;
 927                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 928                 interrupt-names = "macirq";
 929                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 930                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 931                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 932                          <&cru SCLK_MAC2PHY_OUT>;
 933                 clock-names = "stmmaceth", "mac_clk_rx",
 934                               "mac_clk_tx", "clk_mac_ref",
 935                               "aclk_mac", "pclk_mac",
 936                               "clk_macphy";
 937                 resets = <&cru SRST_GMAC2PHY_A>;
 938                 reset-names = "stmmaceth";
 939                 phy-mode = "rmii";
 940                 phy-handle = <&phy>;
 941                 snps,txpbl = <0x4>;
 942                 clock_in_out = "output";
 943                 status = "disabled";
 944
 945                 mdio {
 946                         compatible = "snps,dwmac-mdio";
 947                         #address-cells = <1>;
 948                         #size-cells = <0>;
 949
 950                         phy: ethernet-phy@0 {
 951                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 952                                 reg = <0>;
 953                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 954                                 resets = <&cru SRST_MACPHY>;
 955                                 pinctrl-names = "default";
 956                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 957                                 phy-is-integrated;
 958                         };
 959                 };
 960         };
 961
 962         usb20_otg: usb@ff580000 {
 963                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 964                              "snps,dwc2";
 965                 reg = <0x0 0xff580000 0x0 0x40000>;
 966                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 967                 clocks = <&cru HCLK_OTG>;
 968                 clock-names = "otg";
 969                 dr_mode = "otg";
 970                 g-np-tx-fifo-size = <16>;
 971                 g-rx-fifo-size = <280>;
 972                 g-tx-fifo-size = <256 128 128 64 32 16>;
 973                 phys = <&u2phy_otg>;
 974                 phy-names = "usb2-phy";
 975                 status = "disabled";
 976         };
 977
 978         usb_host0_ehci: usb@ff5c0000 {
 979                 compatible = "generic-ehci";
 980                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 981                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 982                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 983                 phys = <&u2phy_host>;
 984                 phy-names = "usb";
 985                 status = "disabled";
 986         };
 987
 988         usb_host0_ohci: usb@ff5d0000 {
 989                 compatible = "generic-ohci";
 990                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 991                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 992                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 993                 phys = <&u2phy_host>;
 994                 phy-names = "usb";
 995                 status = "disabled";
 996         };
 997
 998         usbdrd3: usb@ff600000 {
 999                 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1000                 reg = <0x0 0xff600000 0x0 0x100000>;
1001                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1002                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1003                          <&cru ACLK_USB3OTG>;
1004                 clock-names = "ref_clk", "suspend_clk",
1005                               "bus_clk";
1006                 dr_mode = "otg";
1007                 phy_type = "utmi_wide";
1008                 snps,dis-del-phy-power-chg-quirk;
1009                 snps,dis_enblslpm_quirk;
1010                 snps,dis-tx-ipgap-linecheck-quirk;
1011                 snps,dis-u2-freeclk-exists-quirk;
1012                 snps,dis_u2_susphy_quirk;
1013                 snps,dis_u3_susphy_quirk;
1014                 status = "disabled";
1015         };
1016
1017         gic: interrupt-controller@ff811000 {
1018                 compatible = "arm,gic-400";
1019                 #interrupt-cells = <3>;
1020                 #address-cells = <0>;
1021                 interrupt-controller;
1022                 reg = <0x0 0xff811000 0 0x1000>,
1023                       <0x0 0xff812000 0 0x2000>,
1024                       <0x0 0xff814000 0 0x2000>,
1025                       <0x0 0xff816000 0 0x2000>;
1026                 interrupts = <GIC_PPI 9
1027                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1028         };
1029
1030         crypto: crypto@ff060000 {
1031                 compatible = "rockchip,rk3328-crypto";
1032                 reg = <0x0 0xff060000 0x0 0x4000>;
1033                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1034                 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1035                          <&cru SCLK_CRYPTO>;
1036                 clock-names = "hclk_master", "hclk_slave", "sclk";
1037                 resets = <&cru SRST_CRYPTO>;
1038                 reset-names = "crypto-rst";
1039         };
1040
1041         pinctrl: pinctrl {
1042                 compatible = "rockchip,rk3328-pinctrl";
1043                 rockchip,grf = <&grf>;
1044                 #address-cells = <2>;
1045                 #size-cells = <2>;
1046                 ranges;
1047
1048                 gpio0: gpio@ff210000 {
1049                         compatible = "rockchip,gpio-bank";
1050                         reg = <0x0 0xff210000 0x0 0x100>;
1051                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1052                         clocks = <&cru PCLK_GPIO0>;
1053
1054                         gpio-controller;
1055                         #gpio-cells = <2>;
1056
1057                         interrupt-controller;
1058                         #interrupt-cells = <2>;
1059                 };
1060
1061                 gpio1: gpio@ff220000 {
1062                         compatible = "rockchip,gpio-bank";
1063                         reg = <0x0 0xff220000 0x0 0x100>;
1064                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1065                         clocks = <&cru PCLK_GPIO1>;
1066
1067                         gpio-controller;
1068                         #gpio-cells = <2>;
1069
1070                         interrupt-controller;
1071                         #interrupt-cells = <2>;
1072                 };
1073
1074                 gpio2: gpio@ff230000 {
1075                         compatible = "rockchip,gpio-bank";
1076                         reg = <0x0 0xff230000 0x0 0x100>;
1077                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1078                         clocks = <&cru PCLK_GPIO2>;
1079
1080                         gpio-controller;
1081                         #gpio-cells = <2>;
1082
1083                         interrupt-controller;
1084                         #interrupt-cells = <2>;
1085                 };
1086
1087                 gpio3: gpio@ff240000 {
1088                         compatible = "rockchip,gpio-bank";
1089                         reg = <0x0 0xff240000 0x0 0x100>;
1090                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1091                         clocks = <&cru PCLK_GPIO3>;
1092
1093                         gpio-controller;
1094                         #gpio-cells = <2>;
1095
1096                         interrupt-controller;
1097                         #interrupt-cells = <2>;
1098                 };
1099
1100                 pcfg_pull_up: pcfg-pull-up {
1101                         bias-pull-up;
1102                 };
1103
1104                 pcfg_pull_down: pcfg-pull-down {
1105                         bias-pull-down;
1106                 };
1107
1108                 pcfg_pull_none: pcfg-pull-none {
1109                         bias-disable;
1110                 };
1111
1112                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1113                         bias-disable;
1114                         drive-strength = <2>;
1115                 };
1116
1117                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1118                         bias-pull-up;
1119                         drive-strength = <2>;
1120                 };
1121
1122                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1123                         bias-pull-up;
1124                         drive-strength = <4>;
1125                 };
1126
1127                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1128                         bias-disable;
1129                         drive-strength = <4>;
1130                 };
1131
1132                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1133                         bias-pull-down;
1134                         drive-strength = <4>;
1135                 };
1136
1137                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1138                         bias-disable;
1139                         drive-strength = <8>;
1140                 };
1141
1142                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1143                         bias-pull-up;
1144                         drive-strength = <8>;
1145                 };
1146
1147                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1148                         bias-disable;
1149                         drive-strength = <12>;
1150                 };
1151
1152                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1153                         bias-pull-up;
1154                         drive-strength = <12>;
1155                 };
1156
1157                 pcfg_output_high: pcfg-output-high {
1158                         output-high;
1159                 };
1160
1161                 pcfg_output_low: pcfg-output-low {
1162                         output-low;
1163                 };
1164
1165                 pcfg_input_high: pcfg-input-high {
1166                         bias-pull-up;
1167                         input-enable;
1168                 };
1169
1170                 pcfg_input: pcfg-input {
1171                         input-enable;
1172                 };
1173
1174                 i2c0 {
1175                         i2c0_xfer: i2c0-xfer {
1176                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1177                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 i2c1 {
1182                         i2c1_xfer: i2c1-xfer {
1183                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1184                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 i2c2 {
1189                         i2c2_xfer: i2c2-xfer {
1190                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1191                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 i2c3 {
1196                         i2c3_xfer: i2c3-xfer {
1197                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1198                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1199                         };
1200                         i2c3_pins: i2c3-pins {
1201                                 rockchip,pins =
1202                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1203                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1204                         };
1205                 };
1206
1207                 hdmi_i2c {
1208                         hdmii2c_xfer: hdmii2c-xfer {
1209                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1210                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1211                         };
1212                 };
1213
1214                 pdm-0 {
1215                         pdmm0_clk: pdmm0-clk {
1216                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1217                         };
1218
1219                         pdmm0_fsync: pdmm0-fsync {
1220                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1221                         };
1222
1223                         pdmm0_sdi0: pdmm0-sdi0 {
1224                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1225                         };
1226
1227                         pdmm0_sdi1: pdmm0-sdi1 {
1228                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1229                         };
1230
1231                         pdmm0_sdi2: pdmm0-sdi2 {
1232                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1233                         };
1234
1235                         pdmm0_sdi3: pdmm0-sdi3 {
1236                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1237                         };
1238
1239                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1240                                 rockchip,pins =
1241                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1242                         };
1243
1244                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1245                                 rockchip,pins =
1246                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1247                         };
1248
1249                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1250                                 rockchip,pins =
1251                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1252                         };
1253
1254                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1255                                 rockchip,pins =
1256                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1257                         };
1258
1259                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1260                                 rockchip,pins =
1261                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1262                         };
1263
1264                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1265                                 rockchip,pins =
1266                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1267                         };
1268                 };
1269
1270                 tsadc {
1271                         otp_pin: otp-pin {
1272                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1273                         };
1274
1275                         otp_out: otp-out {
1276                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1277                         };
1278                 };
1279
1280                 uart0 {
1281                         uart0_xfer: uart0-xfer {
1282                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1283                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1284                         };
1285
1286                         uart0_cts: uart0-cts {
1287                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1288                         };
1289
1290                         uart0_rts: uart0-rts {
1291                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1292                         };
1293
1294                         uart0_rts_pin: uart0-rts-pin {
1295                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1296                         };
1297                 };
1298
1299                 uart1 {
1300                         uart1_xfer: uart1-xfer {
1301                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1302                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1303                         };
1304
1305                         uart1_cts: uart1-cts {
1306                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1307                         };
1308
1309                         uart1_rts: uart1-rts {
1310                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1311                         };
1312
1313                         uart1_rts_pin: uart1-rts-pin {
1314                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 uart2-0 {
1319                         uart2m0_xfer: uart2m0-xfer {
1320                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1321                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1322                         };
1323                 };
1324
1325                 uart2-1 {
1326                         uart2m1_xfer: uart2m1-xfer {
1327                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1328                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1329                         };
1330                 };
1331
1332                 spi0-0 {
1333                         spi0m0_clk: spi0m0-clk {
1334                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1335                         };
1336
1337                         spi0m0_cs0: spi0m0-cs0 {
1338                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1339                         };
1340
1341                         spi0m0_tx: spi0m0-tx {
1342                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1343                         };
1344
1345                         spi0m0_rx: spi0m0-rx {
1346                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1347                         };
1348
1349                         spi0m0_cs1: spi0m0-cs1 {
1350                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1351                         };
1352                 };
1353
1354                 spi0-1 {
1355                         spi0m1_clk: spi0m1-clk {
1356                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1357                         };
1358
1359                         spi0m1_cs0: spi0m1-cs0 {
1360                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1361                         };
1362
1363                         spi0m1_tx: spi0m1-tx {
1364                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1365                         };
1366
1367                         spi0m1_rx: spi0m1-rx {
1368                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1369                         };
1370
1371                         spi0m1_cs1: spi0m1-cs1 {
1372                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1373                         };
1374                 };
1375
1376                 spi0-2 {
1377                         spi0m2_clk: spi0m2-clk {
1378                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1379                         };
1380
1381                         spi0m2_cs0: spi0m2-cs0 {
1382                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1383                         };
1384
1385                         spi0m2_tx: spi0m2-tx {
1386                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1387                         };
1388
1389                         spi0m2_rx: spi0m2-rx {
1390                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1391                         };
1392                 };
1393
1394                 i2s1 {
1395                         i2s1_mclk: i2s1-mclk {
1396                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1397                         };
1398
1399                         i2s1_sclk: i2s1-sclk {
1400                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1401                         };
1402
1403                         i2s1_lrckrx: i2s1-lrckrx {
1404                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1405                         };
1406
1407                         i2s1_lrcktx: i2s1-lrcktx {
1408                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1409                         };
1410
1411                         i2s1_sdi: i2s1-sdi {
1412                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1413                         };
1414
1415                         i2s1_sdo: i2s1-sdo {
1416                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1417                         };
1418
1419                         i2s1_sdio1: i2s1-sdio1 {
1420                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1421                         };
1422
1423                         i2s1_sdio2: i2s1-sdio2 {
1424                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1425                         };
1426
1427                         i2s1_sdio3: i2s1-sdio3 {
1428                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1429                         };
1430
1431                         i2s1_sleep: i2s1-sleep {
1432                                 rockchip,pins =
1433                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1434                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1435                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1436                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1437                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1438                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1439                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1440                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1441                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1442                         };
1443                 };
1444
1445                 i2s2-0 {
1446                         i2s2m0_mclk: i2s2m0-mclk {
1447                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1448                         };
1449
1450                         i2s2m0_sclk: i2s2m0-sclk {
1451                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1452                         };
1453
1454                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1455                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1456                         };
1457
1458                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1459                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1460                         };
1461
1462                         i2s2m0_sdi: i2s2m0-sdi {
1463                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1464                         };
1465
1466                         i2s2m0_sdo: i2s2m0-sdo {
1467                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1468                         };
1469
1470                         i2s2m0_sleep: i2s2m0-sleep {
1471                                 rockchip,pins =
1472                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1473                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1474                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1475                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1476                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1477                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1478                         };
1479                 };
1480
1481                 i2s2-1 {
1482                         i2s2m1_mclk: i2s2m1-mclk {
1483                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1484                         };
1485
1486                         i2s2m1_sclk: i2s2m1-sclk {
1487                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1488                         };
1489
1490                         i2s2m1_lrckrx: i2sm1-lrckrx {
1491                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1492                         };
1493
1494                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1495                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1496                         };
1497
1498                         i2s2m1_sdi: i2s2m1-sdi {
1499                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1500                         };
1501
1502                         i2s2m1_sdo: i2s2m1-sdo {
1503                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1504                         };
1505
1506                         i2s2m1_sleep: i2s2m1-sleep {
1507                                 rockchip,pins =
1508                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1509                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1510                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1511                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1512                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1513                         };
1514                 };
1515
1516                 spdif-0 {
1517                         spdifm0_tx: spdifm0-tx {
1518                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1519                         };
1520                 };
1521
1522                 spdif-1 {
1523                         spdifm1_tx: spdifm1-tx {
1524                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1525                         };
1526                 };
1527
1528                 spdif-2 {
1529                         spdifm2_tx: spdifm2-tx {
1530                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1531                         };
1532                 };
1533
1534                 sdmmc0-0 {
1535                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1536                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1537                         };
1538
1539                         sdmmc0m0_pin: sdmmc0m0-pin {
1540                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1541                         };
1542                 };
1543
1544                 sdmmc0-1 {
1545                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1546                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1547                         };
1548
1549                         sdmmc0m1_pin: sdmmc0m1-pin {
1550                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1551                         };
1552                 };
1553
1554                 sdmmc0 {
1555                         sdmmc0_clk: sdmmc0-clk {
1556                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1557                         };
1558
1559                         sdmmc0_cmd: sdmmc0-cmd {
1560                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1561                         };
1562
1563                         sdmmc0_dectn: sdmmc0-dectn {
1564                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1565                         };
1566
1567                         sdmmc0_wrprt: sdmmc0-wrprt {
1568                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1569                         };
1570
1571                         sdmmc0_bus1: sdmmc0-bus1 {
1572                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1573                         };
1574
1575                         sdmmc0_bus4: sdmmc0-bus4 {
1576                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1577                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1578                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1579                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1580                         };
1581
1582                         sdmmc0_pins: sdmmc0-pins {
1583                                 rockchip,pins =
1584                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1588                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1589                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1590                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1591                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1592                         };
1593                 };
1594
1595                 sdmmc0ext {
1596                         sdmmc0ext_clk: sdmmc0ext-clk {
1597                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1598                         };
1599
1600                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1601                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1602                         };
1603
1604                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1605                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1606                         };
1607
1608                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1609                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1610                         };
1611
1612                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1613                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1614                         };
1615
1616                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1617                                 rockchip,pins =
1618                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1619                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1620                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1621                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1622                         };
1623
1624                         sdmmc0ext_pins: sdmmc0ext-pins {
1625                                 rockchip,pins =
1626                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1634                         };
1635                 };
1636
1637                 sdmmc1 {
1638                         sdmmc1_clk: sdmmc1-clk {
1639                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1640                         };
1641
1642                         sdmmc1_cmd: sdmmc1-cmd {
1643                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1644                         };
1645
1646                         sdmmc1_pwren: sdmmc1-pwren {
1647                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1648                         };
1649
1650                         sdmmc1_wrprt: sdmmc1-wrprt {
1651                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1652                         };
1653
1654                         sdmmc1_dectn: sdmmc1-dectn {
1655                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1656                         };
1657
1658                         sdmmc1_bus1: sdmmc1-bus1 {
1659                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1660                         };
1661
1662                         sdmmc1_bus4: sdmmc1-bus4 {
1663                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1664                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1665                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1666                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1667                         };
1668
1669                         sdmmc1_pins: sdmmc1-pins {
1670                                 rockchip,pins =
1671                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1672                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1673                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1674                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1675                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1676                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1677                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1678                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1679                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1680                         };
1681                 };
1682
1683                 emmc {
1684                         emmc_clk: emmc-clk {
1685                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1686                         };
1687
1688                         emmc_cmd: emmc-cmd {
1689                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1690                         };
1691
1692                         emmc_pwren: emmc-pwren {
1693                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1694                         };
1695
1696                         emmc_rstnout: emmc-rstnout {
1697                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1698                         };
1699
1700                         emmc_bus1: emmc-bus1 {
1701                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1702                         };
1703
1704                         emmc_bus4: emmc-bus4 {
1705                                 rockchip,pins =
1706                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1707                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1708                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1709                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1710                         };
1711
1712                         emmc_bus8: emmc-bus8 {
1713                                 rockchip,pins =
1714                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1715                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1716                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1717                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1718                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1719                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1720                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1721                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1722                         };
1723                 };
1724
1725                 pwm0 {
1726                         pwm0_pin: pwm0-pin {
1727                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1728                         };
1729                 };
1730
1731                 pwm1 {
1732                         pwm1_pin: pwm1-pin {
1733                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 pwm2 {
1738                         pwm2_pin: pwm2-pin {
1739                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1740                         };
1741                 };
1742
1743                 pwmir {
1744                         pwmir_pin: pwmir-pin {
1745                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1746                         };
1747                 };
1748
1749                 gmac-1 {
1750                         rgmiim1_pins: rgmiim1-pins {
1751                                 rockchip,pins =
1752                                         /* mac_txclk */
1753                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1754                                         /* mac_rxclk */
1755                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1756                                         /* mac_mdio */
1757                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1758                                         /* mac_txen */
1759                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1760                                         /* mac_clk */
1761                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1762                                         /* mac_rxdv */
1763                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1764                                         /* mac_mdc */
1765                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1766                                         /* mac_rxd1 */
1767                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1768                                         /* mac_rxd0 */
1769                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1770                                         /* mac_txd1 */
1771                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1772                                         /* mac_txd0 */
1773                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1774                                         /* mac_rxd3 */
1775                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1776                                         /* mac_rxd2 */
1777                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1778                                         /* mac_txd3 */
1779                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1780                                         /* mac_txd2 */
1781                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1782
1783                                         /* mac_txclk */
1784                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1785                                         /* mac_txen */
1786                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1787                                         /* mac_clk */
1788                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1789                                         /* mac_txd1 */
1790                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1791                                         /* mac_txd0 */
1792                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1793                                         /* mac_txd3 */
1794                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1795                                         /* mac_txd2 */
1796                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1797                         };
1798
1799                         rmiim1_pins: rmiim1-pins {
1800                                 rockchip,pins =
1801                                         /* mac_mdio */
1802                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1803                                         /* mac_txen */
1804                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1805                                         /* mac_clk */
1806                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1807                                         /* mac_rxer */
1808                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1809                                         /* mac_rxdv */
1810                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1811                                         /* mac_mdc */
1812                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1813                                         /* mac_rxd1 */
1814                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1815                                         /* mac_rxd0 */
1816                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1817                                         /* mac_txd1 */
1818                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1819                                         /* mac_txd0 */
1820                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1821
1822                                         /* mac_mdio */
1823                                         <0 RK_PB3 1 &pcfg_pull_none>,
1824                                         /* mac_txen */
1825                                         <0 RK_PB4 1 &pcfg_pull_none>,
1826                                         /* mac_clk */
1827                                         <0 RK_PD0 1 &pcfg_pull_none>,
1828                                         /* mac_mdc */
1829                                         <0 RK_PC3 1 &pcfg_pull_none>,
1830                                         /* mac_txd1 */
1831                                         <0 RK_PC0 1 &pcfg_pull_none>,
1832                                         /* mac_txd0 */
1833                                         <0 RK_PC1 1 &pcfg_pull_none>;
1834                         };
1835                 };
1836
1837                 gmac2phy {
1838                         fephyled_speed10: fephyled-speed10 {
1839                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1840                         };
1841
1842                         fephyled_duplex: fephyled-duplex {
1843                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1844                         };
1845
1846                         fephyled_rxm1: fephyled-rxm1 {
1847                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1848                         };
1849
1850                         fephyled_txm1: fephyled-txm1 {
1851                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1852                         };
1853
1854                         fephyled_linkm1: fephyled-linkm1 {
1855                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1856                         };
1857                 };
1858
1859                 tsadc_pin {
1860                         tsadc_int: tsadc-int {
1861                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1862                         };
1863                         tsadc_pin: tsadc-pin {
1864                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1865                         };
1866                 };
1867
1868                 hdmi_pin {
1869                         hdmi_cec: hdmi-cec {
1870                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1871                         };
1872
1873                         hdmi_hpd: hdmi-hpd {
1874                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1875                         };
1876                 };
1877
1878                 cif-0 {
1879                         dvp_d2d9_m0:dvp-d2d9-m0 {
1880                                 rockchip,pins =
1881                                         /* cif_d0 */
1882                                         <3 RK_PA4 2 &pcfg_pull_none>,
1883                                         /* cif_d1 */
1884                                         <3 RK_PA5 2 &pcfg_pull_none>,
1885                                         /* cif_d2 */
1886                                         <3 RK_PA6 2 &pcfg_pull_none>,
1887                                         /* cif_d3 */
1888                                         <3 RK_PA7 2 &pcfg_pull_none>,
1889                                         /* cif_d4 */
1890                                         <3 RK_PB0 2 &pcfg_pull_none>,
1891                                         /* cif_d5m0 */
1892                                         <3 RK_PB1 2 &pcfg_pull_none>,
1893                                         /* cif_d6m0 */
1894                                         <3 RK_PB2 2 &pcfg_pull_none>,
1895                                         /* cif_d7m0 */
1896                                         <3 RK_PB3 2 &pcfg_pull_none>,
1897                                         /* cif_href */
1898                                         <3 RK_PA1 2 &pcfg_pull_none>,
1899                                         /* cif_vsync */
1900                                         <3 RK_PA0 2 &pcfg_pull_none>,
1901                                         /* cif_clkoutm0 */
1902                                         <3 RK_PA3 2 &pcfg_pull_none>,
1903                                         /* cif_clkin */
1904                                         <3 RK_PA2 2 &pcfg_pull_none>;
1905                         };
1906                 };
1907
1908                 cif-1 {
1909                         dvp_d2d9_m1:dvp-d2d9-m1 {
1910                                 rockchip,pins =
1911                                         /* cif_d0 */
1912                                         <3 RK_PA4 2 &pcfg_pull_none>,
1913                                         /* cif_d1 */
1914                                         <3 RK_PA5 2 &pcfg_pull_none>,
1915                                         /* cif_d2 */
1916                                         <3 RK_PA6 2 &pcfg_pull_none>,
1917                                         /* cif_d3 */
1918                                         <3 RK_PA7 2 &pcfg_pull_none>,
1919                                         /* cif_d4 */
1920                                         <3 RK_PB0 2 &pcfg_pull_none>,
1921                                         /* cif_d5m1 */
1922                                         <2 RK_PC0 4 &pcfg_pull_none>,
1923                                         /* cif_d6m1 */
1924                                         <2 RK_PC1 4 &pcfg_pull_none>,
1925                                         /* cif_d7m1 */
1926                                         <2 RK_PC2 4 &pcfg_pull_none>,
1927                                         /* cif_href */
1928                                         <3 RK_PA1 2 &pcfg_pull_none>,
1929                                         /* cif_vsync */
1930                                         <3 RK_PA0 2 &pcfg_pull_none>,
1931                                         /* cif_clkoutm1 */
1932                                         <2 RK_PB7 4 &pcfg_pull_none>,
1933                                         /* cif_clkin */
1934                                         <3 RK_PA2 2 &pcfg_pull_none>;
1935                         };
1936                 };
1937         };
1938 };