arch/arm64/boot/dts/rockchip/rk3308.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  */
   6
   7 #include <dt-bindings/clock/rk3308-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3308";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 spi0 = &spi0;
  33                 spi1 = &spi1;
  34                 spi2 = &spi2;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a35";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         clocks = <&cru ARMCLK>;
  47                         #cooling-cells = <2>;
  48                         dynamic-power-coefficient = <90>;
  49                         operating-points-v2 = <&cpu0_opp_table>;
  50                         cpu-idle-states = <&CPU_SLEEP>;
  51                         next-level-cache = <&l2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP>;
  61                         next-level-cache = <&l2>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a35";
  67                         reg = <0x0 0x2>;
  68                         enable-method = "psci";
  69                         operating-points-v2 = <&cpu0_opp_table>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         next-level-cache = <&l2>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a35";
  77                         reg = <0x0 0x3>;
  78                         enable-method = "psci";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         cpu-idle-states = <&CPU_SLEEP>;
  81                         next-level-cache = <&l2>;
  82                 };
  83
  84                 idle-states {
  85                         entry-method = "psci";
  86
  87                         CPU_SLEEP: cpu-sleep {
  88                                 compatible = "arm,idle-state";
  89                                 local-timer-stop;
  90                                 arm,psci-suspend-param = <0x0010000>;
  91                                 entry-latency-us = <120>;
  92                                 exit-latency-us = <250>;
  93                                 min-residency-us = <900>;
  94                         };
  95                 };
  96
  97                 l2: l2-cache {
  98                         compatible = "cache";
  99                 };
 100         };
 101
 102         cpu0_opp_table: opp-table-0 {
 103                 compatible = "operating-points-v2";
 104                 opp-shared;
 105
 106                 opp-408000000 {
 107                         opp-hz = /bits/ 64 <408000000>;
 108                         opp-microvolt = <950000 950000 1340000>;
 109                         clock-latency-ns = <40000>;
 110                         opp-suspend;
 111                 };
 112                 opp-600000000 {
 113                         opp-hz = /bits/ 64 <600000000>;
 114                         opp-microvolt = <950000 950000 1340000>;
 115                         clock-latency-ns = <40000>;
 116                 };
 117                 opp-816000000 {
 118                         opp-hz = /bits/ 64 <816000000>;
 119                         opp-microvolt = <1025000 1025000 1340000>;
 120                         clock-latency-ns = <40000>;
 121                 };
 122                 opp-1008000000 {
 123                         opp-hz = /bits/ 64 <1008000000>;
 124                         opp-microvolt = <1125000 1125000 1340000>;
 125                         clock-latency-ns = <40000>;
 126                 };
 127         };
 128
 129         arm-pmu {
 130                 compatible = "arm,cortex-a35-pmu";
 131                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 135                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 136         };
 137
 138         mac_clkin: external-mac-clock {
 139                 compatible = "fixed-clock";
 140                 clock-frequency = <50000000>;
 141                 clock-output-names = "mac_clkin";
 142                 #clock-cells = <0>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 153                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 156         };
 157
 158         xin24m: xin24m {
 159                 compatible = "fixed-clock";
 160                 #clock-cells = <0>;
 161                 clock-frequency = <24000000>;
 162                 clock-output-names = "xin24m";
 163         };
 164
 165         grf: grf@ff000000 {
 166                 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
 167                 reg = <0x0 0xff000000 0x0 0x08000>;
 168
 169                 reboot-mode {
 170                         compatible = "syscon-reboot-mode";
 171                         offset = <0x500>;
 172                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 173                         mode-loader = <BOOT_BL_DOWNLOAD>;
 174                         mode-normal = <BOOT_NORMAL>;
 175                         mode-recovery = <BOOT_RECOVERY>;
 176                         mode-fastboot = <BOOT_FASTBOOT>;
 177                 };
 178         };
 179
 180         usb2phy_grf: syscon@ff008000 {
 181                 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
 182                 reg = <0x0 0xff008000 0x0 0x4000>;
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185
 186                 u2phy: usb2phy@100 {
 187                         compatible = "rockchip,rk3308-usb2phy";
 188                         reg = <0x100 0x10>;
 189                         assigned-clocks = <&cru USB480M>;
 190                         assigned-clock-parents = <&u2phy>;
 191                         clocks = <&cru SCLK_USBPHY_REF>;
 192                         clock-names = "phyclk";
 193                         clock-output-names = "usb480m_phy";
 194                         #clock-cells = <0>;
 195                         status = "disabled";
 196
 197                         u2phy_otg: otg-port {
 198                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 199                                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 200                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 201                                 interrupt-names = "otg-bvalid", "otg-id",
 202                                                   "linestate";
 203                                 #phy-cells = <0>;
 204                                 status = "disabled";
 205                         };
 206
 207                         u2phy_host: host-port {
 208                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 209                                 interrupt-names = "linestate";
 210                                 #phy-cells = <0>;
 211                                 status = "disabled";
 212                         };
 213                 };
 214         };
 215
 216         detect_grf: syscon@ff00b000 {
 217                 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
 218                 reg = <0x0 0xff00b000 0x0 0x1000>;
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221         };
 222
 223         core_grf: syscon@ff00c000 {
 224                 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
 225                 reg = <0x0 0xff00c000 0x0 0x1000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228         };
 229
 230         i2c0: i2c@ff040000 {
 231                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 232                 reg = <0x0 0xff040000 0x0 0x1000>;
 233                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 234                 clock-names = "i2c", "pclk";
 235                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&i2c0_xfer>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 status = "disabled";
 241         };
 242
 243         i2c1: i2c@ff050000 {
 244                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 245                 reg = <0x0 0xff050000 0x0 0x1000>;
 246                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 247                 clock-names = "i2c", "pclk";
 248                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&i2c1_xfer>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 status = "disabled";
 254         };
 255
 256         i2c2: i2c@ff060000 {
 257                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 258                 reg = <0x0 0xff060000 0x0 0x1000>;
 259                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 260                 clock-names = "i2c", "pclk";
 261                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&i2c2_xfer>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c3: i2c@ff070000 {
 270                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 271                 reg = <0x0 0xff070000 0x0 0x1000>;
 272                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 273                 clock-names = "i2c", "pclk";
 274                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&i2c3m0_xfer>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 status = "disabled";
 280         };
 281
 282         wdt: watchdog@ff080000 {
 283                 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
 284                 reg = <0x0 0xff080000 0x0 0x100>;
 285                 clocks = <&cru PCLK_WDT>;
 286                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 287                 status = "disabled";
 288         };
 289
 290         uart0: serial@ff0a0000 {
 291                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 292                 reg = <0x0 0xff0a0000 0x0 0x100>;
 293                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 295                 clock-names = "baudclk", "apb_pclk";
 296                 reg-shift = <2>;
 297                 reg-io-width = <4>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 300                 status = "disabled";
 301         };
 302
 303         uart1: serial@ff0b0000 {
 304                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 305                 reg = <0x0 0xff0b0000 0x0 0x100>;
 306                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 308                 clock-names = "baudclk", "apb_pclk";
 309                 reg-shift = <2>;
 310                 reg-io-width = <4>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 313                 status = "disabled";
 314         };
 315
 316         uart2: serial@ff0c0000 {
 317                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 318                 reg = <0x0 0xff0c0000 0x0 0x100>;
 319                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 321                 clock-names = "baudclk", "apb_pclk";
 322                 reg-shift = <2>;
 323                 reg-io-width = <4>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&uart2m0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart3: serial@ff0d0000 {
 330                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 331                 reg = <0x0 0xff0d0000 0x0 0x100>;
 332                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 334                 clock-names = "baudclk", "apb_pclk";
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&uart3_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         uart4: serial@ff0e0000 {
 343                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 344                 reg = <0x0 0xff0e0000 0x0 0x100>;
 345                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 347                 clock-names = "baudclk", "apb_pclk";
 348                 reg-shift = <2>;
 349                 reg-io-width = <4>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 352                 status = "disabled";
 353         };
 354
 355         spi0: spi@ff120000 {
 356                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 357                 reg = <0x0 0xff120000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 362                 clock-names = "spiclk", "apb_pclk";
 363                 dmas = <&dmac0 0>, <&dmac0 1>;
 364                 dma-names = "tx", "rx";
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
 367                 status = "disabled";
 368         };
 369
 370         spi1: spi@ff130000 {
 371                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 372                 reg = <0x0 0xff130000 0x0 0x1000>;
 373                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 377                 clock-names = "spiclk", "apb_pclk";
 378                 dmas = <&dmac0 2>, <&dmac0 3>;
 379                 dma-names = "tx", "rx";
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
 382                 status = "disabled";
 383         };
 384
 385         spi2: spi@ff140000 {
 386                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 387                 reg = <0x0 0xff140000 0x0 0x1000>;
 388                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 392                 clock-names = "spiclk", "apb_pclk";
 393                 dmas = <&dmac1 16>, <&dmac1 17>;
 394                 dma-names = "tx", "rx";
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
 397                 status = "disabled";
 398         };
 399
 400         pwm8: pwm@ff160000 {
 401                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 402                 reg = <0x0 0xff160000 0x0 0x10>;
 403                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 404                 clock-names = "pwm", "pclk";
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&pwm8_pin>;
 407                 #pwm-cells = <3>;
 408                 status = "disabled";
 409         };
 410
 411         pwm9: pwm@ff160010 {
 412                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 413                 reg = <0x0 0xff160010 0x0 0x10>;
 414                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 415                 clock-names = "pwm", "pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&pwm9_pin>;
 418                 #pwm-cells = <3>;
 419                 status = "disabled";
 420         };
 421
 422         pwm10: pwm@ff160020 {
 423                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 424                 reg = <0x0 0xff160020 0x0 0x10>;
 425                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 426                 clock-names = "pwm", "pclk";
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&pwm10_pin>;
 429                 #pwm-cells = <3>;
 430                 status = "disabled";
 431         };
 432
 433         pwm11: pwm@ff160030 {
 434                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 435                 reg = <0x0 0xff160030 0x0 0x10>;
 436                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 437                 clock-names = "pwm", "pclk";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&pwm11_pin>;
 440                 #pwm-cells = <3>;
 441                 status = "disabled";
 442         };
 443
 444         pwm4: pwm@ff170000 {
 445                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 446                 reg = <0x0 0xff170000 0x0 0x10>;
 447                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 448                 clock-names = "pwm", "pclk";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&pwm4_pin>;
 451                 #pwm-cells = <3>;
 452                 status = "disabled";
 453         };
 454
 455         pwm5: pwm@ff170010 {
 456                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 457                 reg = <0x0 0xff170010 0x0 0x10>;
 458                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 459                 clock-names = "pwm", "pclk";
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&pwm5_pin>;
 462                 #pwm-cells = <3>;
 463                 status = "disabled";
 464         };
 465
 466         pwm6: pwm@ff170020 {
 467                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 468                 reg = <0x0 0xff170020 0x0 0x10>;
 469                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 470                 clock-names = "pwm", "pclk";
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&pwm6_pin>;
 473                 #pwm-cells = <3>;
 474                 status = "disabled";
 475         };
 476
 477         pwm7: pwm@ff170030 {
 478                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 479                 reg = <0x0 0xff170030 0x0 0x10>;
 480                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 481                 clock-names = "pwm", "pclk";
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&pwm7_pin>;
 484                 #pwm-cells = <3>;
 485                 status = "disabled";
 486         };
 487
 488         pwm0: pwm@ff180000 {
 489                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 490                 reg = <0x0 0xff180000 0x0 0x10>;
 491                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 492                 clock-names = "pwm", "pclk";
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&pwm0_pin>;
 495                 #pwm-cells = <3>;
 496                 status = "disabled";
 497         };
 498
 499         pwm1: pwm@ff180010 {
 500                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 501                 reg = <0x0 0xff180010 0x0 0x10>;
 502                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 503                 clock-names = "pwm", "pclk";
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&pwm1_pin>;
 506                 #pwm-cells = <3>;
 507                 status = "disabled";
 508         };
 509
 510         pwm2: pwm@ff180020 {
 511                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 512                 reg = <0x0 0xff180020 0x0 0x10>;
 513                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 514                 clock-names = "pwm", "pclk";
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&pwm2_pin>;
 517                 #pwm-cells = <3>;
 518                 status = "disabled";
 519         };
 520
 521         pwm3: pwm@ff180030 {
 522                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 523                 reg = <0x0 0xff180030 0x0 0x10>;
 524                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 525                 clock-names = "pwm", "pclk";
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&pwm3_pin>;
 528                 #pwm-cells = <3>;
 529                 status = "disabled";
 530         };
 531
 532         rktimer: rktimer@ff1a0000 {
 533                 compatible = "rockchip,rk3288-timer";
 534                 reg = <0x0 0xff1a0000 0x0 0x20>;
 535                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 537                 clock-names = "pclk", "timer";
 538         };
 539
 540         saradc: saradc@ff1e0000 {
 541                 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
 542                 reg = <0x0 0xff1e0000 0x0 0x100>;
 543                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 544                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 545                 clock-names = "saradc", "apb_pclk";
 546                 #io-channel-cells = <1>;
 547                 resets = <&cru SRST_SARADC_P>;
 548                 reset-names = "saradc-apb";
 549                 status = "disabled";
 550         };
 551
 552         dmac0: dma-controller@ff2c0000 {
 553                 compatible = "arm,pl330", "arm,primecell";
 554                 reg = <0x0 0xff2c0000 0x0 0x4000>;
 555                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 556                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 557                 arm,pl330-periph-burst;
 558                 clocks = <&cru ACLK_DMAC0>;
 559                 clock-names = "apb_pclk";
 560                 #dma-cells = <1>;
 561         };
 562
 563         dmac1: dma-controller@ff2d0000 {
 564                 compatible = "arm,pl330", "arm,primecell";
 565                 reg = <0x0 0xff2d0000 0x0 0x4000>;
 566                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 567                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 568                 arm,pl330-periph-burst;
 569                 clocks = <&cru ACLK_DMAC1>;
 570                 clock-names = "apb_pclk";
 571                 #dma-cells = <1>;
 572         };
 573
 574         i2s_2ch_0: i2s@ff350000 {
 575                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 576                 reg = <0x0 0xff350000 0x0 0x1000>;
 577                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
 579                 clock-names = "i2s_clk", "i2s_hclk";
 580                 dmas = <&dmac1 8>, <&dmac1 9>;
 581                 dma-names = "tx", "rx";
 582                 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
 583                 reset-names = "reset-m", "reset-h";
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&i2s_2ch_0_sclk
 586                              &i2s_2ch_0_lrck
 587                              &i2s_2ch_0_sdi
 588                              &i2s_2ch_0_sdo>;
 589                 status = "disabled";
 590         };
 591
 592         i2s_2ch_1: i2s@ff360000 {
 593                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 594                 reg = <0x0 0xff360000 0x0 0x1000>;
 595                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
 597                 clock-names = "i2s_clk", "i2s_hclk";
 598                 dmas = <&dmac1 11>;
 599                 dma-names = "rx";
 600                 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
 601                 reset-names = "reset-m", "reset-h";
 602                 status = "disabled";
 603         };
 604
 605         spdif_tx: spdif-tx@ff3a0000 {
 606                 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
 607                 reg = <0x0 0xff3a0000 0x0 0x1000>;
 608                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
 610                 clock-names = "mclk", "hclk";
 611                 dmas = <&dmac1 13>;
 612                 dma-names = "tx";
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&spdif_out>;
 615                 status = "disabled";
 616         };
 617
 618         usb20_otg: usb@ff400000 {
 619                 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
 620                              "snps,dwc2";
 621                 reg = <0x0 0xff400000 0x0 0x40000>;
 622                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&cru HCLK_OTG>;
 624                 clock-names = "otg";
 625                 dr_mode = "otg";
 626                 g-np-tx-fifo-size = <16>;
 627                 g-rx-fifo-size = <280>;
 628                 g-tx-fifo-size = <256 128 128 64 32 16>;
 629                 phys = <&u2phy_otg>;
 630                 phy-names = "usb2-phy";
 631                 status = "disabled";
 632         };
 633
 634         usb_host_ehci: usb@ff440000 {
 635                 compatible = "generic-ehci";
 636                 reg = <0x0 0xff440000 0x0 0x10000>;
 637                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 639                 phys = <&u2phy_host>;
 640                 phy-names = "usb";
 641                 status = "disabled";
 642         };
 643
 644         usb_host_ohci: usb@ff450000 {
 645                 compatible = "generic-ohci";
 646                 reg = <0x0 0xff450000 0x0 0x10000>;
 647                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 649                 phys = <&u2phy_host>;
 650                 phy-names = "usb";
 651                 status = "disabled";
 652         };
 653
 654         sdmmc: mmc@ff480000 {
 655                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 656                 reg = <0x0 0xff480000 0x0 0x4000>;
 657                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 658                 bus-width = <4>;
 659                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 660                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 661                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 662                 fifo-depth = <0x100>;
 663                 max-frequency = <150000000>;
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 666                 status = "disabled";
 667         };
 668
 669         emmc: mmc@ff490000 {
 670                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 671                 reg = <0x0 0xff490000 0x0 0x4000>;
 672                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 673                 bus-width = <8>;
 674                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 675                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 676                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 677                 fifo-depth = <0x100>;
 678                 max-frequency = <150000000>;
 679                 status = "disabled";
 680         };
 681
 682         sdio: mmc@ff4a0000 {
 683                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 684                 reg = <0x0 0xff4a0000 0x0 0x4000>;
 685                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 686                 bus-width = <4>;
 687                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 688                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 689                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 690                 fifo-depth = <0x100>;
 691                 max-frequency = <150000000>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 694                 status = "disabled";
 695         };
 696
 697         nfc: nand-controller@ff4b0000 {
 698                 compatible = "rockchip,rk3308-nfc",
 699                              "rockchip,rv1108-nfc";
 700                 reg = <0x0 0xff4b0000 0x0 0x4000>;
 701                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 702                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 703                 clock-names = "ahb", "nfc";
 704                 assigned-clocks = <&cru SCLK_NANDC>;
 705                 assigned-clock-rates = <150000000>;
 706                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 707                              &flash_rdn &flash_rdy &flash_wrn>;
 708                 pinctrl-names = "default";
 709                 status = "disabled";
 710         };
 711
 712         gmac: ethernet@ff4e0000 {
 713                 compatible = "rockchip,rk3308-gmac";
 714                 reg = <0x0 0xff4e0000 0x0 0x10000>;
 715                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 716                 interrupt-names = "macirq";
 717                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
 718                          <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
 719                          <&cru SCLK_MAC>, <&cru ACLK_MAC>,
 720                          <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
 721                 clock-names = "stmmaceth", "mac_clk_rx",
 722                               "mac_clk_tx", "clk_mac_ref",
 723                               "clk_mac_refout", "aclk_mac",
 724                               "pclk_mac", "clk_mac_speed";
 725                 phy-mode = "rmii";
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 728                 resets = <&cru SRST_MAC_A>;
 729                 reset-names = "stmmaceth";
 730                 rockchip,grf = <&grf>;
 731                 status = "disabled";
 732         };
 733
 734         sfc: spi@ff4c0000 {
 735                 compatible = "rockchip,sfc";
 736                 reg = <0x0 0xff4c0000 0x0 0x4000>;
 737                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 738                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 739                 clock-names = "clk_sfc", "hclk_sfc";
 740                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 741                 pinctrl-names = "default";
 742                 status = "disabled";
 743         };
 744
 745         cru: clock-controller@ff500000 {
 746                 compatible = "rockchip,rk3308-cru";
 747                 reg = <0x0 0xff500000 0x0 0x1000>;
 748                 clocks = <&xin24m>;
 749                 clock-names = "xin24m";
 750                 rockchip,grf = <&grf>;
 751                 #clock-cells = <1>;
 752                 #reset-cells = <1>;
 753                 assigned-clocks = <&cru SCLK_RTC32K>;
 754                 assigned-clock-rates = <32768>;
 755         };
 756
 757         gic: interrupt-controller@ff580000 {
 758                 compatible = "arm,gic-400";
 759                 reg = <0x0 0xff581000 0x0 0x1000>,
 760                       <0x0 0xff582000 0x0 0x2000>,
 761                       <0x0 0xff584000 0x0 0x2000>,
 762                       <0x0 0xff586000 0x0 0x2000>;
 763                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 764                 #interrupt-cells = <3>;
 765                 interrupt-controller;
 766                 #address-cells = <0>;
 767         };
 768
 769         sram: sram@fff80000 {
 770                 compatible = "mmio-sram";
 771                 reg = <0x0 0xfff80000 0x0 0x40000>;
 772                 ranges = <0 0x0 0xfff80000 0x40000>;
 773                 #address-cells = <1>;
 774                 #size-cells = <1>;
 775
 776                 /* reserved for ddr dvfs and system suspend/resume */
 777                 ddr-sram@0 {
 778                         reg = <0x0 0x8000>;
 779                 };
 780
 781                 /* reserved for vad audio buffer */
 782                 vad_sram: vad-sram@8000 {
 783                         reg = <0x8000 0x38000>;
 784                 };
 785         };
 786
 787         pinctrl: pinctrl {
 788                 compatible = "rockchip,rk3308-pinctrl";
 789                 rockchip,grf = <&grf>;
 790                 #address-cells = <2>;
 791                 #size-cells = <2>;
 792                 ranges;
 793
 794                 gpio0: gpio@ff220000 {
 795                         compatible = "rockchip,gpio-bank";
 796                         reg = <0x0 0xff220000 0x0 0x100>;
 797                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 798                         clocks = <&cru PCLK_GPIO0>;
 799                         gpio-controller;
 800                         #gpio-cells = <2>;
 801                         interrupt-controller;
 802                         #interrupt-cells = <2>;
 803                 };
 804
 805                 gpio1: gpio@ff230000 {
 806                         compatible = "rockchip,gpio-bank";
 807                         reg = <0x0 0xff230000 0x0 0x100>;
 808                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&cru PCLK_GPIO1>;
 810                         gpio-controller;
 811                         #gpio-cells = <2>;
 812                         interrupt-controller;
 813                         #interrupt-cells = <2>;
 814                 };
 815
 816                 gpio2: gpio@ff240000 {
 817                         compatible = "rockchip,gpio-bank";
 818                         reg = <0x0 0xff240000 0x0 0x100>;
 819                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 820                         clocks = <&cru PCLK_GPIO2>;
 821                         gpio-controller;
 822                         #gpio-cells = <2>;
 823                         interrupt-controller;
 824                         #interrupt-cells = <2>;
 825                 };
 826
 827                 gpio3: gpio@ff250000 {
 828                         compatible = "rockchip,gpio-bank";
 829                         reg = <0x0 0xff250000 0x0 0x100>;
 830                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&cru PCLK_GPIO3>;
 832                         gpio-controller;
 833                         #gpio-cells = <2>;
 834                         interrupt-controller;
 835                         #interrupt-cells = <2>;
 836                 };
 837
 838                 gpio4: gpio@ff260000 {
 839                         compatible = "rockchip,gpio-bank";
 840                         reg = <0x0 0xff260000 0x0 0x100>;
 841                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 842                         clocks = <&cru PCLK_GPIO4>;
 843                         gpio-controller;
 844                         #gpio-cells = <2>;
 845                         interrupt-controller;
 846                         #interrupt-cells = <2>;
 847                 };
 848
 849                 pcfg_pull_up: pcfg-pull-up {
 850                         bias-pull-up;
 851                 };
 852
 853                 pcfg_pull_down: pcfg-pull-down {
 854                         bias-pull-down;
 855                 };
 856
 857                 pcfg_pull_none: pcfg-pull-none {
 858                         bias-disable;
 859                 };
 860
 861                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 862                         bias-disable;
 863                         drive-strength = <2>;
 864                 };
 865
 866                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 867                         bias-pull-up;
 868                         drive-strength = <2>;
 869                 };
 870
 871                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 872                         bias-pull-up;
 873                         drive-strength = <4>;
 874                 };
 875
 876                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 877                         bias-disable;
 878                         drive-strength = <4>;
 879                 };
 880
 881                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 882                         bias-pull-down;
 883                         drive-strength = <4>;
 884                 };
 885
 886                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 887                         bias-disable;
 888                         drive-strength = <8>;
 889                 };
 890
 891                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 892                         bias-pull-up;
 893                         drive-strength = <8>;
 894                 };
 895
 896                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 897                         bias-disable;
 898                         drive-strength = <12>;
 899                 };
 900
 901                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 902                         bias-pull-up;
 903                         drive-strength = <12>;
 904                 };
 905
 906                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 907                         bias-disable;
 908                         input-schmitt-enable;
 909                 };
 910
 911                 pcfg_output_high: pcfg-output-high {
 912                         output-high;
 913                 };
 914
 915                 pcfg_output_low: pcfg-output-low {
 916                         output-low;
 917                 };
 918
 919                 pcfg_input_high: pcfg-input-high {
 920                         bias-pull-up;
 921                         input-enable;
 922                 };
 923
 924                 pcfg_input: pcfg-input {
 925                         input-enable;
 926                 };
 927
 928                 emmc {
 929                         emmc_clk: emmc-clk {
 930                                 rockchip,pins =
 931                                         <3 RK_PB1 2 &pcfg_pull_none_8ma>;
 932                         };
 933
 934                         emmc_cmd: emmc-cmd {
 935                                 rockchip,pins =
 936                                         <3 RK_PB0 2 &pcfg_pull_up_8ma>;
 937                         };
 938
 939                         emmc_pwren: emmc-pwren {
 940                                 rockchip,pins =
 941                                         <3 RK_PB3 2 &pcfg_pull_none>;
 942                         };
 943
 944                         emmc_rstn: emmc-rstn {
 945                                 rockchip,pins =
 946                                         <3 RK_PB2 2 &pcfg_pull_none>;
 947                         };
 948
 949                         emmc_bus1: emmc-bus1 {
 950                                 rockchip,pins =
 951                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>;
 952                         };
 953
 954                         emmc_bus4: emmc-bus4 {
 955                                 rockchip,pins =
 956                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 957                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 958                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 959                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>;
 960                         };
 961
 962                         emmc_bus8: emmc-bus8 {
 963                                 rockchip,pins =
 964                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 965                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 966                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 967                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>,
 968                                         <3 RK_PA4 2 &pcfg_pull_up_8ma>,
 969                                         <3 RK_PA5 2 &pcfg_pull_up_8ma>,
 970                                         <3 RK_PA6 2 &pcfg_pull_up_8ma>,
 971                                         <3 RK_PA7 2 &pcfg_pull_up_8ma>;
 972                         };
 973                 };
 974
 975                 flash {
 976                         flash_csn0: flash-csn0 {
 977                                 rockchip,pins =
 978                                         <3 RK_PB5 1 &pcfg_pull_none>;
 979                         };
 980
 981                         flash_rdy: flash-rdy {
 982                                 rockchip,pins =
 983                                         <3 RK_PB4 1 &pcfg_pull_none>;
 984                         };
 985
 986                         flash_ale: flash-ale {
 987                                 rockchip,pins =
 988                                         <3 RK_PB3 1 &pcfg_pull_none>;
 989                         };
 990
 991                         flash_cle: flash-cle {
 992                                 rockchip,pins =
 993                                         <3 RK_PB1 1 &pcfg_pull_none>;
 994                         };
 995
 996                         flash_wrn: flash-wrn {
 997                                 rockchip,pins =
 998                                         <3 RK_PB0 1 &pcfg_pull_none>;
 999                         };
1000
1001                         flash_rdn: flash-rdn {
1002                                 rockchip,pins =
1003                                         <3 RK_PB2 1 &pcfg_pull_none>;
1004                         };
1005
1006                         flash_bus8: flash-bus8 {
1007                                 rockchip,pins =
1008                                         <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1009                                         <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1010                                         <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1011                                         <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1012                                         <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1013                                         <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1014                                         <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1015                                         <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1016                         };
1017                 };
1018
1019                 sfc {
1020                         sfc_bus4: sfc-bus4 {
1021                                 rockchip,pins =
1022                                         <3 RK_PA0 3 &pcfg_pull_none>,
1023                                         <3 RK_PA1 3 &pcfg_pull_none>,
1024                                         <3 RK_PA2 3 &pcfg_pull_none>,
1025                                         <3 RK_PA3 3 &pcfg_pull_none>;
1026                         };
1027
1028                         sfc_bus2: sfc-bus2 {
1029                                 rockchip,pins =
1030                                         <3 RK_PA0 3 &pcfg_pull_none>,
1031                                         <3 RK_PA1 3 &pcfg_pull_none>;
1032                         };
1033
1034                         sfc_cs0: sfc-cs0 {
1035                                 rockchip,pins =
1036                                         <3 RK_PA4 3 &pcfg_pull_none>;
1037                         };
1038
1039                         sfc_clk: sfc-clk {
1040                                 rockchip,pins =
1041                                         <3 RK_PA5 3 &pcfg_pull_none>;
1042                         };
1043                 };
1044
1045                 gmac {
1046                         rmii_pins: rmii-pins {
1047                                 rockchip,pins =
1048                                         /* mac_txen */
1049                                         <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1050                                         /* mac_txd1 */
1051                                         <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1052                                         /* mac_txd0 */
1053                                         <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1054                                         /* mac_rxd0 */
1055                                         <1 RK_PC4 3 &pcfg_pull_none>,
1056                                         /* mac_rxd1 */
1057                                         <1 RK_PC5 3 &pcfg_pull_none>,
1058                                         /* mac_rxer */
1059                                         <1 RK_PB7 3 &pcfg_pull_none>,
1060                                         /* mac_rxdv */
1061                                         <1 RK_PC0 3 &pcfg_pull_none>,
1062                                         /* mac_mdio */
1063                                         <1 RK_PB6 3 &pcfg_pull_none>,
1064                                         /* mac_mdc */
1065                                         <1 RK_PB5 3 &pcfg_pull_none>;
1066                         };
1067
1068                         mac_refclk_12ma: mac-refclk-12ma {
1069                                 rockchip,pins =
1070                                         <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1071                         };
1072
1073                         mac_refclk: mac-refclk {
1074                                 rockchip,pins =
1075                                         <1 RK_PB4 3 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 gmac-m1 {
1080                         rmiim1_pins: rmiim1-pins {
1081                                 rockchip,pins =
1082                                         /* mac_txen */
1083                                         <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1084                                         /* mac_txd1 */
1085                                         <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1086                                         /* mac_txd0 */
1087                                         <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1088                                         /* mac_rxd0 */
1089                                         <4 RK_PA2 2 &pcfg_pull_none>,
1090                                         /* mac_rxd1 */
1091                                         <4 RK_PA3 2 &pcfg_pull_none>,
1092                                         /* mac_rxer */
1093                                         <4 RK_PA0 2 &pcfg_pull_none>,
1094                                         /* mac_rxdv */
1095                                         <4 RK_PA1 2 &pcfg_pull_none>,
1096                                         /* mac_mdio */
1097                                         <4 RK_PB6 2 &pcfg_pull_none>,
1098                                         /* mac_mdc */
1099                                         <4 RK_PB5 2 &pcfg_pull_none>;
1100                         };
1101
1102                         macm1_refclk_12ma: macm1-refclk-12ma {
1103                                 rockchip,pins =
1104                                         <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1105                         };
1106
1107                         macm1_refclk: macm1-refclk {
1108                                 rockchip,pins =
1109                                         <4 RK_PB4 2 &pcfg_pull_none>;
1110                         };
1111                 };
1112
1113                 i2c0 {
1114                         i2c0_xfer: i2c0-xfer {
1115                                 rockchip,pins =
1116                                         <1 RK_PD0 2 &pcfg_pull_none_smt>,
1117                                         <1 RK_PD1 2 &pcfg_pull_none_smt>;
1118                         };
1119                 };
1120
1121                 i2c1 {
1122                         i2c1_xfer: i2c1-xfer {
1123                                 rockchip,pins =
1124                                         <0 RK_PB3 1 &pcfg_pull_none_smt>,
1125                                         <0 RK_PB4 1 &pcfg_pull_none_smt>;
1126                         };
1127                 };
1128
1129                 i2c2 {
1130                         i2c2_xfer: i2c2-xfer {
1131                                 rockchip,pins =
1132                                         <2 RK_PA2 3 &pcfg_pull_none_smt>,
1133                                         <2 RK_PA3 3 &pcfg_pull_none_smt>;
1134                         };
1135                 };
1136
1137                 i2c3-m0 {
1138                         i2c3m0_xfer: i2c3m0-xfer {
1139                                 rockchip,pins =
1140                                         <0 RK_PB7 2 &pcfg_pull_none_smt>,
1141                                         <0 RK_PC0 2 &pcfg_pull_none_smt>;
1142                         };
1143                 };
1144
1145                 i2c3-m1 {
1146                         i2c3m1_xfer: i2c3m1-xfer {
1147                                 rockchip,pins =
1148                                         <3 RK_PB4 2 &pcfg_pull_none_smt>,
1149                                         <3 RK_PB5 2 &pcfg_pull_none_smt>;
1150                         };
1151                 };
1152
1153                 i2c3-m2 {
1154                         i2c3m2_xfer: i2c3m2-xfer {
1155                                 rockchip,pins =
1156                                         <2 RK_PA1 3 &pcfg_pull_none_smt>,
1157                                         <2 RK_PA0 3 &pcfg_pull_none_smt>;
1158                         };
1159                 };
1160
1161                 i2s_2ch_0 {
1162                         i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1163                                 rockchip,pins =
1164                                         <4 RK_PB4 1 &pcfg_pull_none>;
1165                         };
1166
1167                         i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1168                                 rockchip,pins =
1169                                         <4 RK_PB5 1 &pcfg_pull_none>;
1170                         };
1171
1172                         i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1173                                 rockchip,pins =
1174                                         <4 RK_PB6 1 &pcfg_pull_none>;
1175                         };
1176
1177                         i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1178                                 rockchip,pins =
1179                                         <4 RK_PB7 1 &pcfg_pull_none>;
1180                         };
1181
1182                         i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1183                                 rockchip,pins =
1184                                         <4 RK_PC0 1 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 i2s_8ch_0 {
1189                         i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1190                                 rockchip,pins =
1191                                         <2 RK_PA4 1 &pcfg_pull_none>;
1192                         };
1193
1194                         i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1195                                 rockchip,pins =
1196                                         <2 RK_PA5 1 &pcfg_pull_none>;
1197                         };
1198
1199                         i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1200                                 rockchip,pins =
1201                                         <2 RK_PA6 1 &pcfg_pull_none>;
1202                         };
1203
1204                         i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1205                                 rockchip,pins =
1206                                         <2 RK_PA7 1 &pcfg_pull_none>;
1207                         };
1208
1209                         i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1210                                 rockchip,pins =
1211                                         <2 RK_PB0 1 &pcfg_pull_none>;
1212                         };
1213
1214                         i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1215                                 rockchip,pins =
1216                                         <2 RK_PB1 1 &pcfg_pull_none>;
1217                         };
1218
1219                         i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1220                                 rockchip,pins =
1221                                         <2 RK_PB2 1 &pcfg_pull_none>;
1222                         };
1223
1224                         i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1225                                 rockchip,pins =
1226                                         <2 RK_PB3 1 &pcfg_pull_none>;
1227                         };
1228
1229                         i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1230                                 rockchip,pins =
1231                                         <2 RK_PB4 1 &pcfg_pull_none>;
1232                         };
1233
1234                         i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1235                                 rockchip,pins =
1236                                         <2 RK_PB5 1 &pcfg_pull_none>;
1237                         };
1238
1239                         i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1240                                 rockchip,pins =
1241                                         <2 RK_PB6 1 &pcfg_pull_none>;
1242                         };
1243
1244                         i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1245                                 rockchip,pins =
1246                                         <2 RK_PB7 1 &pcfg_pull_none>;
1247                         };
1248
1249                         i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1250                                 rockchip,pins =
1251                                         <2 RK_PC0 1 &pcfg_pull_none>;
1252                         };
1253                 };
1254
1255                 i2s_8ch_1_m0 {
1256                         i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1257                                 rockchip,pins =
1258                                         <1 RK_PA2 2 &pcfg_pull_none>;
1259                         };
1260
1261                         i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1262                                 rockchip,pins =
1263                                         <1 RK_PA3 2 &pcfg_pull_none>;
1264                         };
1265
1266                         i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1267                                 rockchip,pins =
1268                                         <1 RK_PA4 2 &pcfg_pull_none>;
1269                         };
1270
1271                         i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1272                                 rockchip,pins =
1273                                         <1 RK_PA5 2 &pcfg_pull_none>;
1274                         };
1275
1276                         i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1277                                 rockchip,pins =
1278                                         <1 RK_PA6 2 &pcfg_pull_none>;
1279                         };
1280
1281                         i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1282                                 rockchip,pins =
1283                                         <1 RK_PA7 2 &pcfg_pull_none>;
1284                         };
1285
1286                         i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1287                                 rockchip,pins =
1288                                         <1 RK_PB0 2 &pcfg_pull_none>;
1289                         };
1290
1291                         i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1292                                 rockchip,pins =
1293                                         <1 RK_PB1 2 &pcfg_pull_none>;
1294                         };
1295
1296                         i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1297                                 rockchip,pins =
1298                                         <1 RK_PB2 2 &pcfg_pull_none>;
1299                         };
1300
1301                         i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1302                                 rockchip,pins =
1303                                         <1 RK_PB3 2 &pcfg_pull_none>;
1304                         };
1305                 };
1306
1307                 i2s_8ch_1_m1 {
1308                         i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1309                                 rockchip,pins =
1310                                         <1 RK_PB4 2 &pcfg_pull_none>;
1311                         };
1312
1313                         i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1314                                 rockchip,pins =
1315                                         <1 RK_PB5 2 &pcfg_pull_none>;
1316                         };
1317
1318                         i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1319                                 rockchip,pins =
1320                                         <1 RK_PB6 2 &pcfg_pull_none>;
1321                         };
1322
1323                         i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1324                                 rockchip,pins =
1325                                         <1 RK_PB7 2 &pcfg_pull_none>;
1326                         };
1327
1328                         i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1329                                 rockchip,pins =
1330                                         <1 RK_PC0 2 &pcfg_pull_none>;
1331                         };
1332
1333                         i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1334                                 rockchip,pins =
1335                                         <1 RK_PC1 2 &pcfg_pull_none>;
1336                         };
1337
1338                         i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1339                                 rockchip,pins =
1340                                         <1 RK_PC2 2 &pcfg_pull_none>;
1341                         };
1342
1343                         i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1344                                 rockchip,pins =
1345                                         <1 RK_PC3 2 &pcfg_pull_none>;
1346                         };
1347
1348                         i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1349                                 rockchip,pins =
1350                                         <1 RK_PC4 2 &pcfg_pull_none>;
1351                         };
1352
1353                         i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1354                                 rockchip,pins =
1355                                         <1 RK_PC5 2 &pcfg_pull_none>;
1356                         };
1357                 };
1358
1359                 pdm_m0 {
1360                         pdm_m0_clk: pdm-m0-clk {
1361                                 rockchip,pins =
1362                                         <1 RK_PA4 3 &pcfg_pull_none>;
1363                         };
1364
1365                         pdm_m0_sdi0: pdm-m0-sdi0 {
1366                                 rockchip,pins =
1367                                         <1 RK_PB3 3 &pcfg_pull_none>;
1368                         };
1369
1370                         pdm_m0_sdi1: pdm-m0-sdi1 {
1371                                 rockchip,pins =
1372                                         <1 RK_PB2 3 &pcfg_pull_none>;
1373                         };
1374
1375                         pdm_m0_sdi2: pdm-m0-sdi2 {
1376                                 rockchip,pins =
1377                                         <1 RK_PB1 3 &pcfg_pull_none>;
1378                         };
1379
1380                         pdm_m0_sdi3: pdm-m0-sdi3 {
1381                                 rockchip,pins =
1382                                         <1 RK_PB0 3 &pcfg_pull_none>;
1383                         };
1384                 };
1385
1386                 pdm_m1 {
1387                         pdm_m1_clk: pdm-m1-clk {
1388                                 rockchip,pins =
1389                                         <1 RK_PB6 4 &pcfg_pull_none>;
1390                         };
1391
1392                         pdm_m1_sdi0: pdm-m1-sdi0 {
1393                                 rockchip,pins =
1394                                         <1 RK_PC5 4 &pcfg_pull_none>;
1395                         };
1396
1397                         pdm_m1_sdi1: pdm-m1-sdi1 {
1398                                 rockchip,pins =
1399                                         <1 RK_PC4 4 &pcfg_pull_none>;
1400                         };
1401
1402                         pdm_m1_sdi2: pdm-m1-sdi2 {
1403                                 rockchip,pins =
1404                                         <1 RK_PC3 4 &pcfg_pull_none>;
1405                         };
1406
1407                         pdm_m1_sdi3: pdm-m1-sdi3 {
1408                                 rockchip,pins =
1409                                         <1 RK_PC2 4 &pcfg_pull_none>;
1410                         };
1411                 };
1412
1413                 pdm_m2 {
1414                         pdm_m2_clkm: pdm-m2-clkm {
1415                                 rockchip,pins =
1416                                         <2 RK_PA4 3 &pcfg_pull_none>;
1417                         };
1418
1419                         pdm_m2_clk: pdm-m2-clk {
1420                                 rockchip,pins =
1421                                         <2 RK_PA6 2 &pcfg_pull_none>;
1422                         };
1423
1424                         pdm_m2_sdi0: pdm-m2-sdi0 {
1425                                 rockchip,pins =
1426                                         <2 RK_PB5 2 &pcfg_pull_none>;
1427                         };
1428
1429                         pdm_m2_sdi1: pdm-m2-sdi1 {
1430                                 rockchip,pins =
1431                                         <2 RK_PB6 2 &pcfg_pull_none>;
1432                         };
1433
1434                         pdm_m2_sdi2: pdm-m2-sdi2 {
1435                                 rockchip,pins =
1436                                         <2 RK_PB7 2 &pcfg_pull_none>;
1437                         };
1438
1439                         pdm_m2_sdi3: pdm-m2-sdi3 {
1440                                 rockchip,pins =
1441                                         <2 RK_PC0 2 &pcfg_pull_none>;
1442                         };
1443                 };
1444
1445                 pwm0 {
1446                         pwm0_pin: pwm0-pin {
1447                                 rockchip,pins =
1448                                         <0 RK_PB5 1 &pcfg_pull_none>;
1449                         };
1450
1451                         pwm0_pin_pull_down: pwm0-pin-pull-down {
1452                                 rockchip,pins =
1453                                         <0 RK_PB5 1 &pcfg_pull_down>;
1454                         };
1455                 };
1456
1457                 pwm1 {
1458                         pwm1_pin: pwm1-pin {
1459                                 rockchip,pins =
1460                                         <0 RK_PB6 1 &pcfg_pull_none>;
1461                         };
1462
1463                         pwm1_pin_pull_down: pwm1-pin-pull-down {
1464                                 rockchip,pins =
1465                                         <0 RK_PB6 1 &pcfg_pull_down>;
1466                         };
1467                 };
1468
1469                 pwm2 {
1470                         pwm2_pin: pwm2-pin {
1471                                 rockchip,pins =
1472                                         <0 RK_PB7 1 &pcfg_pull_none>;
1473                         };
1474
1475                         pwm2_pin_pull_down: pwm2-pin-pull-down {
1476                                 rockchip,pins =
1477                                         <0 RK_PB7 1 &pcfg_pull_down>;
1478                         };
1479                 };
1480
1481                 pwm3 {
1482                         pwm3_pin: pwm3-pin {
1483                                 rockchip,pins =
1484                                         <0 RK_PC0 1 &pcfg_pull_none>;
1485                         };
1486
1487                         pwm3_pin_pull_down: pwm3-pin-pull-down {
1488                                 rockchip,pins =
1489                                         <0 RK_PC0 1 &pcfg_pull_down>;
1490                         };
1491                 };
1492
1493                 pwm4 {
1494                         pwm4_pin: pwm4-pin {
1495                                 rockchip,pins =
1496                                         <0 RK_PA1 2 &pcfg_pull_none>;
1497                         };
1498
1499                         pwm4_pin_pull_down: pwm4-pin-pull-down {
1500                                 rockchip,pins =
1501                                         <0 RK_PA1 2 &pcfg_pull_down>;
1502                         };
1503                 };
1504
1505                 pwm5 {
1506                         pwm5_pin: pwm5-pin {
1507                                 rockchip,pins =
1508                                         <0 RK_PC1 2 &pcfg_pull_none>;
1509                         };
1510
1511                         pwm5_pin_pull_down: pwm5-pin-pull-down {
1512                                 rockchip,pins =
1513                                         <0 RK_PC1 2 &pcfg_pull_down>;
1514                         };
1515                 };
1516
1517                 pwm6 {
1518                         pwm6_pin: pwm6-pin {
1519                                 rockchip,pins =
1520                                         <0 RK_PC2 2 &pcfg_pull_none>;
1521                         };
1522
1523                         pwm6_pin_pull_down: pwm6-pin-pull-down {
1524                                 rockchip,pins =
1525                                         <0 RK_PC2 2 &pcfg_pull_down>;
1526                         };
1527                 };
1528
1529                 pwm7 {
1530                         pwm7_pin: pwm7-pin {
1531                                 rockchip,pins =
1532                                         <2 RK_PB0 2 &pcfg_pull_none>;
1533                         };
1534
1535                         pwm7_pin_pull_down: pwm7-pin-pull-down {
1536                                 rockchip,pins =
1537                                         <2 RK_PB0 2 &pcfg_pull_down>;
1538                         };
1539                 };
1540
1541                 pwm8 {
1542                         pwm8_pin: pwm8-pin {
1543                                 rockchip,pins =
1544                                         <2 RK_PB2 2 &pcfg_pull_none>;
1545                         };
1546
1547                         pwm8_pin_pull_down: pwm8-pin-pull-down {
1548                                 rockchip,pins =
1549                                         <2 RK_PB2 2 &pcfg_pull_down>;
1550                         };
1551                 };
1552
1553                 pwm9 {
1554                         pwm9_pin: pwm9-pin {
1555                                 rockchip,pins =
1556                                         <2 RK_PB3 2 &pcfg_pull_none>;
1557                         };
1558
1559                         pwm9_pin_pull_down: pwm9-pin-pull-down {
1560                                 rockchip,pins =
1561                                         <2 RK_PB3 2 &pcfg_pull_down>;
1562                         };
1563                 };
1564
1565                 pwm10 {
1566                         pwm10_pin: pwm10-pin {
1567                                 rockchip,pins =
1568                                         <2 RK_PB4 2 &pcfg_pull_none>;
1569                         };
1570
1571                         pwm10_pin_pull_down: pwm10-pin-pull-down {
1572                                 rockchip,pins =
1573                                         <2 RK_PB4 2 &pcfg_pull_down>;
1574                         };
1575                 };
1576
1577                 pwm11 {
1578                         pwm11_pin: pwm11-pin {
1579                                 rockchip,pins =
1580                                         <2 RK_PC0 4 &pcfg_pull_none>;
1581                         };
1582
1583                         pwm11_pin_pull_down: pwm11-pin-pull-down {
1584                                 rockchip,pins =
1585                                         <2 RK_PC0 4 &pcfg_pull_down>;
1586                         };
1587                 };
1588
1589                 rtc {
1590                         rtc_32k: rtc-32k {
1591                                 rockchip,pins =
1592                                         <0 RK_PC3 1 &pcfg_pull_none>;
1593                         };
1594                 };
1595
1596                 sdmmc {
1597                         sdmmc_clk: sdmmc-clk {
1598                                 rockchip,pins =
1599                                         <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1600                         };
1601
1602                         sdmmc_cmd: sdmmc-cmd {
1603                                 rockchip,pins =
1604                                         <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1605                         };
1606
1607                         sdmmc_det: sdmmc-det {
1608                                 rockchip,pins =
1609                                         <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1610                         };
1611
1612                         sdmmc_pwren: sdmmc-pwren {
1613                                 rockchip,pins =
1614                                         <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1615                         };
1616
1617                         sdmmc_bus1: sdmmc-bus1 {
1618                                 rockchip,pins =
1619                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1620                         };
1621
1622                         sdmmc_bus4: sdmmc-bus4 {
1623                                 rockchip,pins =
1624                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1625                                         <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1626                                         <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1627                                         <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1628                         };
1629                 };
1630
1631                 sdio {
1632                         sdio_clk: sdio-clk {
1633                                 rockchip,pins =
1634                                         <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1635                         };
1636
1637                         sdio_cmd: sdio-cmd {
1638                                 rockchip,pins =
1639                                         <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1640                         };
1641
1642                         sdio_pwren: sdio-pwren {
1643                                 rockchip,pins =
1644                                         <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1645                         };
1646
1647                         sdio_wrpt: sdio-wrpt {
1648                                 rockchip,pins =
1649                                         <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1650                         };
1651
1652                         sdio_intn: sdio-intn {
1653                                 rockchip,pins =
1654                                         <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1655                         };
1656
1657                         sdio_bus1: sdio-bus1 {
1658                                 rockchip,pins =
1659                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1660                         };
1661
1662                         sdio_bus4: sdio-bus4 {
1663                                 rockchip,pins =
1664                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1665                                         <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1666                                         <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1667                                         <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1668                         };
1669                 };
1670
1671                 spdif_in {
1672                         spdif_in: spdif-in {
1673                                 rockchip,pins =
1674                                         <0 RK_PC2 1 &pcfg_pull_none>;
1675                         };
1676                 };
1677
1678                 spdif_out {
1679                         spdif_out: spdif-out {
1680                                 rockchip,pins =
1681                                         <0 RK_PC1 1 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 spi0 {
1686                         spi0_clk: spi0-clk {
1687                                 rockchip,pins =
1688                                         <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1689                         };
1690
1691                         spi0_csn0: spi0-csn0 {
1692                                 rockchip,pins =
1693                                         <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1694                         };
1695
1696                         spi0_miso: spi0-miso {
1697                                 rockchip,pins =
1698                                         <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1699                         };
1700
1701                         spi0_mosi: spi0-mosi {
1702                                 rockchip,pins =
1703                                         <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1704                         };
1705                 };
1706
1707                 spi1 {
1708                         spi1_clk: spi1-clk {
1709                                 rockchip,pins =
1710                                         <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1711                         };
1712
1713                         spi1_csn0: spi1-csn0 {
1714                                 rockchip,pins =
1715                                         <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1716                         };
1717
1718                         spi1_miso: spi1-miso {
1719                                 rockchip,pins =
1720                                         <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1721                         };
1722
1723                         spi1_mosi: spi1-mosi {
1724                                 rockchip,pins =
1725                                         <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1726                         };
1727                 };
1728
1729                 spi1-m1 {
1730                         spi1m1_miso: spi1m1-miso {
1731                                 rockchip,pins =
1732                                         <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1733                         };
1734
1735                         spi1m1_mosi: spi1m1-mosi {
1736                                 rockchip,pins =
1737                                         <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1738                         };
1739
1740                         spi1m1_clk: spi1m1-clk {
1741                                 rockchip,pins =
1742                                         <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1743                         };
1744
1745                         spi1m1_csn0: spi1m1-csn0 {
1746                                 rockchip,pins =
1747                                         <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1748                         };
1749                 };
1750
1751                 spi2 {
1752                         spi2_clk: spi2-clk {
1753                                 rockchip,pins =
1754                                         <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1755                         };
1756
1757                         spi2_csn0: spi2-csn0 {
1758                                 rockchip,pins =
1759                                         <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1760                         };
1761
1762                         spi2_miso: spi2-miso {
1763                                 rockchip,pins =
1764                                         <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1765                         };
1766
1767                         spi2_mosi: spi2-mosi {
1768                                 rockchip,pins =
1769                                         <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1770                         };
1771                 };
1772
1773                 tsadc {
1774                         tsadc_otp_pin: tsadc-otp-pin {
1775                                 rockchip,pins =
1776                                         <0 RK_PB2 0 &pcfg_pull_none>;
1777                         };
1778
1779                         tsadc_otp_out: tsadc-otp-out {
1780                                 rockchip,pins =
1781                                         <0 RK_PB2 1 &pcfg_pull_none>;
1782                         };
1783                 };
1784
1785                 uart0 {
1786                         uart0_xfer: uart0-xfer {
1787                                 rockchip,pins =
1788                                         <2 RK_PA1 1 &pcfg_pull_up>,
1789                                         <2 RK_PA0 1 &pcfg_pull_up>;
1790                         };
1791
1792                         uart0_cts: uart0-cts {
1793                                 rockchip,pins =
1794                                         <2 RK_PA2 1 &pcfg_pull_none>;
1795                         };
1796
1797                         uart0_rts: uart0-rts {
1798                                 rockchip,pins =
1799                                         <2 RK_PA3 1 &pcfg_pull_none>;
1800                         };
1801
1802                         uart0_rts_pin: uart0-rts-pin {
1803                                 rockchip,pins =
1804                                         <2 RK_PA3 0 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 uart1 {
1809                         uart1_xfer: uart1-xfer {
1810                                 rockchip,pins =
1811                                         <1 RK_PD1 1 &pcfg_pull_up>,
1812                                         <1 RK_PD0 1 &pcfg_pull_up>;
1813                         };
1814
1815                         uart1_cts: uart1-cts {
1816                                 rockchip,pins =
1817                                         <1 RK_PC6 1 &pcfg_pull_none>;
1818                         };
1819
1820                         uart1_rts: uart1-rts {
1821                                 rockchip,pins =
1822                                         <1 RK_PC7 1 &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 uart2-m0 {
1827                         uart2m0_xfer: uart2m0-xfer {
1828                                 rockchip,pins =
1829                                         <1 RK_PC7 2 &pcfg_pull_up>,
1830                                         <1 RK_PC6 2 &pcfg_pull_up>;
1831                         };
1832                 };
1833
1834                 uart2-m1 {
1835                         uart2m1_xfer: uart2m1-xfer {
1836                                 rockchip,pins =
1837                                         <4 RK_PD3 2 &pcfg_pull_up>,
1838                                         <4 RK_PD2 2 &pcfg_pull_up>;
1839                         };
1840                 };
1841
1842                 uart3 {
1843                         uart3_xfer: uart3-xfer {
1844                                 rockchip,pins =
1845                                         <3 RK_PB5 4 &pcfg_pull_up>,
1846                                         <3 RK_PB4 4 &pcfg_pull_up>;
1847                         };
1848                 };
1849
1850                 uart3-m1 {
1851                         uart3m1_xfer: uart3m1-xfer {
1852                                 rockchip,pins =
1853                                         <0 RK_PC2 3 &pcfg_pull_up>,
1854                                         <0 RK_PC1 3 &pcfg_pull_up>;
1855                         };
1856                 };
1857
1858                 uart4 {
1859                         uart4_xfer: uart4-xfer {
1860                                 rockchip,pins =
1861                                         <4 RK_PB1 1 &pcfg_pull_up>,
1862                                         <4 RK_PB0 1 &pcfg_pull_up>;
1863                         };
1864
1865                         uart4_cts: uart4-cts {
1866                                 rockchip,pins =
1867                                         <4 RK_PA6 1 &pcfg_pull_none>;
1868                         };
1869
1870                         uart4_rts: uart4-rts {
1871                                 rockchip,pins =
1872                                         <4 RK_PA7 1 &pcfg_pull_none>;
1873                         };
1874
1875                         uart4_rts_pin: uart4-rts-pin {
1876                                 rockchip,pins =
1877                                         <4 RK_PA7 0 &pcfg_pull_none>;
1878                         };
1879                 };
1880         };
1881 };