1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 compatible = "rockchip,px30";
17 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
46 clocks = <&cru ARMCLK>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
55 compatible = "arm,cortex-a35";
57 enable-method = "psci";
58 clocks = <&cru ARMCLK>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a35";
69 enable-method = "psci";
70 clocks = <&cru ARMCLK>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a35";
81 enable-method = "psci";
82 clocks = <&cru ARMCLK>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points-v2";
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <950000 950000 1350000>;
125 clock-latency-ns = <40000>;
128 opp-hz = /bits/ 64 <816000000>;
129 opp-microvolt = <1050000 1050000 1350000>;
130 clock-latency-ns = <40000>;
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1175000 1175000 1350000>;
135 clock-latency-ns = <40000>;
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <1300000 1300000 1350000>;
140 clock-latency-ns = <40000>;
143 opp-hz = /bits/ 64 <1296000000>;
144 opp-microvolt = <1350000 1350000 1350000>;
145 clock-latency-ns = <40000>;
150 compatible = "arm,cortex-a53-pmu";
151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
158 display_subsystem: display-subsystem {
159 compatible = "rockchip,display-subsystem";
160 ports = <&vopb_out>, <&vopl_out>;
166 compatible = "linaro,optee-tz";
171 gmac_clkin: external-gmac-clock {
172 compatible = "fixed-clock";
173 clock-frequency = <50000000>;
174 clock-output-names = "gmac_clkin";
179 compatible = "arm,psci-1.0";
184 compatible = "arm,armv8-timer";
185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
192 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
199 compatible = "fixed-clock";
201 clock-frequency = <32768>;
202 clock-output-names = "xin32k";
205 pmu: power-management@ff000000 {
206 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
207 reg = <0x0 0xff000000 0x0 0x1000>;
209 power: power-controller {
210 compatible = "rockchip,px30-power-controller";
211 #power-domain-cells = <1>;
212 #address-cells = <1>;
215 /* These power domains are grouped by VD_LOGIC */
216 power-domain@PX30_PD_USB {
218 clocks = <&cru HCLK_HOST>,
221 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
223 power-domain@PX30_PD_SDCARD {
224 reg = <PX30_PD_SDCARD>;
225 clocks = <&cru HCLK_SDMMC>,
227 pm_qos = <&qos_sdmmc>;
229 power-domain@PX30_PD_GMAC {
230 reg = <PX30_PD_GMAC>;
231 clocks = <&cru ACLK_GMAC>,
234 <&cru SCLK_GMAC_RX_TX>;
235 pm_qos = <&qos_gmac>;
237 power-domain@PX30_PD_MMC_NAND {
238 reg = <PX30_PD_MMC_NAND>;
239 clocks = <&cru HCLK_NANDC>,
247 pm_qos = <&qos_emmc>, <&qos_nand>,
248 <&qos_sdio>, <&qos_sfc>;
250 power-domain@PX30_PD_VPU {
252 clocks = <&cru ACLK_VPU>,
254 <&cru SCLK_CORE_VPU>;
255 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
257 power-domain@PX30_PD_VO {
259 clocks = <&cru ACLK_RGA>,
267 <&cru PCLK_MIPI_DSI>,
268 <&cru SCLK_RGA_CORE>,
269 <&cru SCLK_VOPB_PWM>;
270 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
271 <&qos_vop_m0>, <&qos_vop_m1>;
273 power-domain@PX30_PD_VI {
275 clocks = <&cru ACLK_CIF>,
280 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
281 <&qos_isp_wr>, <&qos_isp_m1>,
284 power-domain@PX30_PD_GPU {
286 clocks = <&cru SCLK_GPU>;
292 pmugrf: syscon@ff010000 {
293 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
294 reg = <0x0 0xff010000 0x0 0x1000>;
295 #address-cells = <1>;
298 pmu_io_domains: io-domains {
299 compatible = "rockchip,px30-pmu-io-voltage-domain";
304 compatible = "syscon-reboot-mode";
306 mode-bootloader = <BOOT_BL_DOWNLOAD>;
307 mode-fastboot = <BOOT_FASTBOOT>;
308 mode-loader = <BOOT_BL_DOWNLOAD>;
309 mode-normal = <BOOT_NORMAL>;
310 mode-recovery = <BOOT_RECOVERY>;
314 uart0: serial@ff030000 {
315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff030000 0x0 0x100>;
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 0>, <&dmac 1>;
321 dma-names = "tx", "rx";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
329 i2s1_2ch: i2s@ff070000 {
330 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
331 reg = <0x0 0xff070000 0x0 0x1000>;
332 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
334 clock-names = "i2s_clk", "i2s_hclk";
335 dmas = <&dmac 18>, <&dmac 19>;
336 dma-names = "tx", "rx";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
339 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
340 #sound-dai-cells = <0>;
344 i2s2_2ch: i2s@ff080000 {
345 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
346 reg = <0x0 0xff080000 0x0 0x1000>;
347 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
349 clock-names = "i2s_clk", "i2s_hclk";
350 dmas = <&dmac 20>, <&dmac 21>;
351 dma-names = "tx", "rx";
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
354 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
355 #sound-dai-cells = <0>;
359 gic: interrupt-controller@ff131000 {
360 compatible = "arm,gic-400";
361 #interrupt-cells = <3>;
362 #address-cells = <0>;
363 interrupt-controller;
364 reg = <0x0 0xff131000 0 0x1000>,
365 <0x0 0xff132000 0 0x2000>,
366 <0x0 0xff134000 0 0x2000>,
367 <0x0 0xff136000 0 0x2000>;
368 interrupts = <GIC_PPI 9
369 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
372 grf: syscon@ff140000 {
373 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
374 reg = <0x0 0xff140000 0x0 0x1000>;
375 #address-cells = <1>;
378 io_domains: io-domains {
379 compatible = "rockchip,px30-io-voltage-domain";
384 uart1: serial@ff158000 {
385 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
386 reg = <0x0 0xff158000 0x0 0x100>;
387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
389 clock-names = "baudclk", "apb_pclk";
390 dmas = <&dmac 2>, <&dmac 3>;
391 dma-names = "tx", "rx";
394 pinctrl-names = "default";
395 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
399 uart2: serial@ff160000 {
400 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
401 reg = <0x0 0xff160000 0x0 0x100>;
402 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
404 clock-names = "baudclk", "apb_pclk";
405 dmas = <&dmac 4>, <&dmac 5>;
406 dma-names = "tx", "rx";
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart2m0_xfer>;
414 uart3: serial@ff168000 {
415 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
416 reg = <0x0 0xff168000 0x0 0x100>;
417 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
419 clock-names = "baudclk", "apb_pclk";
420 dmas = <&dmac 6>, <&dmac 7>;
421 dma-names = "tx", "rx";
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
429 uart4: serial@ff170000 {
430 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
431 reg = <0x0 0xff170000 0x0 0x100>;
432 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
434 clock-names = "baudclk", "apb_pclk";
435 dmas = <&dmac 8>, <&dmac 9>;
436 dma-names = "tx", "rx";
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
444 uart5: serial@ff178000 {
445 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
446 reg = <0x0 0xff178000 0x0 0x100>;
447 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
449 clock-names = "baudclk", "apb_pclk";
450 dmas = <&dmac 10>, <&dmac 11>;
451 dma-names = "tx", "rx";
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
460 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
461 reg = <0x0 0xff180000 0x0 0x1000>;
462 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
463 clock-names = "i2c", "pclk";
464 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c0_xfer>;
467 #address-cells = <1>;
473 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
474 reg = <0x0 0xff190000 0x0 0x1000>;
475 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
476 clock-names = "i2c", "pclk";
477 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c1_xfer>;
480 #address-cells = <1>;
486 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
487 reg = <0x0 0xff1a0000 0x0 0x1000>;
488 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
489 clock-names = "i2c", "pclk";
490 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&i2c2_xfer>;
493 #address-cells = <1>;
499 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
500 reg = <0x0 0xff1b0000 0x0 0x1000>;
501 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
502 clock-names = "i2c", "pclk";
503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c3_xfer>;
506 #address-cells = <1>;
512 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
513 reg = <0x0 0xff1d0000 0x0 0x1000>;
514 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
516 clock-names = "spiclk", "apb_pclk";
517 dmas = <&dmac 12>, <&dmac 13>;
518 dma-names = "tx", "rx";
519 pinctrl-names = "default";
520 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
521 #address-cells = <1>;
527 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
528 reg = <0x0 0xff1d8000 0x0 0x1000>;
529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
531 clock-names = "spiclk", "apb_pclk";
532 dmas = <&dmac 14>, <&dmac 15>;
533 dma-names = "tx", "rx";
534 pinctrl-names = "default";
535 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
536 #address-cells = <1>;
541 wdt: watchdog@ff1e0000 {
542 compatible = "snps,dw-wdt";
543 reg = <0x0 0xff1e0000 0x0 0x100>;
544 clocks = <&cru PCLK_WDT_NS>;
545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
550 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
551 reg = <0x0 0xff200000 0x0 0x10>;
552 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
553 clock-names = "pwm", "pclk";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pwm0_pin>;
561 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
562 reg = <0x0 0xff200010 0x0 0x10>;
563 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
564 clock-names = "pwm", "pclk";
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm1_pin>;
572 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
573 reg = <0x0 0xff200020 0x0 0x10>;
574 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
575 clock-names = "pwm", "pclk";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm2_pin>;
583 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
584 reg = <0x0 0xff200030 0x0 0x10>;
585 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
586 clock-names = "pwm", "pclk";
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm3_pin>;
594 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
595 reg = <0x0 0xff208000 0x0 0x10>;
596 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
597 clock-names = "pwm", "pclk";
598 pinctrl-names = "default";
599 pinctrl-0 = <&pwm4_pin>;
605 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
606 reg = <0x0 0xff208010 0x0 0x10>;
607 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
608 clock-names = "pwm", "pclk";
609 pinctrl-names = "default";
610 pinctrl-0 = <&pwm5_pin>;
616 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
617 reg = <0x0 0xff208020 0x0 0x10>;
618 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
619 clock-names = "pwm", "pclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&pwm6_pin>;
627 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
628 reg = <0x0 0xff208030 0x0 0x10>;
629 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
630 clock-names = "pwm", "pclk";
631 pinctrl-names = "default";
632 pinctrl-0 = <&pwm7_pin>;
637 rktimer: timer@ff210000 {
638 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
639 reg = <0x0 0xff210000 0x0 0x1000>;
640 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
642 clock-names = "pclk", "timer";
646 compatible = "simple-bus";
647 #address-cells = <2>;
651 dmac: dmac@ff240000 {
652 compatible = "arm,pl330", "arm,primecell";
653 reg = <0x0 0xff240000 0x0 0x4000>;
654 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&cru ACLK_DMAC>;
657 clock-names = "apb_pclk";
662 saradc: saradc@ff288000 {
663 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
664 reg = <0x0 0xff288000 0x0 0x100>;
665 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
666 #io-channel-cells = <1>;
667 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
668 clock-names = "saradc", "apb_pclk";
669 resets = <&cru SRST_SARADC_P>;
670 reset-names = "saradc-apb";
674 cru: clock-controller@ff2b0000 {
675 compatible = "rockchip,px30-cru";
676 reg = <0x0 0xff2b0000 0x0 0x1000>;
677 rockchip,grf = <&grf>;
681 assigned-clocks = <&cru PLL_NPLL>;
682 assigned-clock-rates = <1188000000>;
685 pmucru: clock-controller@ff2bc000 {
686 compatible = "rockchip,px30-pmucru";
687 reg = <0x0 0xff2bc000 0x0 0x1000>;
688 rockchip,grf = <&grf>;
693 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
694 <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
695 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
696 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
697 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
698 assigned-clock-rates =
699 <1200000000>, <100000000>,
700 <26000000>, <600000000>,
701 <200000000>, <200000000>,
702 <150000000>, <150000000>,
703 <100000000>, <200000000>;
706 usb20_otg: usb@ff300000 {
707 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
709 reg = <0x0 0xff300000 0x0 0x40000>;
710 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru HCLK_OTG>;
714 g-np-tx-fifo-size = <16>;
715 g-rx-fifo-size = <280>;
716 g-tx-fifo-size = <256 128 128 64 32 16>;
718 power-domains = <&power PX30_PD_USB>;
722 usb_host0_ehci: usb@ff340000 {
723 compatible = "generic-ehci";
724 reg = <0x0 0xff340000 0x0 0x10000>;
725 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cru HCLK_HOST>;
727 clock-names = "usbhost";
728 power-domains = <&power PX30_PD_USB>;
732 usb_host0_ohci: usb@ff350000 {
733 compatible = "generic-ohci";
734 reg = <0x0 0xff350000 0x0 0x10000>;
735 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&cru HCLK_HOST>;
737 clock-names = "usbhost";
738 power-domains = <&power PX30_PD_USB>;
742 gmac: ethernet@ff360000 {
743 compatible = "rockchip,px30-gmac";
744 reg = <0x0 0xff360000 0x0 0x10000>;
745 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
746 interrupt-names = "macirq";
747 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
748 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
749 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
750 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
751 clock-names = "stmmaceth", "mac_clk_rx",
752 "mac_clk_tx", "clk_mac_ref",
753 "clk_mac_refout", "aclk_mac",
754 "pclk_mac", "clk_mac_speed";
755 rockchip,grf = <&grf>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
759 power-domains = <&power PX30_PD_GMAC>;
760 resets = <&cru SRST_GMAC_A>;
761 reset-names = "stmmaceth";
765 sdmmc: dwmmc@ff370000 {
766 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
767 reg = <0x0 0xff370000 0x0 0x4000>;
768 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
770 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
771 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
772 fifo-depth = <0x100>;
773 max-frequency = <150000000>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
776 power-domains = <&power PX30_PD_SDCARD>;
780 sdio: dwmmc@ff380000 {
781 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
782 reg = <0x0 0xff380000 0x0 0x4000>;
783 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
785 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
786 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
787 fifo-depth = <0x100>;
788 max-frequency = <150000000>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
791 power-domains = <&power PX30_PD_MMC_NAND>;
795 emmc: dwmmc@ff390000 {
796 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
797 reg = <0x0 0xff390000 0x0 0x4000>;
798 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
800 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
801 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
802 fifo-depth = <0x100>;
803 max-frequency = <150000000>;
804 power-domains = <&power PX30_PD_MMC_NAND>;
809 compatible = "rockchip,px30-vop-big";
810 reg = <0x0 0xff460000 0x0 0xefc>;
811 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
814 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
815 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
816 reset-names = "axi", "ahb", "dclk";
817 iommus = <&vopb_mmu>;
818 power-domains = <&power PX30_PD_VO>;
819 rockchip,grf = <&grf>;
823 #address-cells = <1>;
828 vopb_mmu: iommu@ff460f00 {
829 compatible = "rockchip,iommu";
830 reg = <0x0 0xff460f00 0x0 0x100>;
831 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
832 interrupt-names = "vopb_mmu";
833 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
834 clock-names = "aclk", "hclk";
835 power-domains = <&power PX30_PD_VO>;
841 compatible = "rockchip,px30-vop-lit";
842 reg = <0x0 0xff470000 0x0 0xefc>;
843 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
847 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
848 reset-names = "axi", "ahb", "dclk";
849 iommus = <&vopl_mmu>;
850 power-domains = <&power PX30_PD_VO>;
851 rockchip,grf = <&grf>;
855 #address-cells = <1>;
860 vopl_mmu: iommu@ff470f00 {
861 compatible = "rockchip,iommu";
862 reg = <0x0 0xff470f00 0x0 0x100>;
863 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-names = "vopl_mmu";
865 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
866 clock-names = "aclk", "hclk";
867 power-domains = <&power PX30_PD_VO>;
872 qos_gmac: qos@ff518000 {
873 compatible = "syscon";
874 reg = <0x0 0xff518000 0x0 0x20>;
877 qos_gpu: qos@ff520000 {
878 compatible = "syscon";
879 reg = <0x0 0xff520000 0x0 0x20>;
882 qos_sdmmc: qos@ff52c000 {
883 compatible = "syscon";
884 reg = <0x0 0xff52c000 0x0 0x20>;
887 qos_emmc: qos@ff538000 {
888 compatible = "syscon";
889 reg = <0x0 0xff538000 0x0 0x20>;
892 qos_nand: qos@ff538080 {
893 compatible = "syscon";
894 reg = <0x0 0xff538080 0x0 0x20>;
897 qos_sdio: qos@ff538100 {
898 compatible = "syscon";
899 reg = <0x0 0xff538100 0x0 0x20>;
902 qos_sfc: qos@ff538180 {
903 compatible = "syscon";
904 reg = <0x0 0xff538180 0x0 0x20>;
907 qos_usb_host: qos@ff540000 {
908 compatible = "syscon";
909 reg = <0x0 0xff540000 0x0 0x20>;
912 qos_usb_otg: qos@ff540080 {
913 compatible = "syscon";
914 reg = <0x0 0xff540080 0x0 0x20>;
917 qos_isp_128: qos@ff548000 {
918 compatible = "syscon";
919 reg = <0x0 0xff548000 0x0 0x20>;
922 qos_isp_rd: qos@ff548080 {
923 compatible = "syscon";
924 reg = <0x0 0xff548080 0x0 0x20>;
927 qos_isp_wr: qos@ff548100 {
928 compatible = "syscon";
929 reg = <0x0 0xff548100 0x0 0x20>;
932 qos_isp_m1: qos@ff548180 {
933 compatible = "syscon";
934 reg = <0x0 0xff548180 0x0 0x20>;
937 qos_vip: qos@ff548200 {
938 compatible = "syscon";
939 reg = <0x0 0xff548200 0x0 0x20>;
942 qos_rga_rd: qos@ff550000 {
943 compatible = "syscon";
944 reg = <0x0 0xff550000 0x0 0x20>;
947 qos_rga_wr: qos@ff550080 {
948 compatible = "syscon";
949 reg = <0x0 0xff550080 0x0 0x20>;
952 qos_vop_m0: qos@ff550100 {
953 compatible = "syscon";
954 reg = <0x0 0xff550100 0x0 0x20>;
957 qos_vop_m1: qos@ff550180 {
958 compatible = "syscon";
959 reg = <0x0 0xff550180 0x0 0x20>;
962 qos_vpu: qos@ff558000 {
963 compatible = "syscon";
964 reg = <0x0 0xff558000 0x0 0x20>;
967 qos_vpu_r128: qos@ff558080 {
968 compatible = "syscon";
969 reg = <0x0 0xff558080 0x0 0x20>;
973 compatible = "rockchip,px30-pinctrl";
974 rockchip,grf = <&grf>;
975 rockchip,pmu = <&pmugrf>;
976 #address-cells = <2>;
980 gpio0: gpio0@ff040000 {
981 compatible = "rockchip,gpio-bank";
982 reg = <0x0 0xff040000 0x0 0x100>;
983 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&pmucru PCLK_GPIO0_PMU>;
988 interrupt-controller;
989 #interrupt-cells = <2>;
992 gpio1: gpio1@ff250000 {
993 compatible = "rockchip,gpio-bank";
994 reg = <0x0 0xff250000 0x0 0x100>;
995 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&cru PCLK_GPIO1>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1004 gpio2: gpio2@ff260000 {
1005 compatible = "rockchip,gpio-bank";
1006 reg = <0x0 0xff260000 0x0 0x100>;
1007 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&cru PCLK_GPIO2>;
1012 interrupt-controller;
1013 #interrupt-cells = <2>;
1016 gpio3: gpio3@ff270000 {
1017 compatible = "rockchip,gpio-bank";
1018 reg = <0x0 0xff270000 0x0 0x100>;
1019 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&cru PCLK_GPIO3>;
1024 interrupt-controller;
1025 #interrupt-cells = <2>;
1028 pcfg_pull_up: pcfg-pull-up {
1032 pcfg_pull_down: pcfg-pull-down {
1036 pcfg_pull_none: pcfg-pull-none {
1040 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1042 drive-strength = <2>;
1045 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1047 drive-strength = <2>;
1050 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1052 drive-strength = <4>;
1055 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1057 drive-strength = <4>;
1060 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1062 drive-strength = <4>;
1065 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1067 drive-strength = <8>;
1070 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1072 drive-strength = <8>;
1075 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1077 drive-strength = <12>;
1080 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1082 drive-strength = <12>;
1085 pcfg_pull_none_smt: pcfg-pull-none-smt {
1087 input-schmitt-enable;
1090 pcfg_output_high: pcfg-output-high {
1094 pcfg_output_low: pcfg-output-low {
1098 pcfg_input_high: pcfg-input-high {
1103 pcfg_input: pcfg-input {
1108 i2c0_xfer: i2c0-xfer {
1110 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1111 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1116 i2c1_xfer: i2c1-xfer {
1118 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1119 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1124 i2c2_xfer: i2c2-xfer {
1126 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1127 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1132 i2c3_xfer: i2c3-xfer {
1134 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1135 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1140 tsadc_otp_gpio: tsadc-otp-gpio {
1142 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1145 tsadc_otp_out: tsadc-otp-out {
1147 <0 RK_PA6 1 &pcfg_pull_none>;
1152 uart0_xfer: uart0-xfer {
1154 <0 RK_PB2 1 &pcfg_pull_up>,
1155 <0 RK_PB3 1 &pcfg_pull_up>;
1158 uart0_cts: uart0-cts {
1160 <0 RK_PB4 1 &pcfg_pull_none>;
1163 uart0_rts: uart0-rts {
1165 <0 RK_PB5 1 &pcfg_pull_none>;
1168 uart0_rts_gpio: uart0-rts-gpio {
1170 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1175 uart1_xfer: uart1-xfer {
1177 <1 RK_PC1 1 &pcfg_pull_up>,
1178 <1 RK_PC0 1 &pcfg_pull_up>;
1181 uart1_cts: uart1-cts {
1183 <1 RK_PC2 1 &pcfg_pull_none>;
1186 uart1_rts: uart1-rts {
1188 <1 RK_PC3 1 &pcfg_pull_none>;
1191 uart1_rts_gpio: uart1-rts-gpio {
1193 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1198 uart2m0_xfer: uart2m0-xfer {
1200 <1 RK_PD2 2 &pcfg_pull_up>,
1201 <1 RK_PD3 2 &pcfg_pull_up>;
1206 uart2m1_xfer: uart2m1-xfer {
1208 <2 RK_PB4 2 &pcfg_pull_up>,
1209 <2 RK_PB6 2 &pcfg_pull_up>;
1214 uart3m0_xfer: uart3m0-xfer {
1216 <0 RK_PC0 2 &pcfg_pull_up>,
1217 <0 RK_PC1 2 &pcfg_pull_up>;
1220 uart3m0_cts: uart3m0-cts {
1222 <0 RK_PC2 2 &pcfg_pull_none>;
1225 uart3m0_rts: uart3m0-rts {
1227 <0 RK_PC3 2 &pcfg_pull_none>;
1230 uart3m0_rts_gpio: uart3m0-rts-gpio {
1232 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1237 uart3m1_xfer: uart3m1-xfer {
1239 <1 RK_PB6 2 &pcfg_pull_up>,
1240 <1 RK_PB7 2 &pcfg_pull_up>;
1243 uart3m1_cts: uart3m1-cts {
1245 <1 RK_PB4 2 &pcfg_pull_none>;
1248 uart3m1_rts: uart3m1-rts {
1250 <1 RK_PB5 2 &pcfg_pull_none>;
1253 uart3m1_rts_gpio: uart3m1-rts-gpio {
1255 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1260 uart4_xfer: uart4-xfer {
1262 <1 RK_PD4 2 &pcfg_pull_up>,
1263 <1 RK_PD5 2 &pcfg_pull_up>;
1266 uart4_cts: uart4-cts {
1268 <1 RK_PD6 2 &pcfg_pull_none>;
1271 uart4_rts: uart4-rts {
1273 <1 RK_PD7 2 &pcfg_pull_none>;
1278 uart5_xfer: uart5-xfer {
1280 <3 RK_PA2 4 &pcfg_pull_up>,
1281 <3 RK_PA1 4 &pcfg_pull_up>;
1284 uart5_cts: uart5-cts {
1286 <3 RK_PA3 4 &pcfg_pull_none>;
1289 uart5_rts: uart5-rts {
1291 <3 RK_PA5 4 &pcfg_pull_none>;
1296 spi0_clk: spi0-clk {
1298 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1301 spi0_csn: spi0-csn {
1303 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1306 spi0_miso: spi0-miso {
1308 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1311 spi0_mosi: spi0-mosi {
1313 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1316 spi0_clk_hs: spi0-clk-hs {
1318 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1321 spi0_miso_hs: spi0-miso-hs {
1323 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1326 spi0_mosi_hs: spi0-mosi-hs {
1328 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1333 spi1_clk: spi1-clk {
1335 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1338 spi1_csn0: spi1-csn0 {
1340 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1343 spi1_csn1: spi1-csn1 {
1345 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1348 spi1_miso: spi1-miso {
1350 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1353 spi1_mosi: spi1-mosi {
1355 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1358 spi1_clk_hs: spi1-clk-hs {
1360 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1363 spi1_miso_hs: spi1-miso-hs {
1365 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1368 spi1_mosi_hs: spi1-mosi-hs {
1370 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1375 pdm_clk0m0: pdm-clk0m0 {
1377 <3 RK_PC6 2 &pcfg_pull_none>;
1380 pdm_clk0m1: pdm-clk0m1 {
1382 <2 RK_PC6 1 &pcfg_pull_none>;
1385 pdm_clk1: pdm-clk1 {
1387 <3 RK_PC7 2 &pcfg_pull_none>;
1390 pdm_sdi0m0: pdm-sdi0m0 {
1392 <3 RK_PD3 2 &pcfg_pull_none>;
1395 pdm_sdi0m1: pdm-sdi0m1 {
1397 <2 RK_PC5 2 &pcfg_pull_none>;
1400 pdm_sdi1: pdm-sdi1 {
1402 <3 RK_PD0 2 &pcfg_pull_none>;
1405 pdm_sdi2: pdm-sdi2 {
1407 <3 RK_PD1 2 &pcfg_pull_none>;
1410 pdm_sdi3: pdm-sdi3 {
1412 <3 RK_PD2 2 &pcfg_pull_none>;
1415 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1417 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1420 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1422 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1425 pdm_clk1_sleep: pdm-clk1-sleep {
1427 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1430 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1432 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1435 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1437 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1440 pdm_sdi1_sleep: pdm-sdi1-sleep {
1442 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1445 pdm_sdi2_sleep: pdm-sdi2-sleep {
1447 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1450 pdm_sdi3_sleep: pdm-sdi3-sleep {
1452 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1457 i2s0_8ch_mclk: i2s0-8ch-mclk {
1459 <3 RK_PC1 2 &pcfg_pull_none>;
1462 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1464 <3 RK_PC3 2 &pcfg_pull_none>;
1467 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1469 <3 RK_PB4 2 &pcfg_pull_none>;
1472 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1474 <3 RK_PC2 2 &pcfg_pull_none>;
1477 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1479 <3 RK_PB5 2 &pcfg_pull_none>;
1482 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1484 <3 RK_PC4 2 &pcfg_pull_none>;
1487 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1489 <3 RK_PC0 2 &pcfg_pull_none>;
1492 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1494 <3 RK_PB7 2 &pcfg_pull_none>;
1497 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1499 <3 RK_PB6 2 &pcfg_pull_none>;
1502 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1504 <3 RK_PC5 2 &pcfg_pull_none>;
1507 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1509 <3 RK_PB3 2 &pcfg_pull_none>;
1512 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1514 <3 RK_PB1 2 &pcfg_pull_none>;
1517 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1519 <3 RK_PB0 2 &pcfg_pull_none>;
1524 i2s1_2ch_mclk: i2s1-2ch-mclk {
1526 <2 RK_PC3 1 &pcfg_pull_none>;
1529 i2s1_2ch_sclk: i2s1-2ch-sclk {
1531 <2 RK_PC2 1 &pcfg_pull_none>;
1534 i2s1_2ch_lrck: i2s1-2ch-lrck {
1536 <2 RK_PC1 1 &pcfg_pull_none>;
1539 i2s1_2ch_sdi: i2s1-2ch-sdi {
1541 <2 RK_PC5 1 &pcfg_pull_none>;
1544 i2s1_2ch_sdo: i2s1-2ch-sdo {
1546 <2 RK_PC4 1 &pcfg_pull_none>;
1551 i2s2_2ch_mclk: i2s2-2ch-mclk {
1553 <3 RK_PA1 2 &pcfg_pull_none>;
1556 i2s2_2ch_sclk: i2s2-2ch-sclk {
1558 <3 RK_PA2 2 &pcfg_pull_none>;
1561 i2s2_2ch_lrck: i2s2-2ch-lrck {
1563 <3 RK_PA3 2 &pcfg_pull_none>;
1566 i2s2_2ch_sdi: i2s2-2ch-sdi {
1568 <3 RK_PA5 2 &pcfg_pull_none>;
1571 i2s2_2ch_sdo: i2s2-2ch-sdo {
1573 <3 RK_PA7 2 &pcfg_pull_none>;
1578 sdmmc_clk: sdmmc-clk {
1580 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1583 sdmmc_cmd: sdmmc-cmd {
1585 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1588 sdmmc_det: sdmmc-det {
1590 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1593 sdmmc_bus1: sdmmc-bus1 {
1595 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1598 sdmmc_bus4: sdmmc-bus4 {
1600 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1601 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1602 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1603 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1606 sdmmc_gpio: sdmmc-gpio {
1608 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1609 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1610 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1611 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1612 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1613 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1618 sdio_clk: sdio-clk {
1620 <1 RK_PC5 1 &pcfg_pull_none>;
1623 sdio_cmd: sdio-cmd {
1625 <1 RK_PC4 1 &pcfg_pull_up>;
1628 sdio_bus4: sdio-bus4 {
1630 <1 RK_PC6 1 &pcfg_pull_up>,
1631 <1 RK_PC7 1 &pcfg_pull_up>,
1632 <1 RK_PD0 1 &pcfg_pull_up>,
1633 <1 RK_PD1 1 &pcfg_pull_up>;
1636 sdio_gpio: sdio-gpio {
1638 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
1639 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
1640 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
1641 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
1642 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
1643 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
1648 emmc_clk: emmc-clk {
1650 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1653 emmc_cmd: emmc-cmd {
1655 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1658 emmc_pwren: emmc-pwren {
1660 <1 RK_PB0 2 &pcfg_pull_none>;
1663 emmc_rstnout: emmc-rstnout {
1665 <1 RK_PB3 2 &pcfg_pull_none>;
1668 emmc_bus1: emmc-bus1 {
1670 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1673 emmc_bus4: emmc-bus4 {
1675 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1676 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1677 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1678 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1681 emmc_bus8: emmc-bus8 {
1683 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1684 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1685 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1686 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1687 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1688 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1689 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1690 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1695 flash_cs0: flash-cs0 {
1697 <1 RK_PB0 1 &pcfg_pull_none>;
1700 flash_rdy: flash-rdy {
1702 <1 RK_PB1 1 &pcfg_pull_none>;
1705 flash_dqs: flash-dqs {
1707 <1 RK_PB2 1 &pcfg_pull_none>;
1710 flash_ale: flash-ale {
1712 <1 RK_PB3 1 &pcfg_pull_none>;
1715 flash_cle: flash-cle {
1717 <1 RK_PB4 1 &pcfg_pull_none>;
1720 flash_wrn: flash-wrn {
1722 <1 RK_PB5 1 &pcfg_pull_none>;
1725 flash_csl: flash-csl {
1727 <1 RK_PB6 1 &pcfg_pull_none>;
1730 flash_rdn: flash-rdn {
1732 <1 RK_PB7 1 &pcfg_pull_none>;
1735 flash_bus8: flash-bus8 {
1737 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1738 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1739 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1740 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1741 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1742 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1743 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1744 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1749 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1751 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1754 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1756 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1759 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1761 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1764 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1766 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1769 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1771 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1772 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1773 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1774 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1775 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1776 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1777 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1778 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1779 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1780 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1781 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1782 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1783 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1784 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1785 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1786 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1787 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1788 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1789 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1790 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1791 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1792 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1793 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1794 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1797 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1799 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1800 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1801 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1802 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1803 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1804 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1805 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1806 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1807 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1808 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1809 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1810 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1811 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1812 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1813 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1814 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1815 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1816 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1819 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1821 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1822 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1823 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1824 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1825 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1826 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1827 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1828 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1829 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1830 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1831 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1832 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1833 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1834 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1835 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1836 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1839 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1841 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1842 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1843 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1844 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1845 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1846 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1847 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1848 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1849 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1850 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1851 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1852 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1853 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1854 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1855 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1856 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1857 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1860 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1862 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1863 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1864 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1865 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1866 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1867 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1868 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1869 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1870 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1871 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1872 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1875 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1877 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1878 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1879 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1880 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1881 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1882 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1883 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1884 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1885 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1890 pwm0_pin: pwm0-pin {
1892 <0 RK_PB7 1 &pcfg_pull_none>;
1897 pwm1_pin: pwm1-pin {
1899 <0 RK_PC0 1 &pcfg_pull_none>;
1904 pwm2_pin: pwm2-pin {
1906 <2 RK_PB5 1 &pcfg_pull_none>;
1911 pwm3_pin: pwm3-pin {
1913 <0 RK_PC1 1 &pcfg_pull_none>;
1918 pwm4_pin: pwm4-pin {
1920 <3 RK_PC2 3 &pcfg_pull_none>;
1925 pwm5_pin: pwm5-pin {
1927 <3 RK_PC3 3 &pcfg_pull_none>;
1932 pwm6_pin: pwm6-pin {
1934 <3 RK_PC4 3 &pcfg_pull_none>;
1939 pwm7_pin: pwm7-pin {
1941 <3 RK_PC5 3 &pcfg_pull_none>;
1946 rmii_pins: rmii-pins {
1948 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
1949 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
1950 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
1951 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
1952 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
1953 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
1954 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
1955 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
1956 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
1959 mac_refclk_12ma: mac-refclk-12ma {
1961 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
1964 mac_refclk: mac-refclk {
1966 <2 RK_PB2 2 &pcfg_pull_none>;
1971 cif_clkout_m0: cif-clkout-m0 {
1973 <2 RK_PB3 1 &pcfg_pull_none>;
1976 dvp_d2d9_m0: dvp-d2d9-m0 {
1978 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
1979 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
1980 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
1981 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
1982 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
1983 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
1984 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
1985 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
1986 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
1987 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
1988 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
1989 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
1992 dvp_d0d1_m0: dvp-d0d1-m0 {
1994 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
1995 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
1998 dvp_d10d11_m0:d10-d11-m0 {
2000 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2001 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2006 cif_clkout_m1: cif-clkout-m1 {
2008 <3 RK_PD0 3 &pcfg_pull_none>;
2011 dvp_d2d9_m1: dvp-d2d9-m1 {
2013 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2014 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2015 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2016 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2017 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2018 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2019 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2020 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2021 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2022 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2023 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2024 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2027 dvp_d0d1_m1: dvp-d0d1-m1 {
2029 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2030 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2033 dvp_d10d11_m1:d10-d11-m1 {
2035 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2036 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2041 isp_prelight: isp-prelight {
2043 <3 RK_PD1 4 &pcfg_pull_none>;