arch/arm64/boot/dts/rockchip/px30.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/px30-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/px30-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,px30";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &gmac;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &uart2;
  31                 serial3 = &uart3;
  32                 serial4 = &uart4;
  33                 serial5 = &uart5;
  34                 spi0 = &spi0;
  35                 spi1 = &spi1;
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a35";
  45                         reg = <0x0 0x0>;
  46                         enable-method = "psci";
  47                         clocks = <&cru ARMCLK>;
  48                         #cooling-cells = <2>;
  49                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  50                         dynamic-power-coefficient = <90>;
  51                         operating-points-v2 = <&cpu0_opp_table>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         clocks = <&cru ARMCLK>;
  60                         #cooling-cells = <2>;
  61                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  62                         dynamic-power-coefficient = <90>;
  63                         operating-points-v2 = <&cpu0_opp_table>;
  64                 };
  65
  66                 cpu2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a35";
  69                         reg = <0x0 0x2>;
  70                         enable-method = "psci";
  71                         clocks = <&cru ARMCLK>;
  72                         #cooling-cells = <2>;
  73                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  74                         dynamic-power-coefficient = <90>;
  75                         operating-points-v2 = <&cpu0_opp_table>;
  76                 };
  77
  78                 cpu3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a35";
  81                         reg = <0x0 0x3>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         #cooling-cells = <2>;
  85                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  86                         dynamic-power-coefficient = <90>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101
 102                         CLUSTER_SLEEP: cluster-sleep {
 103                                 compatible = "arm,idle-state";
 104                                 local-timer-stop;
 105                                 arm,psci-suspend-param = <0x1010000>;
 106                                 entry-latency-us = <400>;
 107                                 exit-latency-us = <500>;
 108                                 min-residency-us = <2000>;
 109                         };
 110                 };
 111         };
 112
 113         cpu0_opp_table: opp-table-0 {
 114                 compatible = "operating-points-v2";
 115                 opp-shared;
 116
 117                 opp-600000000 {
 118                         opp-hz = /bits/ 64 <600000000>;
 119                         opp-microvolt = <950000 950000 1350000>;
 120                         clock-latency-ns = <40000>;
 121                         opp-suspend;
 122                 };
 123                 opp-816000000 {
 124                         opp-hz = /bits/ 64 <816000000>;
 125                         opp-microvolt = <1050000 1050000 1350000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp-1008000000 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1175000 1175000 1350000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp-1200000000 {
 134                         opp-hz = /bits/ 64 <1200000000>;
 135                         opp-microvolt = <1300000 1300000 1350000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138                 opp-1296000000 {
 139                         opp-hz = /bits/ 64 <1296000000>;
 140                         opp-microvolt = <1350000 1350000 1350000>;
 141                         clock-latency-ns = <40000>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a35-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         display_subsystem: display-subsystem {
 155                 compatible = "rockchip,display-subsystem";
 156                 ports = <&vopb_out>, <&vopl_out>;
 157                 status = "disabled";
 158         };
 159
 160         gmac_clkin: external-gmac-clock {
 161                 compatible = "fixed-clock";
 162                 clock-frequency = <50000000>;
 163                 clock-output-names = "gmac_clkin";
 164                 #clock-cells = <0>;
 165         };
 166
 167         psci {
 168                 compatible = "arm,psci-1.0";
 169                 method = "smc";
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv8-timer";
 174                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 177                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 178         };
 179
 180         thermal_zones: thermal-zones {
 181                 soc_thermal: soc-thermal {
 182                         polling-delay-passive = <20>;
 183                         polling-delay = <1000>;
 184                         sustainable-power = <750>;
 185                         thermal-sensors = <&tsadc 0>;
 186
 187                         trips {
 188                                 threshold: trip-point-0 {
 189                                         temperature = <70000>;
 190                                         hysteresis = <2000>;
 191                                         type = "passive";
 192                                 };
 193
 194                                 target: trip-point-1 {
 195                                         temperature = <85000>;
 196                                         hysteresis = <2000>;
 197                                         type = "passive";
 198                                 };
 199
 200                                 soc_crit: soc-crit {
 201                                         temperature = <115000>;
 202                                         hysteresis = <2000>;
 203                                         type = "critical";
 204                                 };
 205                         };
 206
 207                         cooling-maps {
 208                                 map0 {
 209                                         trip = <&target>;
 210                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 211                                         contribution = <4096>;
 212                                 };
 213
 214                                 map1 {
 215                                         trip = <&target>;
 216                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 217                                         contribution = <4096>;
 218                                 };
 219                         };
 220                 };
 221
 222                 gpu_thermal: gpu-thermal {
 223                         polling-delay-passive = <100>; /* milliseconds */
 224                         polling-delay = <1000>; /* milliseconds */
 225                         thermal-sensors = <&tsadc 1>;
 226                 };
 227         };
 228
 229         xin24m: xin24m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <24000000>;
 233                 clock-output-names = "xin24m";
 234         };
 235
 236         pmu: power-management@ff000000 {
 237                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 238                 reg = <0x0 0xff000000 0x0 0x1000>;
 239
 240                 power: power-controller {
 241                         compatible = "rockchip,px30-power-controller";
 242                         #power-domain-cells = <1>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245
 246                         /* These power domains are grouped by VD_LOGIC */
 247                         power-domain@PX30_PD_USB {
 248                                 reg = <PX30_PD_USB>;
 249                                 clocks = <&cru HCLK_HOST>,
 250                                          <&cru HCLK_OTG>,
 251                                          <&cru SCLK_OTG_ADP>;
 252                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 253                                 #power-domain-cells = <0>;
 254                         };
 255                         power-domain@PX30_PD_SDCARD {
 256                                 reg = <PX30_PD_SDCARD>;
 257                                 clocks = <&cru HCLK_SDMMC>,
 258                                          <&cru SCLK_SDMMC>;
 259                                 pm_qos = <&qos_sdmmc>;
 260                                 #power-domain-cells = <0>;
 261                         };
 262                         power-domain@PX30_PD_GMAC {
 263                                 reg = <PX30_PD_GMAC>;
 264                                 clocks = <&cru ACLK_GMAC>,
 265                                          <&cru PCLK_GMAC>,
 266                                          <&cru SCLK_MAC_REF>,
 267                                          <&cru SCLK_GMAC_RX_TX>;
 268                                 pm_qos = <&qos_gmac>;
 269                                 #power-domain-cells = <0>;
 270                         };
 271                         power-domain@PX30_PD_MMC_NAND {
 272                                 reg = <PX30_PD_MMC_NAND>;
 273                                 clocks =  <&cru HCLK_NANDC>,
 274                                           <&cru HCLK_EMMC>,
 275                                           <&cru HCLK_SDIO>,
 276                                           <&cru HCLK_SFC>,
 277                                           <&cru SCLK_EMMC>,
 278                                           <&cru SCLK_NANDC>,
 279                                           <&cru SCLK_SDIO>,
 280                                           <&cru SCLK_SFC>;
 281                                 pm_qos = <&qos_emmc>, <&qos_nand>,
 282                                          <&qos_sdio>, <&qos_sfc>;
 283                                 #power-domain-cells = <0>;
 284                         };
 285                         power-domain@PX30_PD_VPU {
 286                                 reg = <PX30_PD_VPU>;
 287                                 clocks = <&cru ACLK_VPU>,
 288                                          <&cru HCLK_VPU>,
 289                                          <&cru SCLK_CORE_VPU>;
 290                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 291                                 #power-domain-cells = <0>;
 292                         };
 293                         power-domain@PX30_PD_VO {
 294                                 reg = <PX30_PD_VO>;
 295                                 clocks = <&cru ACLK_RGA>,
 296                                          <&cru ACLK_VOPB>,
 297                                          <&cru ACLK_VOPL>,
 298                                          <&cru DCLK_VOPB>,
 299                                          <&cru DCLK_VOPL>,
 300                                          <&cru HCLK_RGA>,
 301                                          <&cru HCLK_VOPB>,
 302                                          <&cru HCLK_VOPL>,
 303                                          <&cru PCLK_MIPI_DSI>,
 304                                          <&cru SCLK_RGA_CORE>,
 305                                          <&cru SCLK_VOPB_PWM>;
 306                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 307                                          <&qos_vop_m0>, <&qos_vop_m1>;
 308                                 #power-domain-cells = <0>;
 309                         };
 310                         power-domain@PX30_PD_VI {
 311                                 reg = <PX30_PD_VI>;
 312                                 clocks = <&cru ACLK_CIF>,
 313                                          <&cru ACLK_ISP>,
 314                                          <&cru HCLK_CIF>,
 315                                          <&cru HCLK_ISP>,
 316                                          <&cru SCLK_ISP>;
 317                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 318                                          <&qos_isp_wr>, <&qos_isp_m1>,
 319                                          <&qos_vip>;
 320                                 #power-domain-cells = <0>;
 321                         };
 322                         power-domain@PX30_PD_GPU {
 323                                 reg = <PX30_PD_GPU>;
 324                                 clocks = <&cru SCLK_GPU>;
 325                                 pm_qos = <&qos_gpu>;
 326                                 #power-domain-cells = <0>;
 327                         };
 328                 };
 329         };
 330
 331         pmugrf: syscon@ff010000 {
 332                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 333                 reg = <0x0 0xff010000 0x0 0x1000>;
 334                 #address-cells = <1>;
 335                 #size-cells = <1>;
 336
 337                 pmu_io_domains: io-domains {
 338                         compatible = "rockchip,px30-pmu-io-voltage-domain";
 339                         status = "disabled";
 340                 };
 341
 342                 reboot-mode {
 343                         compatible = "syscon-reboot-mode";
 344                         offset = <0x200>;
 345                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 346                         mode-fastboot = <BOOT_FASTBOOT>;
 347                         mode-loader = <BOOT_BL_DOWNLOAD>;
 348                         mode-normal = <BOOT_NORMAL>;
 349                         mode-recovery = <BOOT_RECOVERY>;
 350                 };
 351         };
 352
 353         uart0: serial@ff030000 {
 354                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 355                 reg = <0x0 0xff030000 0x0 0x100>;
 356                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 358                 clock-names = "baudclk", "apb_pclk";
 359                 dmas = <&dmac 0>, <&dmac 1>;
 360                 dma-names = "tx", "rx";
 361                 reg-shift = <2>;
 362                 reg-io-width = <4>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 365                 status = "disabled";
 366         };
 367
 368         i2s0_8ch: i2s@ff060000 {
 369                 compatible = "rockchip,px30-i2s-tdm";
 370                 reg = <0x0 0xff060000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
 373                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 374                 dmas = <&dmac 16>, <&dmac 17>;
 375                 dma-names = "tx", "rx";
 376                 rockchip,grf = <&grf>;
 377                 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
 378                 reset-names = "tx-m", "rx-m";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
 381                              &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
 382                              &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
 383                              &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
 384                              &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
 385                              &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
 386                 #sound-dai-cells = <0>;
 387                 status = "disabled";
 388         };
 389
 390         i2s1_2ch: i2s@ff070000 {
 391                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 392                 reg = <0x0 0xff070000 0x0 0x1000>;
 393                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 395                 clock-names = "i2s_clk", "i2s_hclk";
 396                 dmas = <&dmac 18>, <&dmac 19>;
 397                 dma-names = "tx", "rx";
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 400                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 401                 #sound-dai-cells = <0>;
 402                 status = "disabled";
 403         };
 404
 405         i2s2_2ch: i2s@ff080000 {
 406                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 407                 reg = <0x0 0xff080000 0x0 0x1000>;
 408                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 410                 clock-names = "i2s_clk", "i2s_hclk";
 411                 dmas = <&dmac 20>, <&dmac 21>;
 412                 dma-names = "tx", "rx";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 415                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 416                 #sound-dai-cells = <0>;
 417                 status = "disabled";
 418         };
 419
 420         gic: interrupt-controller@ff131000 {
 421                 compatible = "arm,gic-400";
 422                 #interrupt-cells = <3>;
 423                 #address-cells = <0>;
 424                 interrupt-controller;
 425                 reg = <0x0 0xff131000 0 0x1000>,
 426                       <0x0 0xff132000 0 0x2000>,
 427                       <0x0 0xff134000 0 0x2000>,
 428                       <0x0 0xff136000 0 0x2000>;
 429                 interrupts = <GIC_PPI 9
 430                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 431         };
 432
 433         grf: syscon@ff140000 {
 434                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 435                 reg = <0x0 0xff140000 0x0 0x1000>;
 436                 #address-cells = <1>;
 437                 #size-cells = <1>;
 438
 439                 io_domains: io-domains {
 440                         compatible = "rockchip,px30-io-voltage-domain";
 441                         status = "disabled";
 442                 };
 443
 444                 lvds: lvds {
 445                         compatible = "rockchip,px30-lvds";
 446                         phys = <&dsi_dphy>;
 447                         phy-names = "dphy";
 448                         rockchip,grf = <&grf>;
 449                         rockchip,output = "lvds";
 450                         status = "disabled";
 451
 452                         ports {
 453                                 #address-cells = <1>;
 454                                 #size-cells = <0>;
 455
 456                                 port@0 {
 457                                         reg = <0>;
 458                                         #address-cells = <1>;
 459                                         #size-cells = <0>;
 460
 461                                         lvds_vopb_in: endpoint@0 {
 462                                                 reg = <0>;
 463                                                 remote-endpoint = <&vopb_out_lvds>;
 464                                         };
 465
 466                                         lvds_vopl_in: endpoint@1 {
 467                                                 reg = <1>;
 468                                                 remote-endpoint = <&vopl_out_lvds>;
 469                                         };
 470                                 };
 471                         };
 472                 };
 473         };
 474
 475         uart1: serial@ff158000 {
 476                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 477                 reg = <0x0 0xff158000 0x0 0x100>;
 478                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 480                 clock-names = "baudclk", "apb_pclk";
 481                 dmas = <&dmac 2>, <&dmac 3>;
 482                 dma-names = "tx", "rx";
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 pinctrl-names = "default";
 486                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 487                 status = "disabled";
 488         };
 489
 490         uart2: serial@ff160000 {
 491                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 492                 reg = <0x0 0xff160000 0x0 0x100>;
 493                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 494                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 495                 clock-names = "baudclk", "apb_pclk";
 496                 dmas = <&dmac 4>, <&dmac 5>;
 497                 dma-names = "tx", "rx";
 498                 reg-shift = <2>;
 499                 reg-io-width = <4>;
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&uart2m0_xfer>;
 502                 status = "disabled";
 503         };
 504
 505         uart3: serial@ff168000 {
 506                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 507                 reg = <0x0 0xff168000 0x0 0x100>;
 508                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 509                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 510                 clock-names = "baudclk", "apb_pclk";
 511                 dmas = <&dmac 6>, <&dmac 7>;
 512                 dma-names = "tx", "rx";
 513                 reg-shift = <2>;
 514                 reg-io-width = <4>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 517                 status = "disabled";
 518         };
 519
 520         uart4: serial@ff170000 {
 521                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff170000 0x0 0x100>;
 523                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 dmas = <&dmac 8>, <&dmac 9>;
 527                 dma-names = "tx", "rx";
 528                 reg-shift = <2>;
 529                 reg-io-width = <4>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 532                 status = "disabled";
 533         };
 534
 535         uart5: serial@ff178000 {
 536                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 537                 reg = <0x0 0xff178000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 540                 clock-names = "baudclk", "apb_pclk";
 541                 dmas = <&dmac 10>, <&dmac 11>;
 542                 dma-names = "tx", "rx";
 543                 reg-shift = <2>;
 544                 reg-io-width = <4>;
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 547                 status = "disabled";
 548         };
 549
 550         i2c0: i2c@ff180000 {
 551                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 552                 reg = <0x0 0xff180000 0x0 0x1000>;
 553                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 554                 clock-names = "i2c", "pclk";
 555                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&i2c0_xfer>;
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 status = "disabled";
 561         };
 562
 563         i2c1: i2c@ff190000 {
 564                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 565                 reg = <0x0 0xff190000 0x0 0x1000>;
 566                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 567                 clock-names = "i2c", "pclk";
 568                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&i2c1_xfer>;
 571                 #address-cells = <1>;
 572                 #size-cells = <0>;
 573                 status = "disabled";
 574         };
 575
 576         i2c2: i2c@ff1a0000 {
 577                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 578                 reg = <0x0 0xff1a0000 0x0 0x1000>;
 579                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 580                 clock-names = "i2c", "pclk";
 581                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&i2c2_xfer>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 status = "disabled";
 587         };
 588
 589         i2c3: i2c@ff1b0000 {
 590                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 591                 reg = <0x0 0xff1b0000 0x0 0x1000>;
 592                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 593                 clock-names = "i2c", "pclk";
 594                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&i2c3_xfer>;
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 status = "disabled";
 600         };
 601
 602         spi0: spi@ff1d0000 {
 603                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 604                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 605                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 607                 clock-names = "spiclk", "apb_pclk";
 608                 dmas = <&dmac 12>, <&dmac 13>;
 609                 dma-names = "tx", "rx";
 610                 num-cs = <2>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         spi1: spi@ff1d8000 {
 619                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 620                 reg = <0x0 0xff1d8000 0x0 0x1000>;
 621                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 623                 clock-names = "spiclk", "apb_pclk";
 624                 dmas = <&dmac 14>, <&dmac 15>;
 625                 dma-names = "tx", "rx";
 626                 num-cs = <2>;
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 status = "disabled";
 632         };
 633
 634         wdt: watchdog@ff1e0000 {
 635                 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
 636                 reg = <0x0 0xff1e0000 0x0 0x100>;
 637                 clocks = <&cru PCLK_WDT_NS>;
 638                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 639                 status = "disabled";
 640         };
 641
 642         pwm0: pwm@ff200000 {
 643                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 644                 reg = <0x0 0xff200000 0x0 0x10>;
 645                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 646                 clock-names = "pwm", "pclk";
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&pwm0_pin>;
 649                 #pwm-cells = <3>;
 650                 status = "disabled";
 651         };
 652
 653         pwm1: pwm@ff200010 {
 654                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 655                 reg = <0x0 0xff200010 0x0 0x10>;
 656                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 657                 clock-names = "pwm", "pclk";
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&pwm1_pin>;
 660                 #pwm-cells = <3>;
 661                 status = "disabled";
 662         };
 663
 664         pwm2: pwm@ff200020 {
 665                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 666                 reg = <0x0 0xff200020 0x0 0x10>;
 667                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 668                 clock-names = "pwm", "pclk";
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&pwm2_pin>;
 671                 #pwm-cells = <3>;
 672                 status = "disabled";
 673         };
 674
 675         pwm3: pwm@ff200030 {
 676                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 677                 reg = <0x0 0xff200030 0x0 0x10>;
 678                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 679                 clock-names = "pwm", "pclk";
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&pwm3_pin>;
 682                 #pwm-cells = <3>;
 683                 status = "disabled";
 684         };
 685
 686         pwm4: pwm@ff208000 {
 687                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 688                 reg = <0x0 0xff208000 0x0 0x10>;
 689                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 690                 clock-names = "pwm", "pclk";
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&pwm4_pin>;
 693                 #pwm-cells = <3>;
 694                 status = "disabled";
 695         };
 696
 697         pwm5: pwm@ff208010 {
 698                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 699                 reg = <0x0 0xff208010 0x0 0x10>;
 700                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 701                 clock-names = "pwm", "pclk";
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&pwm5_pin>;
 704                 #pwm-cells = <3>;
 705                 status = "disabled";
 706         };
 707
 708         pwm6: pwm@ff208020 {
 709                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 710                 reg = <0x0 0xff208020 0x0 0x10>;
 711                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 712                 clock-names = "pwm", "pclk";
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&pwm6_pin>;
 715                 #pwm-cells = <3>;
 716                 status = "disabled";
 717         };
 718
 719         pwm7: pwm@ff208030 {
 720                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 721                 reg = <0x0 0xff208030 0x0 0x10>;
 722                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 723                 clock-names = "pwm", "pclk";
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&pwm7_pin>;
 726                 #pwm-cells = <3>;
 727                 status = "disabled";
 728         };
 729
 730         rktimer: timer@ff210000 {
 731                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 732                 reg = <0x0 0xff210000 0x0 0x1000>;
 733                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 734                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 735                 clock-names = "pclk", "timer";
 736         };
 737
 738         dmac: dma-controller@ff240000 {
 739                 compatible = "arm,pl330", "arm,primecell";
 740                 reg = <0x0 0xff240000 0x0 0x4000>;
 741                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 742                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 743                 arm,pl330-periph-burst;
 744                 clocks = <&cru ACLK_DMAC>;
 745                 clock-names = "apb_pclk";
 746                 #dma-cells = <1>;
 747         };
 748
 749         tsadc: tsadc@ff280000 {
 750                 compatible = "rockchip,px30-tsadc";
 751                 reg = <0x0 0xff280000 0x0 0x100>;
 752                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 753                 assigned-clocks = <&cru SCLK_TSADC>;
 754                 assigned-clock-rates = <50000>;
 755                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 756                 clock-names = "tsadc", "apb_pclk";
 757                 resets = <&cru SRST_TSADC>;
 758                 reset-names = "tsadc-apb";
 759                 rockchip,grf = <&grf>;
 760                 rockchip,hw-tshut-temp = <120000>;
 761                 pinctrl-names = "init", "default", "sleep";
 762                 pinctrl-0 = <&tsadc_otp_pin>;
 763                 pinctrl-1 = <&tsadc_otp_out>;
 764                 pinctrl-2 = <&tsadc_otp_pin>;
 765                 #thermal-sensor-cells = <1>;
 766                 status = "disabled";
 767         };
 768
 769         saradc: saradc@ff288000 {
 770                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 771                 reg = <0x0 0xff288000 0x0 0x100>;
 772                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 773                 #io-channel-cells = <1>;
 774                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 775                 clock-names = "saradc", "apb_pclk";
 776                 resets = <&cru SRST_SARADC_P>;
 777                 reset-names = "saradc-apb";
 778                 status = "disabled";
 779         };
 780
 781         otp: nvmem@ff290000 {
 782                 compatible = "rockchip,px30-otp";
 783                 reg = <0x0 0xff290000 0x0 0x4000>;
 784                 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
 785                          <&cru PCLK_OTP_PHY>;
 786                 clock-names = "otp", "apb_pclk", "phy";
 787                 resets = <&cru SRST_OTP_PHY>;
 788                 reset-names = "phy";
 789                 #address-cells = <1>;
 790                 #size-cells = <1>;
 791
 792                 /* Data cells */
 793                 cpu_id: id@7 {
 794                         reg = <0x07 0x10>;
 795                 };
 796                 cpu_leakage: cpu-leakage@17 {
 797                         reg = <0x17 0x1>;
 798                 };
 799                 performance: performance@1e {
 800                         reg = <0x1e 0x1>;
 801                         bits = <4 3>;
 802                 };
 803         };
 804
 805         cru: clock-controller@ff2b0000 {
 806                 compatible = "rockchip,px30-cru";
 807                 reg = <0x0 0xff2b0000 0x0 0x1000>;
 808                 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
 809                 clock-names = "xin24m", "gpll";
 810                 rockchip,grf = <&grf>;
 811                 #clock-cells = <1>;
 812                 #reset-cells = <1>;
 813
 814                 assigned-clocks = <&cru PLL_NPLL>,
 815                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 816                         <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
 817                         <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
 818
 819                 assigned-clock-rates = <1188000000>,
 820                         <200000000>, <200000000>,
 821                         <150000000>, <150000000>,
 822                         <100000000>, <200000000>;
 823         };
 824
 825         pmucru: clock-controller@ff2bc000 {
 826                 compatible = "rockchip,px30-pmucru";
 827                 reg = <0x0 0xff2bc000 0x0 0x1000>;
 828                 clocks = <&xin24m>;
 829                 clock-names = "xin24m";
 830                 rockchip,grf = <&grf>;
 831                 #clock-cells = <1>;
 832                 #reset-cells = <1>;
 833
 834                 assigned-clocks =
 835                         <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
 836                         <&pmucru SCLK_WIFI_PMU>;
 837                 assigned-clock-rates =
 838                         <1200000000>, <100000000>,
 839                         <26000000>;
 840         };
 841
 842         usb2phy_grf: syscon@ff2c0000 {
 843                 compatible = "rockchip,px30-usb2phy-grf", "syscon",
 844                              "simple-mfd";
 845                 reg = <0x0 0xff2c0000 0x0 0x10000>;
 846                 #address-cells = <1>;
 847                 #size-cells = <1>;
 848
 849                 u2phy: usb2phy@100 {
 850                         compatible = "rockchip,px30-usb2phy";
 851                         reg = <0x100 0x20>;
 852                         clocks = <&pmucru SCLK_USBPHY_REF>;
 853                         clock-names = "phyclk";
 854                         #clock-cells = <0>;
 855                         assigned-clocks = <&cru USB480M>;
 856                         assigned-clock-parents = <&u2phy>;
 857                         clock-output-names = "usb480m_phy";
 858                         status = "disabled";
 859
 860                         u2phy_host: host-port {
 861                                 #phy-cells = <0>;
 862                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 863                                 interrupt-names = "linestate";
 864                                 status = "disabled";
 865                         };
 866
 867                         u2phy_otg: otg-port {
 868                                 #phy-cells = <0>;
 869                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 870                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 871                                              <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 872                                 interrupt-names = "otg-bvalid", "otg-id",
 873                                                   "linestate";
 874                                 status = "disabled";
 875                         };
 876                 };
 877         };
 878
 879         dsi_dphy: phy@ff2e0000 {
 880                 compatible = "rockchip,px30-dsi-dphy";
 881                 reg = <0x0 0xff2e0000 0x0 0x10000>;
 882                 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
 883                 clock-names = "ref", "pclk";
 884                 resets = <&cru SRST_MIPIDSIPHY_P>;
 885                 reset-names = "apb";
 886                 #phy-cells = <0>;
 887                 power-domains = <&power PX30_PD_VO>;
 888                 status = "disabled";
 889         };
 890
 891         csi_dphy: phy@ff2f0000 {
 892                 compatible = "rockchip,px30-csi-dphy";
 893                 reg = <0x0 0xff2f0000 0x0 0x4000>;
 894                 clocks = <&cru PCLK_MIPICSIPHY>;
 895                 clock-names = "pclk";
 896                 #phy-cells = <0>;
 897                 power-domains = <&power PX30_PD_VI>;
 898                 resets = <&cru SRST_MIPICSIPHY_P>;
 899                 reset-names = "apb";
 900                 rockchip,grf = <&grf>;
 901                 status = "disabled";
 902         };
 903
 904         usb20_otg: usb@ff300000 {
 905                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 906                              "snps,dwc2";
 907                 reg = <0x0 0xff300000 0x0 0x40000>;
 908                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 909                 clocks = <&cru HCLK_OTG>;
 910                 clock-names = "otg";
 911                 dr_mode = "otg";
 912                 g-np-tx-fifo-size = <16>;
 913                 g-rx-fifo-size = <280>;
 914                 g-tx-fifo-size = <256 128 128 64 32 16>;
 915                 phys = <&u2phy_otg>;
 916                 phy-names = "usb2-phy";
 917                 power-domains = <&power PX30_PD_USB>;
 918                 status = "disabled";
 919         };
 920
 921         usb_host0_ehci: usb@ff340000 {
 922                 compatible = "generic-ehci";
 923                 reg = <0x0 0xff340000 0x0 0x10000>;
 924                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 925                 clocks = <&cru HCLK_HOST>;
 926                 phys = <&u2phy_host>;
 927                 phy-names = "usb";
 928                 power-domains = <&power PX30_PD_USB>;
 929                 status = "disabled";
 930         };
 931
 932         usb_host0_ohci: usb@ff350000 {
 933                 compatible = "generic-ohci";
 934                 reg = <0x0 0xff350000 0x0 0x10000>;
 935                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 936                 clocks = <&cru HCLK_HOST>;
 937                 phys = <&u2phy_host>;
 938                 phy-names = "usb";
 939                 power-domains = <&power PX30_PD_USB>;
 940                 status = "disabled";
 941         };
 942
 943         gmac: ethernet@ff360000 {
 944                 compatible = "rockchip,px30-gmac";
 945                 reg = <0x0 0xff360000 0x0 0x10000>;
 946                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 947                 interrupt-names = "macirq";
 948                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 949                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 950                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 951                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 952                 clock-names = "stmmaceth", "mac_clk_rx",
 953                               "mac_clk_tx", "clk_mac_ref",
 954                               "clk_mac_refout", "aclk_mac",
 955                               "pclk_mac", "clk_mac_speed";
 956                 rockchip,grf = <&grf>;
 957                 phy-mode = "rmii";
 958                 pinctrl-names = "default";
 959                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 960                 power-domains = <&power PX30_PD_GMAC>;
 961                 resets = <&cru SRST_GMAC_A>;
 962                 reset-names = "stmmaceth";
 963                 status = "disabled";
 964         };
 965
 966         sdmmc: mmc@ff370000 {
 967                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 968                 reg = <0x0 0xff370000 0x0 0x4000>;
 969                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 970                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 971                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 972                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 973                 bus-width = <4>;
 974                 fifo-depth = <0x100>;
 975                 max-frequency = <150000000>;
 976                 pinctrl-names = "default";
 977                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 978                 power-domains = <&power PX30_PD_SDCARD>;
 979                 status = "disabled";
 980         };
 981
 982         sdio: mmc@ff380000 {
 983                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 984                 reg = <0x0 0xff380000 0x0 0x4000>;
 985                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 986                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 987                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 988                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 989                 bus-width = <4>;
 990                 fifo-depth = <0x100>;
 991                 max-frequency = <150000000>;
 992                 pinctrl-names = "default";
 993                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 994                 power-domains = <&power PX30_PD_MMC_NAND>;
 995                 status = "disabled";
 996         };
 997
 998         emmc: mmc@ff390000 {
 999                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1000                 reg = <0x0 0xff390000 0x0 0x4000>;
1001                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1002                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1003                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1004                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1005                 bus-width = <8>;
1006                 fifo-depth = <0x100>;
1007                 max-frequency = <150000000>;
1008                 pinctrl-names = "default";
1009                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1010                 power-domains = <&power PX30_PD_MMC_NAND>;
1011                 status = "disabled";
1012         };
1013
1014         sfc: spi@ff3a0000 {
1015                 compatible = "rockchip,sfc";
1016                 reg = <0x0 0xff3a0000 0x0 0x4000>;
1017                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1019                 clock-names = "clk_sfc", "hclk_sfc";
1020                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1021                 pinctrl-names = "default";
1022                 power-domains = <&power PX30_PD_MMC_NAND>;
1023                 status = "disabled";
1024         };
1025
1026         nfc: nand-controller@ff3b0000 {
1027                 compatible = "rockchip,px30-nfc";
1028                 reg = <0x0 0xff3b0000 0x0 0x4000>;
1029                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1030                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1031                 clock-names = "ahb", "nfc";
1032                 assigned-clocks = <&cru SCLK_NANDC>;
1033                 assigned-clock-rates = <150000000>;
1034                 pinctrl-names = "default";
1035                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1036                              &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1037                 power-domains = <&power PX30_PD_MMC_NAND>;
1038                 status = "disabled";
1039         };
1040
1041         gpu_opp_table: opp-table-1 {
1042                 compatible = "operating-points-v2";
1043
1044                 opp-200000000 {
1045                         opp-hz = /bits/ 64 <200000000>;
1046                         opp-microvolt = <950000>;
1047                 };
1048                 opp-300000000 {
1049                         opp-hz = /bits/ 64 <300000000>;
1050                         opp-microvolt = <975000>;
1051                 };
1052                 opp-400000000 {
1053                         opp-hz = /bits/ 64 <400000000>;
1054                         opp-microvolt = <1050000>;
1055                 };
1056                 opp-480000000 {
1057                         opp-hz = /bits/ 64 <480000000>;
1058                         opp-microvolt = <1125000>;
1059                 };
1060         };
1061
1062         gpu: gpu@ff400000 {
1063                 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1064                 reg = <0x0 0xff400000 0x0 0x4000>;
1065                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1066                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1067                              <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1068                 interrupt-names = "job", "mmu", "gpu";
1069                 clocks = <&cru SCLK_GPU>;
1070                 #cooling-cells = <2>;
1071                 power-domains = <&power PX30_PD_GPU>;
1072                 operating-points-v2 = <&gpu_opp_table>;
1073                 status = "disabled";
1074         };
1075
1076         vpu: video-codec@ff442000 {
1077                 compatible = "rockchip,px30-vpu";
1078                 reg = <0x0 0xff442000 0x0 0x800>;
1079                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1080                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1081                 interrupt-names = "vepu", "vdpu";
1082                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1083                 clock-names = "aclk", "hclk";
1084                 iommus = <&vpu_mmu>;
1085                 power-domains = <&power PX30_PD_VPU>;
1086         };
1087
1088         vpu_mmu: iommu@ff442800 {
1089                 compatible = "rockchip,iommu";
1090                 reg = <0x0 0xff442800 0x0 0x100>;
1091                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1092                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1093                 clock-names = "aclk", "iface";
1094                 #iommu-cells = <0>;
1095                 power-domains = <&power PX30_PD_VPU>;
1096         };
1097
1098         dsi: dsi@ff450000 {
1099                 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1100                 reg = <0x0 0xff450000 0x0 0x10000>;
1101                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1102                 clocks = <&cru PCLK_MIPI_DSI>;
1103                 clock-names = "pclk";
1104                 phys = <&dsi_dphy>;
1105                 phy-names = "dphy";
1106                 power-domains = <&power PX30_PD_VO>;
1107                 resets = <&cru SRST_MIPIDSI_HOST_P>;
1108                 reset-names = "apb";
1109                 rockchip,grf = <&grf>;
1110                 #address-cells = <1>;
1111                 #size-cells = <0>;
1112                 status = "disabled";
1113
1114                 ports {
1115                         #address-cells = <1>;
1116                         #size-cells = <0>;
1117
1118                         port@0 {
1119                                 reg = <0>;
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122
1123                                 dsi_in_vopb: endpoint@0 {
1124                                         reg = <0>;
1125                                         remote-endpoint = <&vopb_out_dsi>;
1126                                 };
1127
1128                                 dsi_in_vopl: endpoint@1 {
1129                                         reg = <1>;
1130                                         remote-endpoint = <&vopl_out_dsi>;
1131                                 };
1132                         };
1133                 };
1134         };
1135
1136         vopb: vop@ff460000 {
1137                 compatible = "rockchip,px30-vop-big";
1138                 reg = <0x0 0xff460000 0x0 0xefc>;
1139                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1140                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1141                          <&cru HCLK_VOPB>;
1142                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1143                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1144                 reset-names = "axi", "ahb", "dclk";
1145                 iommus = <&vopb_mmu>;
1146                 power-domains = <&power PX30_PD_VO>;
1147                 status = "disabled";
1148
1149                 vopb_out: port {
1150                         #address-cells = <1>;
1151                         #size-cells = <0>;
1152
1153                         vopb_out_dsi: endpoint@0 {
1154                                 reg = <0>;
1155                                 remote-endpoint = <&dsi_in_vopb>;
1156                         };
1157
1158                         vopb_out_lvds: endpoint@1 {
1159                                 reg = <1>;
1160                                 remote-endpoint = <&lvds_vopb_in>;
1161                         };
1162                 };
1163         };
1164
1165         vopb_mmu: iommu@ff460f00 {
1166                 compatible = "rockchip,iommu";
1167                 reg = <0x0 0xff460f00 0x0 0x100>;
1168                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1169                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1170                 clock-names = "aclk", "iface";
1171                 power-domains = <&power PX30_PD_VO>;
1172                 #iommu-cells = <0>;
1173                 status = "disabled";
1174         };
1175
1176         vopl: vop@ff470000 {
1177                 compatible = "rockchip,px30-vop-lit";
1178                 reg = <0x0 0xff470000 0x0 0xefc>;
1179                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1180                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1181                          <&cru HCLK_VOPL>;
1182                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1183                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1184                 reset-names = "axi", "ahb", "dclk";
1185                 iommus = <&vopl_mmu>;
1186                 power-domains = <&power PX30_PD_VO>;
1187                 status = "disabled";
1188
1189                 vopl_out: port {
1190                         #address-cells = <1>;
1191                         #size-cells = <0>;
1192
1193                         vopl_out_dsi: endpoint@0 {
1194                                 reg = <0>;
1195                                 remote-endpoint = <&dsi_in_vopl>;
1196                         };
1197
1198                         vopl_out_lvds: endpoint@1 {
1199                                 reg = <1>;
1200                                 remote-endpoint = <&lvds_vopl_in>;
1201                         };
1202                 };
1203         };
1204
1205         vopl_mmu: iommu@ff470f00 {
1206                 compatible = "rockchip,iommu";
1207                 reg = <0x0 0xff470f00 0x0 0x100>;
1208                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1209                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1210                 clock-names = "aclk", "iface";
1211                 power-domains = <&power PX30_PD_VO>;
1212                 #iommu-cells = <0>;
1213                 status = "disabled";
1214         };
1215
1216         isp: isp@ff4a0000 {
1217                 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1218                 reg = <0x0 0xff4a0000 0x0 0x8000>;
1219                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1220                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1221                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1222                 interrupt-names = "isp", "mi", "mipi";
1223                 clocks = <&cru SCLK_ISP>,
1224                          <&cru ACLK_ISP>,
1225                          <&cru HCLK_ISP>,
1226                          <&cru PCLK_ISP>;
1227                 clock-names = "isp", "aclk", "hclk", "pclk";
1228                 iommus = <&isp_mmu>;
1229                 phys = <&csi_dphy>;
1230                 phy-names = "dphy";
1231                 power-domains = <&power PX30_PD_VI>;
1232                 status = "disabled";
1233
1234                 ports {
1235                         #address-cells = <1>;
1236                         #size-cells = <0>;
1237
1238                         port@0 {
1239                                 reg = <0>;
1240                                 #address-cells = <1>;
1241                                 #size-cells = <0>;
1242                         };
1243                 };
1244         };
1245
1246         isp_mmu: iommu@ff4a8000 {
1247                 compatible = "rockchip,iommu";
1248                 reg = <0x0 0xff4a8000 0x0 0x100>;
1249                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1250                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1251                 clock-names = "aclk", "iface";
1252                 power-domains = <&power PX30_PD_VI>;
1253                 rockchip,disable-mmu-reset;
1254                 #iommu-cells = <0>;
1255         };
1256
1257         qos_gmac: qos@ff518000 {
1258                 compatible = "rockchip,px30-qos", "syscon";
1259                 reg = <0x0 0xff518000 0x0 0x20>;
1260         };
1261
1262         qos_gpu: qos@ff520000 {
1263                 compatible = "rockchip,px30-qos", "syscon";
1264                 reg = <0x0 0xff520000 0x0 0x20>;
1265         };
1266
1267         qos_sdmmc: qos@ff52c000 {
1268                 compatible = "rockchip,px30-qos", "syscon";
1269                 reg = <0x0 0xff52c000 0x0 0x20>;
1270         };
1271
1272         qos_emmc: qos@ff538000 {
1273                 compatible = "rockchip,px30-qos", "syscon";
1274                 reg = <0x0 0xff538000 0x0 0x20>;
1275         };
1276
1277         qos_nand: qos@ff538080 {
1278                 compatible = "rockchip,px30-qos", "syscon";
1279                 reg = <0x0 0xff538080 0x0 0x20>;
1280         };
1281
1282         qos_sdio: qos@ff538100 {
1283                 compatible = "rockchip,px30-qos", "syscon";
1284                 reg = <0x0 0xff538100 0x0 0x20>;
1285         };
1286
1287         qos_sfc: qos@ff538180 {
1288                 compatible = "rockchip,px30-qos", "syscon";
1289                 reg = <0x0 0xff538180 0x0 0x20>;
1290         };
1291
1292         qos_usb_host: qos@ff540000 {
1293                 compatible = "rockchip,px30-qos", "syscon";
1294                 reg = <0x0 0xff540000 0x0 0x20>;
1295         };
1296
1297         qos_usb_otg: qos@ff540080 {
1298                 compatible = "rockchip,px30-qos", "syscon";
1299                 reg = <0x0 0xff540080 0x0 0x20>;
1300         };
1301
1302         qos_isp_128: qos@ff548000 {
1303                 compatible = "rockchip,px30-qos", "syscon";
1304                 reg = <0x0 0xff548000 0x0 0x20>;
1305         };
1306
1307         qos_isp_rd: qos@ff548080 {
1308                 compatible = "rockchip,px30-qos", "syscon";
1309                 reg = <0x0 0xff548080 0x0 0x20>;
1310         };
1311
1312         qos_isp_wr: qos@ff548100 {
1313                 compatible = "rockchip,px30-qos", "syscon";
1314                 reg = <0x0 0xff548100 0x0 0x20>;
1315         };
1316
1317         qos_isp_m1: qos@ff548180 {
1318                 compatible = "rockchip,px30-qos", "syscon";
1319                 reg = <0x0 0xff548180 0x0 0x20>;
1320         };
1321
1322         qos_vip: qos@ff548200 {
1323                 compatible = "rockchip,px30-qos", "syscon";
1324                 reg = <0x0 0xff548200 0x0 0x20>;
1325         };
1326
1327         qos_rga_rd: qos@ff550000 {
1328                 compatible = "rockchip,px30-qos", "syscon";
1329                 reg = <0x0 0xff550000 0x0 0x20>;
1330         };
1331
1332         qos_rga_wr: qos@ff550080 {
1333                 compatible = "rockchip,px30-qos", "syscon";
1334                 reg = <0x0 0xff550080 0x0 0x20>;
1335         };
1336
1337         qos_vop_m0: qos@ff550100 {
1338                 compatible = "rockchip,px30-qos", "syscon";
1339                 reg = <0x0 0xff550100 0x0 0x20>;
1340         };
1341
1342         qos_vop_m1: qos@ff550180 {
1343                 compatible = "rockchip,px30-qos", "syscon";
1344                 reg = <0x0 0xff550180 0x0 0x20>;
1345         };
1346
1347         qos_vpu: qos@ff558000 {
1348                 compatible = "rockchip,px30-qos", "syscon";
1349                 reg = <0x0 0xff558000 0x0 0x20>;
1350         };
1351
1352         qos_vpu_r128: qos@ff558080 {
1353                 compatible = "rockchip,px30-qos", "syscon";
1354                 reg = <0x0 0xff558080 0x0 0x20>;
1355         };
1356
1357         pinctrl: pinctrl {
1358                 compatible = "rockchip,px30-pinctrl";
1359                 rockchip,grf = <&grf>;
1360                 rockchip,pmu = <&pmugrf>;
1361                 #address-cells = <2>;
1362                 #size-cells = <2>;
1363                 ranges;
1364
1365                 gpio0: gpio@ff040000 {
1366                         compatible = "rockchip,gpio-bank";
1367                         reg = <0x0 0xff040000 0x0 0x100>;
1368                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1369                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1370                         gpio-controller;
1371                         #gpio-cells = <2>;
1372
1373                         interrupt-controller;
1374                         #interrupt-cells = <2>;
1375                 };
1376
1377                 gpio1: gpio@ff250000 {
1378                         compatible = "rockchip,gpio-bank";
1379                         reg = <0x0 0xff250000 0x0 0x100>;
1380                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1381                         clocks = <&cru PCLK_GPIO1>;
1382                         gpio-controller;
1383                         #gpio-cells = <2>;
1384
1385                         interrupt-controller;
1386                         #interrupt-cells = <2>;
1387                 };
1388
1389                 gpio2: gpio@ff260000 {
1390                         compatible = "rockchip,gpio-bank";
1391                         reg = <0x0 0xff260000 0x0 0x100>;
1392                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1393                         clocks = <&cru PCLK_GPIO2>;
1394                         gpio-controller;
1395                         #gpio-cells = <2>;
1396
1397                         interrupt-controller;
1398                         #interrupt-cells = <2>;
1399                 };
1400
1401                 gpio3: gpio@ff270000 {
1402                         compatible = "rockchip,gpio-bank";
1403                         reg = <0x0 0xff270000 0x0 0x100>;
1404                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1405                         clocks = <&cru PCLK_GPIO3>;
1406                         gpio-controller;
1407                         #gpio-cells = <2>;
1408
1409                         interrupt-controller;
1410                         #interrupt-cells = <2>;
1411                 };
1412
1413                 pcfg_pull_up: pcfg-pull-up {
1414                         bias-pull-up;
1415                 };
1416
1417                 pcfg_pull_down: pcfg-pull-down {
1418                         bias-pull-down;
1419                 };
1420
1421                 pcfg_pull_none: pcfg-pull-none {
1422                         bias-disable;
1423                 };
1424
1425                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1426                         bias-disable;
1427                         drive-strength = <2>;
1428                 };
1429
1430                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1431                         bias-pull-up;
1432                         drive-strength = <2>;
1433                 };
1434
1435                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1436                         bias-pull-up;
1437                         drive-strength = <4>;
1438                 };
1439
1440                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1441                         bias-disable;
1442                         drive-strength = <4>;
1443                 };
1444
1445                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1446                         bias-pull-down;
1447                         drive-strength = <4>;
1448                 };
1449
1450                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1451                         bias-disable;
1452                         drive-strength = <8>;
1453                 };
1454
1455                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1456                         bias-pull-up;
1457                         drive-strength = <8>;
1458                 };
1459
1460                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1461                         bias-disable;
1462                         drive-strength = <12>;
1463                 };
1464
1465                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1466                         bias-pull-up;
1467                         drive-strength = <12>;
1468                 };
1469
1470                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1471                         bias-disable;
1472                         input-schmitt-enable;
1473                 };
1474
1475                 pcfg_output_high: pcfg-output-high {
1476                         output-high;
1477                 };
1478
1479                 pcfg_output_low: pcfg-output-low {
1480                         output-low;
1481                 };
1482
1483                 pcfg_input_high: pcfg-input-high {
1484                         bias-pull-up;
1485                         input-enable;
1486                 };
1487
1488                 pcfg_input: pcfg-input {
1489                         input-enable;
1490                 };
1491
1492                 i2c0 {
1493                         i2c0_xfer: i2c0-xfer {
1494                                 rockchip,pins =
1495                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1496                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1497                         };
1498                 };
1499
1500                 i2c1 {
1501                         i2c1_xfer: i2c1-xfer {
1502                                 rockchip,pins =
1503                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1504                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1505                         };
1506                 };
1507
1508                 i2c2 {
1509                         i2c2_xfer: i2c2-xfer {
1510                                 rockchip,pins =
1511                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1512                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1513                         };
1514                 };
1515
1516                 i2c3 {
1517                         i2c3_xfer: i2c3-xfer {
1518                                 rockchip,pins =
1519                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1520                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1521                         };
1522                 };
1523
1524                 tsadc {
1525                         tsadc_otp_pin: tsadc-otp-pin {
1526                                 rockchip,pins =
1527                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1528                         };
1529
1530                         tsadc_otp_out: tsadc-otp-out {
1531                                 rockchip,pins =
1532                                         <0 RK_PA6 1 &pcfg_pull_none>;
1533                         };
1534                 };
1535
1536                 uart0 {
1537                         uart0_xfer: uart0-xfer {
1538                                 rockchip,pins =
1539                                         <0 RK_PB2 1 &pcfg_pull_up>,
1540                                         <0 RK_PB3 1 &pcfg_pull_up>;
1541                         };
1542
1543                         uart0_cts: uart0-cts {
1544                                 rockchip,pins =
1545                                         <0 RK_PB4 1 &pcfg_pull_none>;
1546                         };
1547
1548                         uart0_rts: uart0-rts {
1549                                 rockchip,pins =
1550                                         <0 RK_PB5 1 &pcfg_pull_none>;
1551                         };
1552                 };
1553
1554                 uart1 {
1555                         uart1_xfer: uart1-xfer {
1556                                 rockchip,pins =
1557                                         <1 RK_PC1 1 &pcfg_pull_up>,
1558                                         <1 RK_PC0 1 &pcfg_pull_up>;
1559                         };
1560
1561                         uart1_cts: uart1-cts {
1562                                 rockchip,pins =
1563                                         <1 RK_PC2 1 &pcfg_pull_none>;
1564                         };
1565
1566                         uart1_rts: uart1-rts {
1567                                 rockchip,pins =
1568                                         <1 RK_PC3 1 &pcfg_pull_none>;
1569                         };
1570                 };
1571
1572                 uart2-m0 {
1573                         uart2m0_xfer: uart2m0-xfer {
1574                                 rockchip,pins =
1575                                         <1 RK_PD2 2 &pcfg_pull_up>,
1576                                         <1 RK_PD3 2 &pcfg_pull_up>;
1577                         };
1578                 };
1579
1580                 uart2-m1 {
1581                         uart2m1_xfer: uart2m1-xfer {
1582                                 rockchip,pins =
1583                                         <2 RK_PB4 2 &pcfg_pull_up>,
1584                                         <2 RK_PB6 2 &pcfg_pull_up>;
1585                         };
1586                 };
1587
1588                 uart3-m0 {
1589                         uart3m0_xfer: uart3m0-xfer {
1590                                 rockchip,pins =
1591                                         <0 RK_PC0 2 &pcfg_pull_up>,
1592                                         <0 RK_PC1 2 &pcfg_pull_up>;
1593                         };
1594
1595                         uart3m0_cts: uart3m0-cts {
1596                                 rockchip,pins =
1597                                         <0 RK_PC2 2 &pcfg_pull_none>;
1598                         };
1599
1600                         uart3m0_rts: uart3m0-rts {
1601                                 rockchip,pins =
1602                                         <0 RK_PC3 2 &pcfg_pull_none>;
1603                         };
1604                 };
1605
1606                 uart3-m1 {
1607                         uart3m1_xfer: uart3m1-xfer {
1608                                 rockchip,pins =
1609                                         <1 RK_PB6 2 &pcfg_pull_up>,
1610                                         <1 RK_PB7 2 &pcfg_pull_up>;
1611                         };
1612
1613                         uart3m1_cts: uart3m1-cts {
1614                                 rockchip,pins =
1615                                         <1 RK_PB4 2 &pcfg_pull_none>;
1616                         };
1617
1618                         uart3m1_rts: uart3m1-rts {
1619                                 rockchip,pins =
1620                                         <1 RK_PB5 2 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 uart4 {
1625                         uart4_xfer: uart4-xfer {
1626                                 rockchip,pins =
1627                                         <1 RK_PD4 2 &pcfg_pull_up>,
1628                                         <1 RK_PD5 2 &pcfg_pull_up>;
1629                         };
1630
1631                         uart4_cts: uart4-cts {
1632                                 rockchip,pins =
1633                                         <1 RK_PD6 2 &pcfg_pull_none>;
1634                         };
1635
1636                         uart4_rts: uart4-rts {
1637                                 rockchip,pins =
1638                                         <1 RK_PD7 2 &pcfg_pull_none>;
1639                         };
1640                 };
1641
1642                 uart5 {
1643                         uart5_xfer: uart5-xfer {
1644                                 rockchip,pins =
1645                                         <3 RK_PA2 4 &pcfg_pull_up>,
1646                                         <3 RK_PA1 4 &pcfg_pull_up>;
1647                         };
1648
1649                         uart5_cts: uart5-cts {
1650                                 rockchip,pins =
1651                                         <3 RK_PA3 4 &pcfg_pull_none>;
1652                         };
1653
1654                         uart5_rts: uart5-rts {
1655                                 rockchip,pins =
1656                                         <3 RK_PA5 4 &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 spi0 {
1661                         spi0_clk: spi0-clk {
1662                                 rockchip,pins =
1663                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1664                         };
1665
1666                         spi0_csn: spi0-csn {
1667                                 rockchip,pins =
1668                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1669                         };
1670
1671                         spi0_miso: spi0-miso {
1672                                 rockchip,pins =
1673                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1674                         };
1675
1676                         spi0_mosi: spi0-mosi {
1677                                 rockchip,pins =
1678                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1679                         };
1680
1681                         spi0_clk_hs: spi0-clk-hs {
1682                                 rockchip,pins =
1683                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1684                         };
1685
1686                         spi0_miso_hs: spi0-miso-hs {
1687                                 rockchip,pins =
1688                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1689                         };
1690
1691                         spi0_mosi_hs: spi0-mosi-hs {
1692                                 rockchip,pins =
1693                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1694                         };
1695                 };
1696
1697                 spi1 {
1698                         spi1_clk: spi1-clk {
1699                                 rockchip,pins =
1700                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1701                         };
1702
1703                         spi1_csn0: spi1-csn0 {
1704                                 rockchip,pins =
1705                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1706                         };
1707
1708                         spi1_csn1: spi1-csn1 {
1709                                 rockchip,pins =
1710                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1711                         };
1712
1713                         spi1_miso: spi1-miso {
1714                                 rockchip,pins =
1715                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1716                         };
1717
1718                         spi1_mosi: spi1-mosi {
1719                                 rockchip,pins =
1720                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1721                         };
1722
1723                         spi1_clk_hs: spi1-clk-hs {
1724                                 rockchip,pins =
1725                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1726                         };
1727
1728                         spi1_miso_hs: spi1-miso-hs {
1729                                 rockchip,pins =
1730                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1731                         };
1732
1733                         spi1_mosi_hs: spi1-mosi-hs {
1734                                 rockchip,pins =
1735                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1736                         };
1737                 };
1738
1739                 pdm {
1740                         pdm_clk0m0: pdm-clk0m0 {
1741                                 rockchip,pins =
1742                                         <3 RK_PC6 2 &pcfg_pull_none>;
1743                         };
1744
1745                         pdm_clk0m1: pdm-clk0m1 {
1746                                 rockchip,pins =
1747                                         <2 RK_PC6 1 &pcfg_pull_none>;
1748                         };
1749
1750                         pdm_clk1: pdm-clk1 {
1751                                 rockchip,pins =
1752                                         <3 RK_PC7 2 &pcfg_pull_none>;
1753                         };
1754
1755                         pdm_sdi0m0: pdm-sdi0m0 {
1756                                 rockchip,pins =
1757                                         <3 RK_PD3 2 &pcfg_pull_none>;
1758                         };
1759
1760                         pdm_sdi0m1: pdm-sdi0m1 {
1761                                 rockchip,pins =
1762                                         <2 RK_PC5 2 &pcfg_pull_none>;
1763                         };
1764
1765                         pdm_sdi1: pdm-sdi1 {
1766                                 rockchip,pins =
1767                                         <3 RK_PD0 2 &pcfg_pull_none>;
1768                         };
1769
1770                         pdm_sdi2: pdm-sdi2 {
1771                                 rockchip,pins =
1772                                         <3 RK_PD1 2 &pcfg_pull_none>;
1773                         };
1774
1775                         pdm_sdi3: pdm-sdi3 {
1776                                 rockchip,pins =
1777                                         <3 RK_PD2 2 &pcfg_pull_none>;
1778                         };
1779
1780                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1781                                 rockchip,pins =
1782                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1783                         };
1784
1785                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1786                                 rockchip,pins =
1787                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1788                         };
1789
1790                         pdm_clk1_sleep: pdm-clk1-sleep {
1791                                 rockchip,pins =
1792                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1793                         };
1794
1795                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1796                                 rockchip,pins =
1797                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1798                         };
1799
1800                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1801                                 rockchip,pins =
1802                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1803                         };
1804
1805                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1806                                 rockchip,pins =
1807                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1808                         };
1809
1810                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1811                                 rockchip,pins =
1812                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1813                         };
1814
1815                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1816                                 rockchip,pins =
1817                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1818                         };
1819                 };
1820
1821                 i2s0 {
1822                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1823                                 rockchip,pins =
1824                                         <3 RK_PC1 2 &pcfg_pull_none>;
1825                         };
1826
1827                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1828                                 rockchip,pins =
1829                                         <3 RK_PC3 2 &pcfg_pull_none>;
1830                         };
1831
1832                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1833                                 rockchip,pins =
1834                                         <3 RK_PB4 2 &pcfg_pull_none>;
1835                         };
1836
1837                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1838                                 rockchip,pins =
1839                                         <3 RK_PC2 2 &pcfg_pull_none>;
1840                         };
1841
1842                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1843                                 rockchip,pins =
1844                                         <3 RK_PB5 2 &pcfg_pull_none>;
1845                         };
1846
1847                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1848                                 rockchip,pins =
1849                                         <3 RK_PC4 2 &pcfg_pull_none>;
1850                         };
1851
1852                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1853                                 rockchip,pins =
1854                                         <3 RK_PC0 2 &pcfg_pull_none>;
1855                         };
1856
1857                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1858                                 rockchip,pins =
1859                                         <3 RK_PB7 2 &pcfg_pull_none>;
1860                         };
1861
1862                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1863                                 rockchip,pins =
1864                                         <3 RK_PB6 2 &pcfg_pull_none>;
1865                         };
1866
1867                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1868                                 rockchip,pins =
1869                                         <3 RK_PC5 2 &pcfg_pull_none>;
1870                         };
1871
1872                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1873                                 rockchip,pins =
1874                                         <3 RK_PB3 2 &pcfg_pull_none>;
1875                         };
1876
1877                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1878                                 rockchip,pins =
1879                                         <3 RK_PB1 2 &pcfg_pull_none>;
1880                         };
1881
1882                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1883                                 rockchip,pins =
1884                                         <3 RK_PB0 2 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 i2s1 {
1889                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1890                                 rockchip,pins =
1891                                         <2 RK_PC3 1 &pcfg_pull_none>;
1892                         };
1893
1894                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1895                                 rockchip,pins =
1896                                         <2 RK_PC2 1 &pcfg_pull_none>;
1897                         };
1898
1899                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1900                                 rockchip,pins =
1901                                         <2 RK_PC1 1 &pcfg_pull_none>;
1902                         };
1903
1904                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1905                                 rockchip,pins =
1906                                         <2 RK_PC5 1 &pcfg_pull_none>;
1907                         };
1908
1909                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1910                                 rockchip,pins =
1911                                         <2 RK_PC4 1 &pcfg_pull_none>;
1912                         };
1913                 };
1914
1915                 i2s2 {
1916                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1917                                 rockchip,pins =
1918                                         <3 RK_PA1 2 &pcfg_pull_none>;
1919                         };
1920
1921                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1922                                 rockchip,pins =
1923                                         <3 RK_PA2 2 &pcfg_pull_none>;
1924                         };
1925
1926                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1927                                 rockchip,pins =
1928                                         <3 RK_PA3 2 &pcfg_pull_none>;
1929                         };
1930
1931                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1932                                 rockchip,pins =
1933                                         <3 RK_PA5 2 &pcfg_pull_none>;
1934                         };
1935
1936                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1937                                 rockchip,pins =
1938                                         <3 RK_PA7 2 &pcfg_pull_none>;
1939                         };
1940                 };
1941
1942                 sdmmc {
1943                         sdmmc_clk: sdmmc-clk {
1944                                 rockchip,pins =
1945                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1946                         };
1947
1948                         sdmmc_cmd: sdmmc-cmd {
1949                                 rockchip,pins =
1950                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1951                         };
1952
1953                         sdmmc_det: sdmmc-det {
1954                                 rockchip,pins =
1955                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1956                         };
1957
1958                         sdmmc_bus1: sdmmc-bus1 {
1959                                 rockchip,pins =
1960                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1961                         };
1962
1963                         sdmmc_bus4: sdmmc-bus4 {
1964                                 rockchip,pins =
1965                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1966                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1967                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1968                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1969                         };
1970                 };
1971
1972                 sdio {
1973                         sdio_clk: sdio-clk {
1974                                 rockchip,pins =
1975                                         <1 RK_PC5 1 &pcfg_pull_none>;
1976                         };
1977
1978                         sdio_cmd: sdio-cmd {
1979                                 rockchip,pins =
1980                                         <1 RK_PC4 1 &pcfg_pull_up>;
1981                         };
1982
1983                         sdio_bus4: sdio-bus4 {
1984                                 rockchip,pins =
1985                                         <1 RK_PC6 1 &pcfg_pull_up>,
1986                                         <1 RK_PC7 1 &pcfg_pull_up>,
1987                                         <1 RK_PD0 1 &pcfg_pull_up>,
1988                                         <1 RK_PD1 1 &pcfg_pull_up>;
1989                         };
1990                 };
1991
1992                 emmc {
1993                         emmc_clk: emmc-clk {
1994                                 rockchip,pins =
1995                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1996                         };
1997
1998                         emmc_cmd: emmc-cmd {
1999                                 rockchip,pins =
2000                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2001                         };
2002
2003                         emmc_rstnout: emmc-rstnout {
2004                                 rockchip,pins =
2005                                         <1 RK_PB3 2 &pcfg_pull_none>;
2006                         };
2007
2008                         emmc_bus1: emmc-bus1 {
2009                                 rockchip,pins =
2010                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2011                         };
2012
2013                         emmc_bus4: emmc-bus4 {
2014                                 rockchip,pins =
2015                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2016                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2017                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2018                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2019                         };
2020
2021                         emmc_bus8: emmc-bus8 {
2022                                 rockchip,pins =
2023                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2024                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2025                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2026                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2027                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2028                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2029                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2030                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2031                         };
2032                 };
2033
2034                 flash {
2035                         flash_cs0: flash-cs0 {
2036                                 rockchip,pins =
2037                                         <1 RK_PB0 1 &pcfg_pull_none>;
2038                         };
2039
2040                         flash_rdy: flash-rdy {
2041                                 rockchip,pins =
2042                                         <1 RK_PB1 1 &pcfg_pull_none>;
2043                         };
2044
2045                         flash_dqs: flash-dqs {
2046                                 rockchip,pins =
2047                                         <1 RK_PB2 1 &pcfg_pull_none>;
2048                         };
2049
2050                         flash_ale: flash-ale {
2051                                 rockchip,pins =
2052                                         <1 RK_PB3 1 &pcfg_pull_none>;
2053                         };
2054
2055                         flash_cle: flash-cle {
2056                                 rockchip,pins =
2057                                         <1 RK_PB4 1 &pcfg_pull_none>;
2058                         };
2059
2060                         flash_wrn: flash-wrn {
2061                                 rockchip,pins =
2062                                         <1 RK_PB5 1 &pcfg_pull_none>;
2063                         };
2064
2065                         flash_csl: flash-csl {
2066                                 rockchip,pins =
2067                                         <1 RK_PB6 1 &pcfg_pull_none>;
2068                         };
2069
2070                         flash_rdn: flash-rdn {
2071                                 rockchip,pins =
2072                                         <1 RK_PB7 1 &pcfg_pull_none>;
2073                         };
2074
2075                         flash_bus8: flash-bus8 {
2076                                 rockchip,pins =
2077                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2078                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2079                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2080                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2081                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2082                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2083                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2084                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2085                         };
2086                 };
2087
2088                 sfc {
2089                         sfc_bus4: sfc-bus4 {
2090                                 rockchip,pins =
2091                                         <1 RK_PA0 3 &pcfg_pull_none>,
2092                                         <1 RK_PA1 3 &pcfg_pull_none>,
2093                                         <1 RK_PA2 3 &pcfg_pull_none>,
2094                                         <1 RK_PA3 3 &pcfg_pull_none>;
2095                         };
2096
2097                         sfc_bus2: sfc-bus2 {
2098                                 rockchip,pins =
2099                                         <1 RK_PA0 3 &pcfg_pull_none>,
2100                                         <1 RK_PA1 3 &pcfg_pull_none>;
2101                         };
2102
2103                         sfc_cs0: sfc-cs0 {
2104                                 rockchip,pins =
2105                                         <1 RK_PA4 3 &pcfg_pull_none>;
2106                         };
2107
2108                         sfc_clk: sfc-clk {
2109                                 rockchip,pins =
2110                                         <1 RK_PB1 3 &pcfg_pull_none>;
2111                         };
2112                 };
2113
2114                 lcdc {
2115                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2116                                 rockchip,pins =
2117                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2118                         };
2119
2120                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2121                                 rockchip,pins =
2122                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2123                         };
2124
2125                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2126                                 rockchip,pins =
2127                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2128                         };
2129
2130                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2131                                 rockchip,pins =
2132                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2133                         };
2134
2135                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2136                                 rockchip,pins =
2137                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2138                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2139                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2140                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2141                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2142                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2143                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2144                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2145                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2146                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2147                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2148                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2149                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2150                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2151                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2152                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2153                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2154                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2155                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2156                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2157                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2158                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2159                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2160                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2161                         };
2162
2163                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2164                                 rockchip,pins =
2165                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2182                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2183                         };
2184
2185                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2186                                 rockchip,pins =
2187                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2188                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2189                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2190                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2191                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2192                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2193                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2194                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2195                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2196                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2197                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2198                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2199                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2200                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2201                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2202                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2203                         };
2204
2205                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2206                                 rockchip,pins =
2207                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2208                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2209                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2210                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2211                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2212                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2213                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2214                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2215                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2216                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2217                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2218                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2219                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2220                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2221                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2222                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2223                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2224                         };
2225
2226                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2227                                 rockchip,pins =
2228                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2229                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2230                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2231                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2232                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2233                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2234                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2235                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2236                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2237                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2238                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2239                         };
2240
2241                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2242                                 rockchip,pins =
2243                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2244                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2245                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2246                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2247                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2248                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2249                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2250                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2251                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2252                         };
2253                 };
2254
2255                 pwm0 {
2256                         pwm0_pin: pwm0-pin {
2257                                 rockchip,pins =
2258                                         <0 RK_PB7 1 &pcfg_pull_none>;
2259                         };
2260                 };
2261
2262                 pwm1 {
2263                         pwm1_pin: pwm1-pin {
2264                                 rockchip,pins =
2265                                         <0 RK_PC0 1 &pcfg_pull_none>;
2266                         };
2267                 };
2268
2269                 pwm2 {
2270                         pwm2_pin: pwm2-pin {
2271                                 rockchip,pins =
2272                                         <2 RK_PB5 1 &pcfg_pull_none>;
2273                         };
2274                 };
2275
2276                 pwm3 {
2277                         pwm3_pin: pwm3-pin {
2278                                 rockchip,pins =
2279                                         <0 RK_PC1 1 &pcfg_pull_none>;
2280                         };
2281                 };
2282
2283                 pwm4 {
2284                         pwm4_pin: pwm4-pin {
2285                                 rockchip,pins =
2286                                         <3 RK_PC2 3 &pcfg_pull_none>;
2287                         };
2288                 };
2289
2290                 pwm5 {
2291                         pwm5_pin: pwm5-pin {
2292                                 rockchip,pins =
2293                                         <3 RK_PC3 3 &pcfg_pull_none>;
2294                         };
2295                 };
2296
2297                 pwm6 {
2298                         pwm6_pin: pwm6-pin {
2299                                 rockchip,pins =
2300                                         <3 RK_PC4 3 &pcfg_pull_none>;
2301                         };
2302                 };
2303
2304                 pwm7 {
2305                         pwm7_pin: pwm7-pin {
2306                                 rockchip,pins =
2307                                         <3 RK_PC5 3 &pcfg_pull_none>;
2308                         };
2309                 };
2310
2311                 gmac {
2312                         rmii_pins: rmii-pins {
2313                                 rockchip,pins =
2314                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2315                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2316                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2317                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2318                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2319                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2320                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2321                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2322                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2323                         };
2324
2325                         mac_refclk_12ma: mac-refclk-12ma {
2326                                 rockchip,pins =
2327                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2328                         };
2329
2330                         mac_refclk: mac-refclk {
2331                                 rockchip,pins =
2332                                         <2 RK_PB2 2 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 cif-m0 {
2337                         cif_clkout_m0: cif-clkout-m0 {
2338                                 rockchip,pins =
2339                                         <2 RK_PB3 1 &pcfg_pull_none>;
2340                         };
2341
2342                         dvp_d2d9_m0: dvp-d2d9-m0 {
2343                                 rockchip,pins =
2344                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2345                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2346                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2347                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2348                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2349                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2350                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2351                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2352                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2353                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2354                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2355                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2356                         };
2357
2358                         dvp_d0d1_m0: dvp-d0d1-m0 {
2359                                 rockchip,pins =
2360                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2361                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2362                         };
2363
2364                         dvp_d10d11_m0:d10-d11-m0 {
2365                                 rockchip,pins =
2366                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2367                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2368                         };
2369                 };
2370
2371                 cif-m1 {
2372                         cif_clkout_m1: cif-clkout-m1 {
2373                                 rockchip,pins =
2374                                         <3 RK_PD0 3 &pcfg_pull_none>;
2375                         };
2376
2377                         dvp_d2d9_m1: dvp-d2d9-m1 {
2378                                 rockchip,pins =
2379                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2380                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2381                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2382                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2383                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2384                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2385                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2386                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2387                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2388                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2389                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2390                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2391                         };
2392
2393                         dvp_d0d1_m1: dvp-d0d1-m1 {
2394                                 rockchip,pins =
2395                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2396                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2397                         };
2398
2399                         dvp_d10d11_m1:d10-d11-m1 {
2400                                 rockchip,pins =
2401                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2402                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2403                         };
2404                 };
2405
2406                 isp {
2407                         isp_prelight: isp-prelight {
2408                                 rockchip,pins =
2409                                         <3 RK_PD1 4 &pcfg_pull_none>;
2410                         };
2411                 };
2412         };
2413 };