1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
5 * Copyright (C) 2022 Renesas Electronics Corp.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
21 compatible = "fixed-clock";
23 clock-frequency = <12000000>;
27 compatible = "hdmi-connector";
31 hdmi_con_out: endpoint {
32 remote-endpoint = <&adv7535_out>;
38 #if (SW_SCIF_CAN || SW_RSPI_CAN)
40 pinctrl-0 = <&can1_pins>;
41 /delete-node/ channel@0;
45 /delete-property/ pinctrl-0;
46 /delete-property/ pinctrl-names;
71 data-lanes = <1 2 3 4>;
72 remote-endpoint = <&adv7535_in>;
80 compatible = "adi,adv7535";
83 interrupt-parent = <&pinctrl>;
84 interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
87 avdd-supply = <®_1p8v>;
88 dvdd-supply = <®_1p8v>;
89 pvdd-supply = <®_1p8v>;
90 a2vdd-supply = <®_1p8v>;
91 v3p3-supply = <®_3p3v>;
92 v1p2-supply = <®_1p8v>;
102 adv7535_in: endpoint {
103 remote-endpoint = <&dsi0_out>;
109 adv7535_out: endpoint {
110 remote-endpoint = <&hdmi_con_out>;
118 pinctrl-0 = <&i2c2_pins>;
119 pinctrl-names = "default";
120 clock-frequency = <400000>;
125 compatible = "wlf,wm8978";
126 #sound-dai-cells = <0>;
130 versa3: clock-generator@68 {
131 compatible = "renesas,5p35023";
137 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
138 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
142 assigned-clocks = <&versa3 0>, <&versa3 1>,
143 <&versa3 2>, <&versa3 3>,
144 <&versa3 4>, <&versa3 5>;
145 assigned-clock-rates = <24000000>, <11289600>,
146 <11289600>, <12000000>,
147 <25000000>, <12288000>;
153 pinctrl-0 = <&mtu3_pins>;
154 pinctrl-names = "default";
165 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
166 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
167 * SW2 should be at position 2->3 so that SER0_TX line is activated
168 * SW3 should be at position 2->3 so that SER0_RX line is activated
169 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
171 #if (!SW_SCIF_CAN && PMOD1_SER0)
173 pinctrl-0 = <&scif1_pins>;
174 pinctrl-names = "default";
182 pinctrl-0 = <&ssi0_pins>;
183 pinctrl-names = "default";
190 /delete-property/ pinctrl-0;
191 /delete-property/ pinctrl-names;
197 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;