1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
5 * Copyright (C) 2022 Renesas Electronics Corp.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * DIP-Switch SW1 setting on SoM
14 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
15 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
16 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
17 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
18 * Please change below macros according to SW1 setting
21 #define SW_SD0_DEV_SEL 1
25 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
28 /* Please set SW_RSPI_CAN. Default value is 1 */
32 #if (SW_SCIF_CAN && SW_RSPI_CAN)
33 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
36 #include "rzg2lc-smarc-som.dtsi"
37 #include "rzg2lc-smarc-pinfunction.dtsi"
38 #include "rz-smarc-common.dtsi"
40 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
50 #if (SW_SCIF_CAN || SW_RSPI_CAN)
52 pinctrl-0 = <&can1_pins>;
53 /delete-node/ channel@0;
57 /delete-property/ pinctrl-0;
58 /delete-property/ pinctrl-names;
68 pinctrl-0 = <&i2c2_pins>;
69 pinctrl-names = "default";
70 clock-frequency = <400000>;
75 compatible = "wlf,wm8978";
76 #sound-dai-cells = <0>;
82 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
83 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
84 * SW2 should be at position 2->3 so that SER0_TX line is activated
85 * SW3 should be at position 2->3 so that SER0_RX line is activated
86 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
88 #if (!SW_SCIF_CAN && PMOD1_SER0)
90 pinctrl-0 = <&scif1_pins>;
91 pinctrl-names = "default";
99 pinctrl-0 = <&ssi0_pins>;
100 pinctrl-names = "default";
107 /delete-property/ pinctrl-0;
108 /delete-property/ pinctrl-names;
114 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;