1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts
5 * Copyright (C) 2021 Renesas Electronics Corp.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
18 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
22 device_type = "memory";
23 /* first 128MB is reserved for secure area. */
24 reg = <0x0 0x48000000 0x0 0x38000000>;
27 reg_1p8v: regulator-1p8v {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
36 reg_3p3v: regulator-3p3v {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
45 reg_1p1v: regulator-vdd-core {
46 compatible = "regulator-fixed";
47 regulator-name = "fixed-1.1V";
48 regulator-min-microvolt = <1100000>;
49 regulator-max-microvolt = <1100000>;
54 vccq_sdhi0: regulator-vccq-sdhi0 {
55 compatible = "regulator-gpio";
57 regulator-name = "SDHI0 VccQ";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3300000>;
60 states = <3300000 1>, <1800000 0>;
62 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
66 /* 32.768kHz crystal */
68 compatible = "fixed-clock";
70 clock-frequency = <32768>;
75 pinctrl-0 = <ð0_pins>;
76 pinctrl-names = "default";
78 phy-mode = "rgmii-id";
81 phy0: ethernet-phy@7 {
82 compatible = "ethernet-phy-id0022.1640",
83 "ethernet-phy-ieee802.3-c22";
85 interrupt-parent = <&irqc>;
86 interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
87 rxc-skew-psec = <2400>;
88 txc-skew-psec = <2400>;
103 clock-frequency = <24000000>;
107 mali-supply = <®_1p1v>;
112 compatible = "renesas,raa215300";
113 reg = <0x12>, <0x6f>;
114 reg-names = "main", "rtc";
131 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
132 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
133 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
134 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
135 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
136 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
137 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
138 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
139 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
140 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
141 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
142 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
143 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
144 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
145 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
146 <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */
149 gpio-sd0-pwr-en-hog {
151 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
153 line-name = "gpio_sd0_pwr_en";
158 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
159 power-source = <1800>;
163 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
164 power-source = <1800>;
169 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
170 * The below switch logic can be used to select the device between
171 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
172 * SW1[2] should be at OFF position to enable 64 GB eMMC
173 * SW1[2] should be at position ON to enable uSD card CN3
175 gpio-sd0-dev-sel-hog {
177 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
179 line-name = "gpio_sd0_dev_sel";
182 sdhi0_emmc_pins: sd0emmc {
184 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
185 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
186 power-source = <1800>;
190 pins = "SD0_CLK", "SD0_CMD";
191 power-source = <1800>;
196 power-source = <1800>;
202 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
203 power-source = <3300>;
207 pins = "SD0_CLK", "SD0_CMD";
208 power-source = <3300>;
212 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
216 sdhi0_pins_uhs: sd0_uhs {
218 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
219 power-source = <1800>;
223 pins = "SD0_CLK", "SD0_CMD";
224 power-source = <1800>;
228 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
234 pinctrl-0 = <&qspi0_pins>;
235 pinctrl-names = "default";
239 compatible = "micron,mt25qu512a", "jedec,spi-nor";
242 spi-max-frequency = <50000000>;
243 spi-rx-bus-width = <4>;
246 compatible = "fixed-partitions";
247 #address-cells = <1>;
251 reg = <0x00000000 0x2000000>;
255 reg = <0x2000000 0x2000000>;
261 #if (!SW_SD0_DEV_SEL)
263 pinctrl-0 = <&sdhi0_pins>;
264 pinctrl-1 = <&sdhi0_pins_uhs>;
265 pinctrl-names = "default", "state_uhs";
267 vmmc-supply = <®_3p3v>;
268 vqmmc-supply = <&vccq_sdhi0>;
278 pinctrl-0 = <&sdhi0_emmc_pins>;
279 pinctrl-1 = <&sdhi0_emmc_pins>;
280 pinctrl-names = "default", "state_uhs";
282 vmmc-supply = <®_3p3v>;
283 vqmmc-supply = <®_1p8v>;
287 fixed-emmc-driver-type = <1>;