arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2LC SMARC SOM common parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  10
  11 / {
  12         aliases {
  13                 ethernet0 = &eth0;
  14         };
  15
  16         chosen {
  17                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  18         };
  19
  20         memory@48000000 {
  21                 device_type = "memory";
  22                 /* first 128MB is reserved for secure area. */
  23                 reg = <0x0 0x48000000 0x0 0x38000000>;
  24         };
  25
  26         reg_1p8v: regulator-1p8v {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "fixed-1.8V";
  29                 regulator-min-microvolt = <1800000>;
  30                 regulator-max-microvolt = <1800000>;
  31                 regulator-boot-on;
  32                 regulator-always-on;
  33         };
  34
  35         reg_3p3v: regulator-3p3v {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "fixed-3.3V";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 regulator-boot-on;
  41                 regulator-always-on;
  42         };
  43
  44         reg_1p1v: regulator-vdd-core {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "fixed-1.1V";
  47                 regulator-min-microvolt = <1100000>;
  48                 regulator-max-microvolt = <1100000>;
  49                 regulator-boot-on;
  50                 regulator-always-on;
  51         };
  52
  53         vccq_sdhi0: regulator-vccq-sdhi0 {
  54                 compatible = "regulator-gpio";
  55
  56                 regulator-name = "SDHI0 VccQ";
  57                 regulator-min-microvolt = <1800000>;
  58                 regulator-max-microvolt = <3300000>;
  59                 states = <3300000 1>, <1800000 0>;
  60                 regulator-boot-on;
  61                 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
  62                 regulator-always-on;
  63         };
  64 };
  65
  66 &eth0 {
  67         pinctrl-0 = <&eth0_pins>;
  68         pinctrl-names = "default";
  69         phy-handle = <&phy0>;
  70         phy-mode = "rgmii-id";
  71         status = "okay";
  72
  73         phy0: ethernet-phy@7 {
  74                 compatible = "ethernet-phy-id0022.1640",
  75                              "ethernet-phy-ieee802.3-c22";
  76                 reg = <7>;
  77                 rxc-skew-psec = <2400>;
  78                 txc-skew-psec = <2400>;
  79                 rxdv-skew-psec = <0>;
  80                 txen-skew-psec = <0>;
  81                 rxd0-skew-psec = <0>;
  82                 rxd1-skew-psec = <0>;
  83                 rxd2-skew-psec = <0>;
  84                 rxd3-skew-psec = <0>;
  85                 txd0-skew-psec = <0>;
  86                 txd1-skew-psec = <0>;
  87                 txd2-skew-psec = <0>;
  88                 txd3-skew-psec = <0>;
  89         };
  90 };
  91
  92 &extal_clk {
  93         clock-frequency = <24000000>;
  94 };
  95
  96 &gpu {
  97         mali-supply = <&reg_1p1v>;
  98 };
  99
 100 &ostm1 {
 101         status = "okay";
 102 };
 103
 104 &ostm2 {
 105         status = "okay";
 106 };
 107
 108 &pinctrl {
 109         eth0_pins: eth0 {
 110                 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
 111                          <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
 112                          <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
 113                          <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
 114                          <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
 115                          <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
 116                          <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
 117                          <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
 118                          <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
 119                          <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
 120                          <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
 121                          <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 122                          <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 123                          <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
 124                          <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
 125         };
 126
 127         gpio-sd0-pwr-en-hog {
 128                 gpio-hog;
 129                 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
 130                 output-high;
 131                 line-name = "gpio_sd0_pwr_en";
 132         };
 133
 134         qspi0_pins: qspi0 {
 135                 qspi0-data {
 136                         pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
 137                         power-source = <1800>;
 138                 };
 139
 140                 qspi0-ctrl {
 141                         pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
 142                         power-source = <1800>;
 143                 };
 144         };
 145
 146         /*
 147          * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
 148          * The below switch logic can be used to select the device between
 149          * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
 150          * SW1[2] should be at OFF position to enable 64 GB eMMC
 151          * SW1[2] should be at position ON to enable uSD card CN3
 152          */
 153         gpio-sd0-dev-sel-hog {
 154                 gpio-hog;
 155                 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
 156                 output-high;
 157                 line-name = "gpio_sd0_dev_sel";
 158         };
 159
 160         sdhi0_emmc_pins: sd0emmc {
 161                 sd0_emmc_data {
 162                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 163                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 164                         power-source = <1800>;
 165                 };
 166
 167                 sd0_emmc_ctrl {
 168                         pins = "SD0_CLK", "SD0_CMD";
 169                         power-source = <1800>;
 170                 };
 171
 172                 sd0_emmc_rst {
 173                         pins = "SD0_RST#";
 174                         power-source = <1800>;
 175                 };
 176         };
 177
 178         sdhi0_pins: sd0 {
 179                 sd0_data {
 180                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 181                         power-source = <3300>;
 182                 };
 183
 184                 sd0_ctrl {
 185                         pins = "SD0_CLK", "SD0_CMD";
 186                         power-source = <3300>;
 187                 };
 188
 189                 sd0_mux {
 190                         pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
 191                 };
 192         };
 193
 194         sdhi0_pins_uhs: sd0_uhs {
 195                 sd0_data_uhs {
 196                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 197                         power-source = <1800>;
 198                 };
 199
 200                 sd0_ctrl_uhs {
 201                         pins = "SD0_CLK", "SD0_CMD";
 202                         power-source = <1800>;
 203                 };
 204
 205                 sd0_mux_uhs {
 206                         pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
 207                 };
 208         };
 209 };
 210
 211 &sbc {
 212         pinctrl-0 = <&qspi0_pins>;
 213         pinctrl-names = "default";
 214         status = "okay";
 215
 216         flash@0 {
 217                 compatible = "micron,mt25qu512a", "jedec,spi-nor";
 218                 reg = <0>;
 219                 m25p,fast-read;
 220                 spi-max-frequency = <50000000>;
 221                 spi-rx-bus-width = <4>;
 222
 223                 partitions {
 224                         compatible = "fixed-partitions";
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227
 228                         boot@0 {
 229                                 reg = <0x00000000 0x2000000>;
 230                                 read-only;
 231                         };
 232                         user@2000000 {
 233                                 reg = <0x2000000 0x2000000>;
 234                         };
 235                 };
 236         };
 237 };
 238
 239 #if (!SW_SD0_DEV_SEL)
 240 &sdhi0 {
 241         pinctrl-0 = <&sdhi0_pins>;
 242         pinctrl-1 = <&sdhi0_pins_uhs>;
 243         pinctrl-names = "default", "state_uhs";
 244
 245         vmmc-supply = <&reg_3p3v>;
 246         vqmmc-supply = <&vccq_sdhi0>;
 247         bus-width = <4>;
 248         sd-uhs-sdr50;
 249         sd-uhs-sdr104;
 250         status = "okay";
 251 };
 252 #endif
 253
 254 #if SW_SD0_DEV_SEL
 255 &sdhi0 {
 256         pinctrl-0 = <&sdhi0_emmc_pins>;
 257         pinctrl-1 = <&sdhi0_emmc_pins>;
 258         pinctrl-names = "default", "state_uhs";
 259
 260         vmmc-supply = <&reg_3p3v>;
 261         vqmmc-supply = <&reg_1p8v>;
 262         bus-width = <8>;
 263         mmc-hs200-1_8v;
 264         non-removable;
 265         fixed-emmc-driver-type = <1>;
 266         status = "okay";
 267 };
 268 #endif
 269
 270 &wdt0 {
 271         status = "okay";
 272         timeout-sec = <60>;
 273 };
 274
 275 &wdt1 {
 276         status = "okay";
 277         timeout-sec = <60>;
 278 };
 279
 280 &wdt2 {
 281         status = "okay";
 282         timeout-sec = <60>;
 283 };