1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
5 * Copyright (C) 2021 Renesas Electronics Corp.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
16 /* SW8 should be at position 2->1 */
18 pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
19 <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
27 gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
29 line-name = "can1_stb";
33 pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
34 <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
39 pins = "RIIC0_SDA", "RIIC0_SCL";
44 pins = "RIIC1_SDA", "RIIC1_SCL";
49 pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
50 <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
55 pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
56 <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
57 <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
58 <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
63 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
64 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
68 pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
69 <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
70 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
71 <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
76 gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
78 line-name = "sd1_pwr_en";
83 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
84 power-source = <3300>;
88 pins = "SD1_CLK", "SD1_CMD";
89 power-source = <3300>;
93 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
97 sdhi1_pins_uhs: sd1_uhs {
99 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
100 power-source = <1800>;
104 pins = "SD1_CLK", "SD1_CMD";
105 power-source = <1800>;
109 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
113 sound_clk_pins: sound_clk {
114 pins = "AUDIO_CLK1", "AUDIO_CLK2";
119 pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
120 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
121 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
122 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
126 pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
127 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
128 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
129 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
133 pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
134 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
135 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
139 pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
140 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */