arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  10
  11 / {
  12         aliases {
  13                 serial1 = &scif2;
  14                 i2c3 = &i2c3;
  15         };
  16
  17         osc1: cec-clock {
  18                 compatible = "fixed-clock";
  19                 #clock-cells = <0>;
  20                 clock-frequency = <12000000>;
  21         };
  22
  23         hdmi-out {
  24                 compatible = "hdmi-connector";
  25                 type = "d";
  26
  27                 port {
  28                         hdmi_con_out: endpoint {
  29                                 remote-endpoint = <&adv7535_out>;
  30                         };
  31                 };
  32         };
  33 };
  34
  35 &cpu_dai {
  36         sound-dai = <&ssi0>;
  37 };
  38
  39 &dsi {
  40         status = "okay";
  41
  42         ports {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 port@0 {
  47                         reg = <0>;
  48                         dsi0_in: endpoint {
  49                         };
  50                 };
  51
  52                 port@1 {
  53                         reg = <1>;
  54                         dsi0_out: endpoint {
  55                                 data-lanes = <1 2 3 4>;
  56                                 remote-endpoint = <&adv7535_in>;
  57                         };
  58                 };
  59         };
  60 };
  61
  62 &i2c1 {
  63         adv7535: hdmi@3d {
  64                 compatible = "adi,adv7535";
  65                 reg = <0x3d>;
  66
  67                 interrupt-parent = <&pinctrl>;
  68                 interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
  69                 clocks = <&osc1>;
  70                 clock-names = "cec";
  71                 avdd-supply = <&reg_1p8v>;
  72                 dvdd-supply = <&reg_1p8v>;
  73                 pvdd-supply = <&reg_1p8v>;
  74                 a2vdd-supply = <&reg_1p8v>;
  75                 v3p3-supply = <&reg_3p3v>;
  76                 v1p2-supply = <&reg_1p8v>;
  77
  78                 adi,dsi-lanes = <4>;
  79
  80                 ports {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83
  84                         port@0 {
  85                                 reg = <0>;
  86                                 adv7535_in: endpoint {
  87                                         remote-endpoint = <&dsi0_out>;
  88                                 };
  89                         };
  90
  91                         port@1 {
  92                                 reg = <1>;
  93                                 adv7535_out: endpoint {
  94                                         remote-endpoint = <&hdmi_con_out>;
  95                                 };
  96                         };
  97                 };
  98         };
  99 };
 100
 101 &i2c3 {
 102         pinctrl-0 = <&i2c3_pins>;
 103         pinctrl-names = "default";
 104         clock-frequency = <400000>;
 105
 106         status = "okay";
 107
 108         wm8978: codec@1a {
 109                 compatible = "wlf,wm8978";
 110                 #sound-dai-cells = <0>;
 111                 reg = <0x1a>;
 112         };
 113
 114         versa3: clock-generator@68 {
 115                 compatible = "renesas,5p35023";
 116                 reg = <0x68>;
 117                 #clock-cells = <1>;
 118                 clocks = <&x1>;
 119
 120                 renesas,settings = [
 121                         80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
 122                         00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
 123                         80 b0 45 c4 95
 124                 ];
 125
 126                 assigned-clocks = <&versa3 0>, <&versa3 1>,
 127                                   <&versa3 2>, <&versa3 3>,
 128                                   <&versa3 4>, <&versa3 5>;
 129                 assigned-clock-rates = <24000000>, <11289600>,
 130                                        <11289600>, <12000000>,
 131                                        <25000000>, <12288000>;
 132         };
 133 };
 134
 135 #if PMOD_MTU3
 136 &mtu3 {
 137         pinctrl-0 = <&mtu3_pins>;
 138         pinctrl-names = "default";
 139
 140         status = "okay";
 141 };
 142
 143 #if MTU3_COUNTER_Z_PHASE_SIGNAL
 144 /* SDHI cd pin is muxed with counter Z phase signal */
 145 &sdhi1 {
 146         status = "disabled";
 147 };
 148 #endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
 149
 150 &spi1 {
 151         status = "disabled";
 152 };
 153 #endif /* PMOD_MTU3 */
 154
 155 /*
 156  * To enable SCIF2 (SER0) on PMOD1 (CN7)
 157  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
 158  * SW2 should be at position 2->3 so that SER0_TX line is activated
 159  * SW3 should be at position 2->3 so that SER0_RX line is activated
 160  * SW4 should be at position 2->3 so that SER0_RTS# line is activated
 161  */
 162 #if PMOD1_SER0
 163 &scif2 {
 164         pinctrl-0 = <&scif2_pins>;
 165         pinctrl-names = "default";
 166
 167         uart-has-rtscts;
 168         status = "okay";
 169 };
 170 #endif
 171
 172 &ssi0 {
 173         pinctrl-0 = <&ssi0_pins>;
 174         pinctrl-names = "default";
 175
 176         status = "okay";
 177 };
 178
 179 &vccq_sdhi1 {
 180         gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
 181 };