1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
5 * Copyright (C) 2021 Renesas Electronics Corp.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
16 * To enable uSD card on CN3,
17 * SW1[2] should be at position 3/ON.
18 * Disable eMMC by setting "#define EMMC 0" above.
29 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
33 device_type = "memory";
34 /* first 128MB is reserved for secure area. */
35 reg = <0x0 0x48000000 0x0 0x78000000>;
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <1800000>;
47 reg_3p3v: regulator-3p3v {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
56 reg_1p1v: regulator-vdd-core {
57 compatible = "regulator-fixed";
58 regulator-name = "fixed-1.1V";
59 regulator-min-microvolt = <1100000>;
60 regulator-max-microvolt = <1100000>;
65 vccq_sdhi0: regulator-vccq-sdhi0 {
66 compatible = "regulator-gpio";
68 regulator-name = "SDHI0 VccQ";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3300000>;
71 states = <3300000 1>, <1800000 0>;
73 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
77 /* 32.768kHz crystal */
79 compatible = "fixed-clock";
81 clock-frequency = <32768>;
86 pinctrl-0 = <&adc_pins>;
87 pinctrl-names = "default";
90 /delete-node/ channel@6;
91 /delete-node/ channel@7;
95 pinctrl-0 = <ð0_pins>;
96 pinctrl-names = "default";
98 phy-mode = "rgmii-id";
101 phy0: ethernet-phy@7 {
102 compatible = "ethernet-phy-id0022.1640",
103 "ethernet-phy-ieee802.3-c22";
105 interrupt-parent = <&irqc>;
106 interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
107 rxc-skew-psec = <2400>;
108 txc-skew-psec = <2400>;
109 rxdv-skew-psec = <0>;
110 txen-skew-psec = <0>;
111 rxd0-skew-psec = <0>;
112 rxd1-skew-psec = <0>;
113 rxd2-skew-psec = <0>;
114 rxd3-skew-psec = <0>;
115 txd0-skew-psec = <0>;
116 txd1-skew-psec = <0>;
117 txd2-skew-psec = <0>;
118 txd3-skew-psec = <0>;
123 pinctrl-0 = <ð1_pins>;
124 pinctrl-names = "default";
125 phy-handle = <&phy1>;
126 phy-mode = "rgmii-id";
129 phy1: ethernet-phy@7 {
130 compatible = "ethernet-phy-id0022.1640",
131 "ethernet-phy-ieee802.3-c22";
133 interrupt-parent = <&irqc>;
134 interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
135 rxc-skew-psec = <2400>;
136 txc-skew-psec = <2400>;
137 rxdv-skew-psec = <0>;
138 txen-skew-psec = <0>;
139 rxd0-skew-psec = <0>;
140 rxd1-skew-psec = <0>;
141 rxd2-skew-psec = <0>;
142 rxd3-skew-psec = <0>;
143 txd0-skew-psec = <0>;
144 txd1-skew-psec = <0>;
145 txd2-skew-psec = <0>;
146 txd3-skew-psec = <0>;
151 clock-frequency = <24000000>;
155 mali-supply = <®_1p1v>;
160 compatible = "renesas,raa215300";
161 reg = <0x12>, <0x6f>;
162 reg-names = "main", "rtc";
179 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
183 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
184 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
185 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
186 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
187 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
188 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
189 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
190 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
191 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
192 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
193 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
194 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
195 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
196 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
197 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
198 <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
202 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
203 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
204 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
205 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
206 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
207 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
208 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
209 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
210 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
211 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
212 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
213 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
214 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
215 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
216 <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
217 <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
220 gpio-sd0-pwr-en-hog {
222 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
224 line-name = "gpio_sd0_pwr_en";
229 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
230 power-source = <1800>;
234 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
235 power-source = <1800>;
240 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
241 * The below switch logic can be used to select the device between
242 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
243 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
244 * SW1[2] should be at position 3/ON to enable uSD card CN3
248 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
250 line-name = "sd0_dev_sel";
253 sdhi0_emmc_pins: sd0emmc {
255 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
256 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
257 power-source = <1800>;
261 pins = "SD0_CLK", "SD0_CMD";
262 power-source = <1800>;
267 power-source = <1800>;
273 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
274 power-source = <3300>;
278 pins = "SD0_CLK", "SD0_CMD";
279 power-source = <3300>;
283 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
287 sdhi0_pins_uhs: sd0_uhs {
289 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
290 power-source = <1800>;
294 pins = "SD0_CLK", "SD0_CMD";
295 power-source = <1800>;
299 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
305 pinctrl-0 = <&qspi0_pins>;
306 pinctrl-names = "default";
310 compatible = "micron,mt25qu512a", "jedec,spi-nor";
313 spi-max-frequency = <50000000>;
314 spi-rx-bus-width = <4>;
317 compatible = "fixed-partitions";
318 #address-cells = <1>;
322 reg = <0x00000000 0x2000000>;
326 reg = <0x2000000 0x2000000>;
334 pinctrl-0 = <&sdhi0_pins>;
335 pinctrl-1 = <&sdhi0_pins_uhs>;
336 pinctrl-names = "default", "state_uhs";
338 vmmc-supply = <®_3p3v>;
339 vqmmc-supply = <&vccq_sdhi0>;
349 pinctrl-0 = <&sdhi0_emmc_pins>;
350 pinctrl-1 = <&sdhi0_emmc_pins>;
351 pinctrl-names = "default", "state_uhs";
353 vmmc-supply = <®_3p3v>;
354 vqmmc-supply = <®_1p8v>;
358 fixed-emmc-driver-type = <1>;