arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
  10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  11
  12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
  13 #define EMMC    1
  14
  15 /*
  16  * To enable uSD card on CN3,
  17  * SW1[2] should be at position 3/ON.
  18  * Disable eMMC by setting "#define EMMC        0" above.
  19  */
  20 #define SDHI    (!EMMC)
  21
  22 / {
  23         aliases {
  24                 ethernet0 = &eth0;
  25                 ethernet1 = &eth1;
  26         };
  27
  28         chosen {
  29                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  30         };
  31
  32         memory@48000000 {
  33                 device_type = "memory";
  34                 /* first 128MB is reserved for secure area. */
  35                 reg = <0x0 0x48000000 0x0 0x78000000>;
  36         };
  37
  38         reg_1p8v: regulator-1p8v {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "fixed-1.8V";
  41                 regulator-min-microvolt = <1800000>;
  42                 regulator-max-microvolt = <1800000>;
  43                 regulator-boot-on;
  44                 regulator-always-on;
  45         };
  46
  47         reg_3p3v: regulator-3p3v {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "fixed-3.3V";
  50                 regulator-min-microvolt = <3300000>;
  51                 regulator-max-microvolt = <3300000>;
  52                 regulator-boot-on;
  53                 regulator-always-on;
  54         };
  55
  56         reg_1p1v: regulator-vdd-core {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "fixed-1.1V";
  59                 regulator-min-microvolt = <1100000>;
  60                 regulator-max-microvolt = <1100000>;
  61                 regulator-boot-on;
  62                 regulator-always-on;
  63         };
  64
  65         vccq_sdhi0: regulator-vccq-sdhi0 {
  66                 compatible = "regulator-gpio";
  67
  68                 regulator-name = "SDHI0 VccQ";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 states = <3300000 1>, <1800000 0>;
  72                 regulator-boot-on;
  73                 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
  74                 regulator-always-on;
  75         };
  76
  77         /* 32.768kHz crystal */
  78         x2: x2-clock {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <32768>;
  82         };
  83 };
  84
  85 &adc {
  86         pinctrl-0 = <&adc_pins>;
  87         pinctrl-names = "default";
  88         status = "okay";
  89
  90         /delete-node/ channel@6;
  91         /delete-node/ channel@7;
  92 };
  93
  94 &eth0 {
  95         pinctrl-0 = <&eth0_pins>;
  96         pinctrl-names = "default";
  97         phy-handle = <&phy0>;
  98         phy-mode = "rgmii-id";
  99         status = "okay";
 100
 101         phy0: ethernet-phy@7 {
 102                 compatible = "ethernet-phy-id0022.1640",
 103                              "ethernet-phy-ieee802.3-c22";
 104                 reg = <7>;
 105                 interrupt-parent = <&irqc>;
 106                 interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
 107                 rxc-skew-psec = <2400>;
 108                 txc-skew-psec = <2400>;
 109                 rxdv-skew-psec = <0>;
 110                 txen-skew-psec = <0>;
 111                 rxd0-skew-psec = <0>;
 112                 rxd1-skew-psec = <0>;
 113                 rxd2-skew-psec = <0>;
 114                 rxd3-skew-psec = <0>;
 115                 txd0-skew-psec = <0>;
 116                 txd1-skew-psec = <0>;
 117                 txd2-skew-psec = <0>;
 118                 txd3-skew-psec = <0>;
 119         };
 120 };
 121
 122 &eth1 {
 123         pinctrl-0 = <&eth1_pins>;
 124         pinctrl-names = "default";
 125         phy-handle = <&phy1>;
 126         phy-mode = "rgmii-id";
 127         status = "okay";
 128
 129         phy1: ethernet-phy@7 {
 130                 compatible = "ethernet-phy-id0022.1640",
 131                              "ethernet-phy-ieee802.3-c22";
 132                 reg = <7>;
 133                 interrupt-parent = <&irqc>;
 134                 interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
 135                 rxc-skew-psec = <2400>;
 136                 txc-skew-psec = <2400>;
 137                 rxdv-skew-psec = <0>;
 138                 txen-skew-psec = <0>;
 139                 rxd0-skew-psec = <0>;
 140                 rxd1-skew-psec = <0>;
 141                 rxd2-skew-psec = <0>;
 142                 rxd3-skew-psec = <0>;
 143                 txd0-skew-psec = <0>;
 144                 txd1-skew-psec = <0>;
 145                 txd2-skew-psec = <0>;
 146                 txd3-skew-psec = <0>;
 147         };
 148 };
 149
 150 &extal_clk {
 151         clock-frequency = <24000000>;
 152 };
 153
 154 &gpu {
 155         mali-supply = <&reg_1p1v>;
 156 };
 157
 158 &i2c3 {
 159         raa215300: pmic@12 {
 160                 compatible = "renesas,raa215300";
 161                 reg = <0x12>, <0x6f>;
 162                 reg-names = "main", "rtc";
 163
 164                 clocks = <&x2>;
 165                 clock-names = "xin";
 166         };
 167 };
 168
 169 &ostm1 {
 170         status = "okay";
 171 };
 172
 173 &ostm2 {
 174         status = "okay";
 175 };
 176
 177 &pinctrl {
 178         adc_pins: adc {
 179                 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
 180         };
 181
 182         eth0_pins: eth0 {
 183                 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
 184                          <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
 185                          <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
 186                          <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
 187                          <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
 188                          <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
 189                          <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
 190                          <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
 191                          <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
 192                          <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
 193                          <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
 194                          <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 195                          <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 196                          <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
 197                          <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
 198                          <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
 199         };
 200
 201         eth1_pins: eth1 {
 202                 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
 203                          <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
 204                          <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
 205                          <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
 206                          <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
 207                          <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
 208                          <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
 209                          <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
 210                          <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
 211                          <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
 212                          <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
 213                          <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
 214                          <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
 215                          <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
 216                          <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
 217                          <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
 218         };
 219
 220         gpio-sd0-pwr-en-hog {
 221                 gpio-hog;
 222                 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
 223                 output-high;
 224                 line-name = "gpio_sd0_pwr_en";
 225         };
 226
 227         qspi0_pins: qspi0 {
 228                 qspi0-data {
 229                         pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
 230                         power-source = <1800>;
 231                 };
 232
 233                 qspi0-ctrl {
 234                         pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
 235                         power-source = <1800>;
 236                 };
 237         };
 238
 239         /*
 240          * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
 241          * The below switch logic can be used to select the device between
 242          * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
 243          * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
 244          * SW1[2] should be at position 3/ON to enable uSD card CN3
 245          */
 246         sd0-dev-sel-hog {
 247                 gpio-hog;
 248                 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
 249                 output-high;
 250                 line-name = "sd0_dev_sel";
 251         };
 252
 253         sdhi0_emmc_pins: sd0emmc {
 254                 sd0_emmc_data {
 255                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 256                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 257                         power-source = <1800>;
 258                 };
 259
 260                 sd0_emmc_ctrl {
 261                         pins = "SD0_CLK", "SD0_CMD";
 262                         power-source = <1800>;
 263                 };
 264
 265                 sd0_emmc_rst {
 266                         pins = "SD0_RST#";
 267                         power-source = <1800>;
 268                 };
 269         };
 270
 271         sdhi0_pins: sd0 {
 272                 sd0_data {
 273                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 274                         power-source = <3300>;
 275                 };
 276
 277                 sd0_ctrl {
 278                         pins = "SD0_CLK", "SD0_CMD";
 279                         power-source = <3300>;
 280                 };
 281
 282                 sd0_mux {
 283                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 284                 };
 285         };
 286
 287         sdhi0_pins_uhs: sd0_uhs {
 288                 sd0_data_uhs {
 289                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 290                         power-source = <1800>;
 291                 };
 292
 293                 sd0_ctrl_uhs {
 294                         pins = "SD0_CLK", "SD0_CMD";
 295                         power-source = <1800>;
 296                 };
 297
 298                 sd0_mux_uhs {
 299                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 300                 };
 301         };
 302 };
 303
 304 &sbc {
 305         pinctrl-0 = <&qspi0_pins>;
 306         pinctrl-names = "default";
 307         status = "okay";
 308
 309         flash@0 {
 310                 compatible = "micron,mt25qu512a", "jedec,spi-nor";
 311                 reg = <0>;
 312                 m25p,fast-read;
 313                 spi-max-frequency = <50000000>;
 314                 spi-rx-bus-width = <4>;
 315
 316                 partitions {
 317                         compatible = "fixed-partitions";
 318                         #address-cells = <1>;
 319                         #size-cells = <1>;
 320
 321                         boot@0 {
 322                                 reg = <0x00000000 0x2000000>;
 323                                 read-only;
 324                         };
 325                         user@2000000 {
 326                                 reg = <0x2000000 0x2000000>;
 327                         };
 328                 };
 329         };
 330 };
 331
 332 #if SDHI
 333 &sdhi0 {
 334         pinctrl-0 = <&sdhi0_pins>;
 335         pinctrl-1 = <&sdhi0_pins_uhs>;
 336         pinctrl-names = "default", "state_uhs";
 337
 338         vmmc-supply = <&reg_3p3v>;
 339         vqmmc-supply = <&vccq_sdhi0>;
 340         bus-width = <4>;
 341         sd-uhs-sdr50;
 342         sd-uhs-sdr104;
 343         status = "okay";
 344 };
 345 #endif
 346
 347 #if EMMC
 348 &sdhi0 {
 349         pinctrl-0 = <&sdhi0_emmc_pins>;
 350         pinctrl-1 = <&sdhi0_emmc_pins>;
 351         pinctrl-names = "default", "state_uhs";
 352
 353         vmmc-supply = <&reg_3p3v>;
 354         vqmmc-supply = <&reg_1p8v>;
 355         bus-width = <8>;
 356         mmc-hs200-1_8v;
 357         non-removable;
 358         fixed-emmc-driver-type = <1>;
 359         status = "okay";
 360 };
 361 #endif
 362
 363 &wdt0 {
 364         status = "okay";
 365         timeout-sec = <60>;
 366 };
 367
 368 &wdt1 {
 369         status = "okay";
 370         timeout-sec = <60>;
 371 };