arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  10
  11 &pinctrl {
  12         pinctrl-0 = <&sound_clk_pins>;
  13         pinctrl-names = "default";
  14
  15         can0_pins: can0 {
  16                 pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
  17                          <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
  18         };
  19
  20         /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
  21         can0-stb-hog {
  22                 gpio-hog;
  23                 gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
  24                 output-low;
  25                 line-name = "can0_stb";
  26         };
  27
  28         can1_pins: can1 {
  29                 pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
  30                          <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
  31         };
  32
  33         /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
  34         can1-stb-hog {
  35                 gpio-hog;
  36                 gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
  37                 output-low;
  38                 line-name = "can1_stb";
  39         };
  40
  41         i2c0_pins: i2c0 {
  42                 pins = "RIIC0_SDA", "RIIC0_SCL";
  43                 input-enable;
  44         };
  45
  46         i2c1_pins: i2c1 {
  47                 pins = "RIIC1_SDA", "RIIC1_SCL";
  48                 input-enable;
  49         };
  50
  51         i2c3_pins: i2c3 {
  52                 pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
  53                          <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
  54         };
  55
  56         scif0_pins: scif0 {
  57                 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
  58                          <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
  59         };
  60
  61         scif2_pins: scif2 {
  62                 pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
  63                          <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
  64                          <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
  65                          <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
  66         };
  67
  68         sd1-pwr-en-hog {
  69                 gpio-hog;
  70                 gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
  71                 output-high;
  72                 line-name = "sd1_pwr_en";
  73         };
  74
  75         sdhi1_pins: sd1 {
  76                 sd1_data {
  77                         pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
  78                         power-source = <3300>;
  79                 };
  80
  81                 sd1_ctrl {
  82                         pins = "SD1_CLK", "SD1_CMD";
  83                         power-source = <3300>;
  84                 };
  85
  86                 sd1_mux {
  87                         pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
  88                 };
  89         };
  90
  91         sdhi1_pins_uhs: sd1_uhs {
  92                 sd1_data_uhs {
  93                         pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
  94                         power-source = <1800>;
  95                 };
  96
  97                 sd1_ctrl_uhs {
  98                         pins = "SD1_CLK", "SD1_CMD";
  99                         power-source = <1800>;
 100                 };
 101
 102                 sd1_mux_uhs {
 103                         pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
 104                 };
 105         };
 106
 107         sound_clk_pins: sound_clk {
 108                 pins = "AUDIO_CLK1", "AUDIO_CLK2";
 109                 input-enable;
 110         };
 111
 112         spi1_pins: spi1 {
 113                 pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
 114                          <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
 115                          <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
 116                          <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
 117         };
 118
 119         ssi0_pins: ssi0 {
 120                 pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
 121                          <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
 122                          <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
 123                          <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
 124         };
 125
 126         usb0_pins: usb0 {
 127                 pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
 128                          <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
 129                          <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
 130         };
 131
 132         usb1_pins: usb1 {
 133                 pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
 134                          <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
 135         };
 136 };
 137