1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G3S SoC
5 * Copyright (C) 2023 Renesas Electronics Corp.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
12 compatible = "renesas,r9a08g045";
21 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci";
27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
30 L3_CA55: cache-controller-0 {
34 cache-size = <0x40000>;
38 extal_clk: extal-clk {
39 compatible = "fixed-clock";
41 /* This value must be overridden by the board. */
42 clock-frequency = <0>;
46 compatible = "simple-bus";
47 interrupt-parent = <&gic>;
52 scif0: serial@1004b800 {
53 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
54 reg = <0 0x1004b800 0 0x400>;
55 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
61 interrupt-names = "eri", "rxi", "txi",
63 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
65 power-domains = <&cpg>;
66 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
70 cpg: clock-controller@11010000 {
71 compatible = "renesas,r9a08g045-cpg";
72 reg = <0 0x11010000 0 0x10000>;
73 clocks = <&extal_clk>;
74 clock-names = "extal";
77 #power-domain-cells = <0>;
80 sysc: system-controller@11020000 {
81 compatible = "renesas,r9a08g045-sysc";
82 reg = <0 0x11020000 0 0x10000>;
83 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-names = "lpm_int", "ca55stbydone_int",
88 "cm33stbyr_int", "ca55_deny";
92 pinctrl: pinctrl@11030000 {
93 compatible = "renesas,r9a08g045-pinctrl";
94 reg = <0 0x11030000 0 0x10000>;
98 #interrupt-cells = <2>;
99 gpio-ranges = <&pinctrl 0 0 152>;
100 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
101 power-domains = <&cpg>;
102 resets = <&cpg R9A08G045_GPIO_RSTN>,
103 <&cpg R9A08G045_GPIO_PORT_RESETN>,
104 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
107 sdhi0: mmc@11c00000 {
108 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
109 reg = <0x0 0x11c00000 0 0x10000>;
110 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
113 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
114 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
115 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
116 clock-names = "core", "clkh", "cd", "aclk";
117 resets = <&cpg R9A08G045_SDHI0_IXRST>;
118 power-domains = <&cpg>;
122 sdhi1: mmc@11c10000 {
123 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
124 reg = <0x0 0x11c10000 0 0x10000>;
125 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
128 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
129 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
130 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
131 clock-names = "core", "clkh", "cd", "aclk";
132 resets = <&cpg R9A08G045_SDHI1_IXRST>;
133 power-domains = <&cpg>;
137 sdhi2: mmc@11c20000 {
138 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
139 reg = <0x0 0x11c20000 0 0x10000>;
140 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
143 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
144 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
145 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
146 clock-names = "core", "clkh", "cd", "aclk";
147 resets = <&cpg R9A08G045_SDHI2_IXRST>;
148 power-domains = <&cpg>;
152 gic: interrupt-controller@12400000 {
153 compatible = "arm,gic-v3";
154 #interrupt-cells = <3>;
155 #address-cells = <0>;
156 interrupt-controller;
157 reg = <0x0 0x12400000 0 0x40000>,
158 <0x0 0x12440000 0 0x60000>;
159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
164 compatible = "arm,armv8-timer";
165 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
166 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
167 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
168 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;