arch/arm64/boot/dts/renesas/r9a07g054.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/V2L SoC
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/r9a07g054-cpg.h>
  10
  11 / {
  12         compatible = "renesas,r9a07g054";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         audio_clk1: audio1-clk {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 /* This value must be overridden by boards that provide it */
  20                 clock-frequency = <0>;
  21         };
  22
  23         audio_clk2: audio2-clk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 /* This value must be overridden by boards that provide it */
  27                 clock-frequency = <0>;
  28         };
  29
  30         /* External CAN clock - to be overridden by boards that provide it */
  31         can_clk: can-clk {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <0>;
  35         };
  36
  37         /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
  38         extal_clk: extal-clk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 /* This value must be overridden by the board */
  42                 clock-frequency = <0>;
  43         };
  44
  45         cluster0_opp: opp-table-0 {
  46                 compatible = "operating-points-v2";
  47                 opp-shared;
  48
  49                 opp-150000000 {
  50                         opp-hz = /bits/ 64 <150000000>;
  51                         opp-microvolt = <1100000>;
  52                         clock-latency-ns = <300000>;
  53                 };
  54                 opp-300000000 {
  55                         opp-hz = /bits/ 64 <300000000>;
  56                         opp-microvolt = <1100000>;
  57                         clock-latency-ns = <300000>;
  58                 };
  59                 opp-600000000 {
  60                         opp-hz = /bits/ 64 <600000000>;
  61                         opp-microvolt = <1100000>;
  62                         clock-latency-ns = <300000>;
  63                 };
  64                 opp-1200000000 {
  65                         opp-hz = /bits/ 64 <1200000000>;
  66                         opp-microvolt = <1100000>;
  67                         clock-latency-ns = <300000>;
  68                         opp-suspend;
  69                 };
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 cpu-map {
  77                         cluster0 {
  78                                 core0 {
  79                                         cpu = <&cpu0>;
  80                                 };
  81                                 core1 {
  82                                         cpu = <&cpu1>;
  83                                 };
  84                         };
  85                 };
  86
  87                 cpu0: cpu@0 {
  88                         compatible = "arm,cortex-a55";
  89                         reg = <0>;
  90                         device_type = "cpu";
  91                         #cooling-cells = <2>;
  92                         next-level-cache = <&L3_CA55>;
  93                         enable-method = "psci";
  94                         clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
  95                         operating-points-v2 = <&cluster0_opp>;
  96                 };
  97
  98                 cpu1: cpu@100 {
  99                         compatible = "arm,cortex-a55";
 100                         reg = <0x100>;
 101                         device_type = "cpu";
 102                         next-level-cache = <&L3_CA55>;
 103                         enable-method = "psci";
 104                         clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
 105                         operating-points-v2 = <&cluster0_opp>;
 106                 };
 107
 108                 L3_CA55: cache-controller-0 {
 109                         compatible = "cache";
 110                         cache-unified;
 111                         cache-size = <0x40000>;
 112                 };
 113         };
 114
 115         gpu_opp_table: opp-table-1 {
 116                 compatible = "operating-points-v2";
 117
 118                 opp-500000000 {
 119                         opp-hz = /bits/ 64 <500000000>;
 120                         opp-microvolt = <1100000>;
 121                 };
 122
 123                 opp-400000000 {
 124                         opp-hz = /bits/ 64 <400000000>;
 125                         opp-microvolt = <1100000>;
 126                 };
 127
 128                 opp-250000000 {
 129                         opp-hz = /bits/ 64 <250000000>;
 130                         opp-microvolt = <1100000>;
 131                 };
 132
 133                 opp-200000000 {
 134                         opp-hz = /bits/ 64 <200000000>;
 135                         opp-microvolt = <1100000>;
 136                 };
 137
 138                 opp-125000000 {
 139                         opp-hz = /bits/ 64 <125000000>;
 140                         opp-microvolt = <1100000>;
 141                 };
 142
 143                 opp-100000000 {
 144                         opp-hz = /bits/ 64 <100000000>;
 145                         opp-microvolt = <1100000>;
 146                 };
 147
 148                 opp-62500000 {
 149                         opp-hz = /bits/ 64 <62500000>;
 150                         opp-microvolt = <1100000>;
 151                 };
 152
 153                 opp-50000000 {
 154                         opp-hz = /bits/ 64 <50000000>;
 155                         opp-microvolt = <1100000>;
 156                 };
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         soc: soc {
 165                 compatible = "simple-bus";
 166                 interrupt-parent = <&gic>;
 167                 #address-cells = <2>;
 168                 #size-cells = <2>;
 169                 ranges;
 170
 171                 ssi0: ssi@10049c00 {
 172                         compatible = "renesas,r9a07g054-ssi",
 173                                      "renesas,rz-ssi";
 174                         reg = <0 0x10049c00 0 0x400>;
 175                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
 177                                      <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
 178                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 179                         clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
 180                                  <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
 181                                  <&audio_clk1>, <&audio_clk2>;
 182                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 183                         resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
 184                         dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 185                         dma-names = "tx", "rx";
 186                         power-domains = <&cpg>;
 187                         #sound-dai-cells = <0>;
 188                         status = "disabled";
 189                 };
 190
 191                 ssi1: ssi@1004a000 {
 192                         compatible = "renesas,r9a07g054-ssi",
 193                                      "renesas,rz-ssi";
 194                         reg = <0 0x1004a000 0 0x400>;
 195                         interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
 197                                      <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
 198                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 199                         clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
 200                                  <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
 201                                  <&audio_clk1>, <&audio_clk2>;
 202                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 203                         resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
 204                         dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 205                         dma-names = "tx", "rx";
 206                         power-domains = <&cpg>;
 207                         #sound-dai-cells = <0>;
 208                         status = "disabled";
 209                 };
 210
 211                 ssi2: ssi@1004a400 {
 212                         compatible = "renesas,r9a07g054-ssi",
 213                                      "renesas,rz-ssi";
 214                         reg = <0 0x1004a400 0 0x400>;
 215                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
 217                         interrupt-names = "int_req", "dma_rt";
 218                         clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
 219                                  <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
 220                                  <&audio_clk1>, <&audio_clk2>;
 221                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 222                         resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
 223                         dmas = <&dmac 0x265f>;
 224                         dma-names = "rt";
 225                         power-domains = <&cpg>;
 226                         #sound-dai-cells = <0>;
 227                         status = "disabled";
 228                 };
 229
 230                 ssi3: ssi@1004a800 {
 231                         compatible = "renesas,r9a07g054-ssi",
 232                                      "renesas,rz-ssi";
 233                         reg = <0 0x1004a800 0 0x400>;
 234                         interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
 236                                      <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 237                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 238                         clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
 239                                  <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
 240                                  <&audio_clk1>, <&audio_clk2>;
 241                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 242                         resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
 243                         dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 244                         dma-names = "tx", "rx";
 245                         power-domains = <&cpg>;
 246                         #sound-dai-cells = <0>;
 247                         status = "disabled";
 248                 };
 249
 250                 spi0: spi@1004ac00 {
 251                         compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
 252                         reg = <0 0x1004ac00 0 0x400>;
 253                         interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 256                         interrupt-names = "error", "rx", "tx";
 257                         clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
 258                         resets = <&cpg R9A07G054_RSPI0_RST>;
 259                         dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 260                         dma-names = "tx", "rx";
 261                         power-domains = <&cpg>;
 262                         num-cs = <1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266                 };
 267
 268                 spi1: spi@1004b000 {
 269                         compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
 270                         reg = <0 0x1004b000 0 0x400>;
 271                         interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
 274                         interrupt-names = "error", "rx", "tx";
 275                         clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
 276                         resets = <&cpg R9A07G054_RSPI1_RST>;
 277                         dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 278                         dma-names = "tx", "rx";
 279                         power-domains = <&cpg>;
 280                         num-cs = <1>;
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         status = "disabled";
 284                 };
 285
 286                 spi2: spi@1004b400 {
 287                         compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
 288                         reg = <0 0x1004b400 0 0x400>;
 289                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 292                         interrupt-names = "error", "rx", "tx";
 293                         clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
 294                         resets = <&cpg R9A07G054_RSPI2_RST>;
 295                         dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 296                         dma-names = "tx", "rx";
 297                         power-domains = <&cpg>;
 298                         num-cs = <1>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         status = "disabled";
 302                 };
 303
 304                 scif0: serial@1004b800 {
 305                         compatible = "renesas,scif-r9a07g054",
 306                                      "renesas,scif-r9a07g044";
 307                         reg = <0 0x1004b800 0 0x400>;
 308                         interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 314                         interrupt-names = "eri", "rxi", "txi",
 315                                           "bri", "dri", "tei";
 316                         clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
 317                         clock-names = "fck";
 318                         power-domains = <&cpg>;
 319                         resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
 320                         status = "disabled";
 321                 };
 322
 323                 scif1: serial@1004bc00 {
 324                         compatible = "renesas,scif-r9a07g054",
 325                                      "renesas,scif-r9a07g044";
 326                         reg = <0 0x1004bc00 0 0x400>;
 327                         interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 328                                      <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 331                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
 333                         interrupt-names = "eri", "rxi", "txi",
 334                                           "bri", "dri", "tei";
 335                         clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
 336                         clock-names = "fck";
 337                         power-domains = <&cpg>;
 338                         resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
 339                         status = "disabled";
 340                 };
 341
 342                 scif2: serial@1004c000 {
 343                         compatible = "renesas,scif-r9a07g054",
 344                                      "renesas,scif-r9a07g044";
 345                         reg = <0 0x1004c000 0 0x400>;
 346                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
 352                         interrupt-names = "eri", "rxi", "txi",
 353                                           "bri", "dri", "tei";
 354                         clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
 355                         clock-names = "fck";
 356                         power-domains = <&cpg>;
 357                         resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
 358                         status = "disabled";
 359                 };
 360
 361                 scif3: serial@1004c400 {
 362                         compatible = "renesas,scif-r9a07g054",
 363                                      "renesas,scif-r9a07g044";
 364                         reg = <0 0x1004c400 0 0x400>;
 365                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 367                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 368                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 371                         interrupt-names = "eri", "rxi", "txi",
 372                                           "bri", "dri", "tei";
 373                         clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
 374                         clock-names = "fck";
 375                         power-domains = <&cpg>;
 376                         resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
 377                         status = "disabled";
 378                 };
 379
 380                 scif4: serial@1004c800 {
 381                         compatible = "renesas,scif-r9a07g054",
 382                                      "renesas,scif-r9a07g044";
 383                         reg = <0 0x1004c800 0 0x400>;
 384                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 385                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 386                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 388                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 390                         interrupt-names = "eri", "rxi", "txi",
 391                                           "bri", "dri", "tei";
 392                         clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
 393                         clock-names = "fck";
 394                         power-domains = <&cpg>;
 395                         resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
 396                         status = "disabled";
 397                 };
 398
 399                 sci0: serial@1004d000 {
 400                         compatible = "renesas,r9a07g054-sci", "renesas,sci";
 401                         reg = <0 0x1004d000 0 0x400>;
 402                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 403                                      <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
 404                                      <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 405                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 406                         interrupt-names = "eri", "rxi", "txi", "tei";
 407                         clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
 408                         clock-names = "fck";
 409                         power-domains = <&cpg>;
 410                         resets = <&cpg R9A07G054_SCI0_RST>;
 411                         status = "disabled";
 412                 };
 413
 414                 sci1: serial@1004d400 {
 415                         compatible = "renesas,r9a07g054-sci", "renesas,sci";
 416                         reg = <0 0x1004d400 0 0x400>;
 417                         interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 418                                      <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
 419                                      <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 420                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 421                         interrupt-names = "eri", "rxi", "txi", "tei";
 422                         clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
 423                         clock-names = "fck";
 424                         power-domains = <&cpg>;
 425                         resets = <&cpg R9A07G054_SCI1_RST>;
 426                         status = "disabled";
 427                 };
 428
 429                 canfd: can@10050000 {
 430                         compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
 431                         reg = <0 0x10050000 0 0x8000>;
 432                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 434                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 435                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 436                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 437                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 438                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 440                         interrupt-names = "g_err", "g_recc",
 441                                           "ch0_err", "ch0_rec", "ch0_trx",
 442                                           "ch1_err", "ch1_rec", "ch1_trx";
 443                         clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
 444                                  <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
 445                                  <&can_clk>;
 446                         clock-names = "fck", "canfd", "can_clk";
 447                         assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
 448                         assigned-clock-rates = <50000000>;
 449                         resets = <&cpg R9A07G054_CANFD_RSTP_N>,
 450                                  <&cpg R9A07G054_CANFD_RSTC_N>;
 451                         reset-names = "rstp_n", "rstc_n";
 452                         power-domains = <&cpg>;
 453                         status = "disabled";
 454
 455                         channel0 {
 456                                 status = "disabled";
 457                         };
 458                         channel1 {
 459                                 status = "disabled";
 460                         };
 461                 };
 462
 463                 i2c0: i2c@10058000 {
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
 467                         reg = <0 0x10058000 0 0x400>;
 468                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 469                                      <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
 470                                      <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
 471                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 472                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 473                                      <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 474                                      <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 476                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 477                                           "naki", "ali", "tmoi";
 478                         clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
 479                         clock-frequency = <100000>;
 480                         resets = <&cpg R9A07G054_I2C0_MRST>;
 481                         power-domains = <&cpg>;
 482                         status = "disabled";
 483                 };
 484
 485                 i2c1: i2c@10058400 {
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                         compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
 489                         reg = <0 0x10058400 0 0x400>;
 490                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
 492                                      <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
 493                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 494                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
 498                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 499                                           "naki", "ali", "tmoi";
 500                         clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
 501                         clock-frequency = <100000>;
 502                         resets = <&cpg R9A07G054_I2C1_MRST>;
 503                         power-domains = <&cpg>;
 504                         status = "disabled";
 505                 };
 506
 507                 i2c2: i2c@10058800 {
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
 511                         reg = <0 0x10058800 0 0x400>;
 512                         interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
 513                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 514                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 515                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 520                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 521                                           "naki", "ali", "tmoi";
 522                         clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
 523                         clock-frequency = <100000>;
 524                         resets = <&cpg R9A07G054_I2C2_MRST>;
 525                         power-domains = <&cpg>;
 526                         status = "disabled";
 527                 };
 528
 529                 i2c3: i2c@10058c00 {
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
 533                         reg = <0 0x10058c00 0 0x400>;
 534                         interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
 536                                      <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 537                                      <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 542                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 543                                           "naki", "ali", "tmoi";
 544                         clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
 545                         clock-frequency = <100000>;
 546                         resets = <&cpg R9A07G054_I2C3_MRST>;
 547                         power-domains = <&cpg>;
 548                         status = "disabled";
 549                 };
 550
 551                 adc: adc@10059000 {
 552                         compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
 553                         reg = <0 0x10059000 0 0x400>;
 554                         interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
 555                         clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
 556                                  <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
 557                         clock-names = "adclk", "pclk";
 558                         resets = <&cpg R9A07G054_ADC_PRESETN>,
 559                                  <&cpg R9A07G054_ADC_ADRST_N>;
 560                         reset-names = "presetn", "adrst-n";
 561                         power-domains = <&cpg>;
 562                         status = "disabled";
 563
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566
 567                         channel@0 {
 568                                 reg = <0>;
 569                         };
 570                         channel@1 {
 571                                 reg = <1>;
 572                         };
 573                         channel@2 {
 574                                 reg = <2>;
 575                         };
 576                         channel@3 {
 577                                 reg = <3>;
 578                         };
 579                         channel@4 {
 580                                 reg = <4>;
 581                         };
 582                         channel@5 {
 583                                 reg = <5>;
 584                         };
 585                         channel@6 {
 586                                 reg = <6>;
 587                         };
 588                         channel@7 {
 589                                 reg = <7>;
 590                         };
 591                 };
 592
 593                 tsu: thermal@10059400 {
 594                         compatible = "renesas,r9a07g054-tsu",
 595                                      "renesas,rzg2l-tsu";
 596                         reg = <0 0x10059400 0 0x400>;
 597                         clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
 598                         resets = <&cpg R9A07G054_TSU_PRESETN>;
 599                         power-domains = <&cpg>;
 600                         #thermal-sensor-cells = <1>;
 601                 };
 602
 603                 sbc: spi@10060000 {
 604                         compatible = "renesas,r9a07g054-rpc-if",
 605                                      "renesas,rzg2l-rpc-if";
 606                         reg = <0 0x10060000 0 0x10000>,
 607                               <0 0x20000000 0 0x10000000>,
 608                               <0 0x10070000 0 0x10000>;
 609                         reg-names = "regs", "dirmap", "wbuf";
 610                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
 612                                  <&cpg CPG_MOD R9A07G054_SPI_CLK>;
 613                         resets = <&cpg R9A07G054_SPI_RST>;
 614                         power-domains = <&cpg>;
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                         status = "disabled";
 618                 };
 619
 620                 cpg: clock-controller@11010000 {
 621                         compatible = "renesas,r9a07g054-cpg";
 622                         reg = <0 0x11010000 0 0x10000>;
 623                         clocks = <&extal_clk>;
 624                         clock-names = "extal";
 625                         #clock-cells = <2>;
 626                         #reset-cells = <1>;
 627                         #power-domain-cells = <0>;
 628                 };
 629
 630                 sysc: system-controller@11020000 {
 631                         compatible = "renesas,r9a07g054-sysc";
 632                         reg = <0 0x11020000 0 0x10000>;
 633                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 637                         interrupt-names = "lpm_int", "ca55stbydone_int",
 638                                           "cm33stbyr_int", "ca55_deny";
 639                         status = "disabled";
 640                 };
 641
 642                 pinctrl: pinctrl@11030000 {
 643                         compatible = "renesas,r9a07g054-pinctrl",
 644                                      "renesas,r9a07g044-pinctrl";
 645                         reg = <0 0x11030000 0 0x10000>;
 646                         gpio-controller;
 647                         #gpio-cells = <2>;
 648                         #address-cells = <2>;
 649                         #interrupt-cells = <2>;
 650                         interrupt-parent = <&irqc>;
 651                         interrupt-controller;
 652                         gpio-ranges = <&pinctrl 0 0 392>;
 653                         clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
 654                         power-domains = <&cpg>;
 655                         resets = <&cpg R9A07G054_GPIO_RSTN>,
 656                                  <&cpg R9A07G054_GPIO_PORT_RESETN>,
 657                                  <&cpg R9A07G054_GPIO_SPARE_RESETN>;
 658                 };
 659
 660                 irqc: interrupt-controller@110a0000 {
 661                         compatible = "renesas,r9a07g054-irqc",
 662                                      "renesas,rzg2l-irqc";
 663                         #interrupt-cells = <2>;
 664                         #address-cells = <0>;
 665                         interrupt-controller;
 666                         reg = <0 0x110a0000 0 0x10000>;
 667                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 675                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
 709                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 710                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 711                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 712                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 713                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 714                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
 715                         interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
 716                                           "irq4", "irq5", "irq6", "irq7",
 717                                           "tint0", "tint1", "tint2", "tint3",
 718                                           "tint4", "tint5", "tint6", "tint7",
 719                                           "tint8", "tint9", "tint10", "tint11",
 720                                           "tint12", "tint13", "tint14", "tint15",
 721                                           "tint16", "tint17", "tint18", "tint19",
 722                                           "tint20", "tint21", "tint22", "tint23",
 723                                           "tint24", "tint25", "tint26", "tint27",
 724                                           "tint28", "tint29", "tint30", "tint31",
 725                                           "bus-err", "ec7tie1-0", "ec7tie2-0",
 726                                           "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
 727                                           "ec7tiovf-1";
 728                         clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
 729                                  <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
 730                         clock-names = "clk", "pclk";
 731                         power-domains = <&cpg>;
 732                         resets = <&cpg R9A07G054_IA55_RESETN>;
 733                 };
 734
 735                 dmac: dma-controller@11820000 {
 736                         compatible = "renesas,r9a07g054-dmac",
 737                                      "renesas,rz-dmac";
 738                         reg = <0 0x11820000 0 0x10000>,
 739                               <0 0x11830000 0 0x10000>;
 740                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 741                                      <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 742                                      <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 743                                      <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 744                                      <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 745                                      <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 746                                      <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 747                                      <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 748                                      <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 749                                      <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 750                                      <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 751                                      <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 752                                      <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 753                                      <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 754                                      <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 755                                      <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 756                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 757                         interrupt-names = "error",
 758                                           "ch0", "ch1", "ch2", "ch3",
 759                                           "ch4", "ch5", "ch6", "ch7",
 760                                           "ch8", "ch9", "ch10", "ch11",
 761                                           "ch12", "ch13", "ch14", "ch15";
 762                         clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
 763                                  <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
 764                         power-domains = <&cpg>;
 765                         resets = <&cpg R9A07G054_DMAC_ARESETN>,
 766                                  <&cpg R9A07G054_DMAC_RST_ASYNC>;
 767                         #dma-cells = <1>;
 768                         dma-channels = <16>;
 769                 };
 770
 771                 gpu: gpu@11840000 {
 772                         compatible = "renesas,r9a07g054-mali",
 773                                      "arm,mali-bifrost";
 774                         reg = <0x0 0x11840000 0x0 0x10000>;
 775                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 778                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 779                         interrupt-names = "job", "mmu", "gpu", "event";
 780                         clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
 781                                  <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
 782                                  <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
 783                         clock-names = "gpu", "bus", "bus_ace";
 784                         power-domains = <&cpg>;
 785                         resets = <&cpg R9A07G054_GPU_RESETN>,
 786                                  <&cpg R9A07G054_GPU_AXI_RESETN>,
 787                                  <&cpg R9A07G054_GPU_ACE_RESETN>;
 788                         reset-names = "rst", "axi_rst", "ace_rst";
 789                         operating-points-v2 = <&gpu_opp_table>;
 790                 };
 791
 792                 gic: interrupt-controller@11900000 {
 793                         compatible = "arm,gic-v3";
 794                         #interrupt-cells = <3>;
 795                         #address-cells = <0>;
 796                         interrupt-controller;
 797                         reg = <0x0 0x11900000 0 0x40000>,
 798                               <0x0 0x11940000 0 0x60000>;
 799                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 800                 };
 801
 802                 sdhi0: mmc@11c00000 {
 803                         compatible = "renesas,sdhi-r9a07g054",
 804                                      "renesas,rcar-gen3-sdhi";
 805                         reg = <0x0 0x11c00000 0 0x10000>;
 806                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 808                         clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
 809                                  <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
 810                                  <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
 811                                  <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
 812                         clock-names = "core", "clkh", "cd", "aclk";
 813                         resets = <&cpg R9A07G054_SDHI0_IXRST>;
 814                         power-domains = <&cpg>;
 815                         status = "disabled";
 816                 };
 817
 818                 sdhi1: mmc@11c10000 {
 819                         compatible = "renesas,sdhi-r9a07g054",
 820                                      "renesas,rcar-gen3-sdhi";
 821                         reg = <0x0 0x11c10000 0 0x10000>;
 822                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 823                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
 825                                  <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
 826                                  <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
 827                                  <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
 828                         clock-names = "core", "clkh", "cd", "aclk";
 829                         resets = <&cpg R9A07G054_SDHI1_IXRST>;
 830                         power-domains = <&cpg>;
 831                         status = "disabled";
 832                 };
 833
 834                 eth0: ethernet@11c20000 {
 835                         compatible = "renesas,r9a07g054-gbeth",
 836                                      "renesas,rzg2l-gbeth";
 837                         reg = <0 0x11c20000 0 0x10000>;
 838                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 839                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 840                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 841                         interrupt-names = "mux", "fil", "arp_ns";
 842                         phy-mode = "rgmii";
 843                         clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
 844                                  <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
 845                                  <&cpg CPG_CORE R9A07G054_CLK_HP>;
 846                         clock-names = "axi", "chi", "refclk";
 847                         resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
 848                         power-domains = <&cpg>;
 849                         #address-cells = <1>;
 850                         #size-cells = <0>;
 851                         status = "disabled";
 852                 };
 853
 854                 eth1: ethernet@11c30000 {
 855                         compatible = "renesas,r9a07g054-gbeth",
 856                                      "renesas,rzg2l-gbeth";
 857                         reg = <0 0x11c30000 0 0x10000>;
 858                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 859                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 860                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 861                         interrupt-names = "mux", "fil", "arp_ns";
 862                         phy-mode = "rgmii";
 863                         clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
 864                                  <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
 865                                  <&cpg CPG_CORE R9A07G054_CLK_HP>;
 866                         clock-names = "axi", "chi", "refclk";
 867                         resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
 868                         power-domains = <&cpg>;
 869                         #address-cells = <1>;
 870                         #size-cells = <0>;
 871                         status = "disabled";
 872                 };
 873
 874                 phyrst: usbphy-ctrl@11c40000 {
 875                         compatible = "renesas,r9a07g054-usbphy-ctrl",
 876                                      "renesas,rzg2l-usbphy-ctrl";
 877                         reg = <0 0x11c40000 0 0x10000>;
 878                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
 879                         resets = <&cpg R9A07G054_USB_PRESETN>;
 880                         power-domains = <&cpg>;
 881                         #reset-cells = <1>;
 882                         status = "disabled";
 883                 };
 884
 885                 ohci0: usb@11c50000 {
 886                         compatible = "generic-ohci";
 887                         reg = <0 0x11c50000 0 0x100>;
 888                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 889                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 890                                  <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
 891                         resets = <&phyrst 0>,
 892                                  <&cpg R9A07G054_USB_U2H0_HRESETN>;
 893                         phys = <&usb2_phy0 1>;
 894                         phy-names = "usb";
 895                         power-domains = <&cpg>;
 896                         status = "disabled";
 897                 };
 898
 899                 ohci1: usb@11c70000 {
 900                         compatible = "generic-ohci";
 901                         reg = <0 0x11c70000 0 0x100>;
 902                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 903                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 904                                  <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
 905                         resets = <&phyrst 1>,
 906                                  <&cpg R9A07G054_USB_U2H1_HRESETN>;
 907                         phys = <&usb2_phy1 1>;
 908                         phy-names = "usb";
 909                         power-domains = <&cpg>;
 910                         status = "disabled";
 911                 };
 912
 913                 ehci0: usb@11c50100 {
 914                         compatible = "generic-ehci";
 915                         reg = <0 0x11c50100 0 0x100>;
 916                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 917                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 918                                  <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
 919                         resets = <&phyrst 0>,
 920                                  <&cpg R9A07G054_USB_U2H0_HRESETN>;
 921                         phys = <&usb2_phy0 2>;
 922                         phy-names = "usb";
 923                         companion = <&ohci0>;
 924                         power-domains = <&cpg>;
 925                         status = "disabled";
 926                 };
 927
 928                 ehci1: usb@11c70100 {
 929                         compatible = "generic-ehci";
 930                         reg = <0 0x11c70100 0 0x100>;
 931                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 932                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 933                                  <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
 934                         resets = <&phyrst 1>,
 935                                  <&cpg R9A07G054_USB_U2H1_HRESETN>;
 936                         phys = <&usb2_phy1 2>;
 937                         phy-names = "usb";
 938                         companion = <&ohci1>;
 939                         power-domains = <&cpg>;
 940                         status = "disabled";
 941                 };
 942
 943                 usb2_phy0: usb-phy@11c50200 {
 944                         compatible = "renesas,usb2-phy-r9a07g054",
 945                                      "renesas,rzg2l-usb2-phy";
 946                         reg = <0 0x11c50200 0 0x700>;
 947                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 949                                  <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
 950                         resets = <&phyrst 0>;
 951                         #phy-cells = <1>;
 952                         power-domains = <&cpg>;
 953                         status = "disabled";
 954                 };
 955
 956                 usb2_phy1: usb-phy@11c70200 {
 957                         compatible = "renesas,usb2-phy-r9a07g054",
 958                                      "renesas,rzg2l-usb2-phy";
 959                         reg = <0 0x11c70200 0 0x700>;
 960                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 962                                  <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
 963                         resets = <&phyrst 1>;
 964                         #phy-cells = <1>;
 965                         power-domains = <&cpg>;
 966                         status = "disabled";
 967                 };
 968
 969                 hsusb: usb@11c60000 {
 970                         compatible = "renesas,usbhs-r9a07g054",
 971                                      "renesas,rza2-usbhs";
 972                         reg = <0 0x11c60000 0 0x10000>;
 973                         interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
 974                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 976                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 977                         clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
 978                                  <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
 979                         resets = <&phyrst 0>,
 980                                  <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
 981                         renesas,buswait = <7>;
 982                         phys = <&usb2_phy0 3>;
 983                         phy-names = "usb";
 984                         power-domains = <&cpg>;
 985                         status = "disabled";
 986                 };
 987
 988                 wdt0: watchdog@12800800 {
 989                         compatible = "renesas,r9a07g054-wdt",
 990                                      "renesas,rzg2l-wdt";
 991                         reg = <0 0x12800800 0 0x400>;
 992                         clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
 993                                  <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
 994                         clock-names = "pclk", "oscclk";
 995                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 997                         interrupt-names = "wdt", "perrout";
 998                         resets = <&cpg R9A07G054_WDT0_PRESETN>;
 999                         power-domains = <&cpg>;
1000                         status = "disabled";
1001                 };
1002
1003                 wdt1: watchdog@12800c00 {
1004                         compatible = "renesas,r9a07g054-wdt",
1005                                      "renesas,rzg2l-wdt";
1006                         reg = <0 0x12800C00 0 0x400>;
1007                         clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1008                                  <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1009                         clock-names = "pclk", "oscclk";
1010                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1011                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1012                         interrupt-names = "wdt", "perrout";
1013                         resets = <&cpg R9A07G054_WDT1_PRESETN>;
1014                         power-domains = <&cpg>;
1015                         status = "disabled";
1016                 };
1017
1018                 wdt2: watchdog@12800400 {
1019                         compatible = "renesas,r9a07g054-wdt",
1020                                      "renesas,rzg2l-wdt";
1021                         reg = <0 0x12800400 0 0x400>;
1022                         clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
1023                                  <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
1024                         clock-names = "pclk", "oscclk";
1025                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1027                         interrupt-names = "wdt", "perrout";
1028                         resets = <&cpg R9A07G054_WDT2_PRESETN>;
1029                         power-domains = <&cpg>;
1030                         status = "disabled";
1031                 };
1032
1033                 ostm0: timer@12801000 {
1034                         compatible = "renesas,r9a07g054-ostm",
1035                                      "renesas,ostm";
1036                         reg = <0x0 0x12801000 0x0 0x400>;
1037                         interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1038                         clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1039                         resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1040                         power-domains = <&cpg>;
1041                         status = "disabled";
1042                 };
1043
1044                 ostm1: timer@12801400 {
1045                         compatible = "renesas,r9a07g054-ostm",
1046                                      "renesas,ostm";
1047                         reg = <0x0 0x12801400 0x0 0x400>;
1048                         interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1049                         clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1050                         resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1051                         power-domains = <&cpg>;
1052                         status = "disabled";
1053                 };
1054
1055                 ostm2: timer@12801800 {
1056                         compatible = "renesas,r9a07g054-ostm",
1057                                      "renesas,ostm";
1058                         reg = <0x0 0x12801800 0x0 0x400>;
1059                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1060                         clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1061                         resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1062                         power-domains = <&cpg>;
1063                         status = "disabled";
1064                 };
1065         };
1066
1067         thermal-zones {
1068                 cpu-thermal {
1069                         polling-delay-passive = <250>;
1070                         polling-delay = <1000>;
1071                         thermal-sensors = <&tsu 0>;
1072                         sustainable-power = <717>;
1073
1074                         cooling-maps {
1075                                 map0 {
1076                                         trip = <&target>;
1077                                         cooling-device = <&cpu0 0 2>;
1078                                         contribution = <1024>;
1079                                 };
1080                         };
1081
1082                         trips {
1083                                 sensor_crit: sensor-crit {
1084                                         temperature = <125000>;
1085                                         hysteresis = <1000>;
1086                                         type = "critical";
1087                                 };
1088
1089                                 target: trip-point {
1090                                         temperature = <100000>;
1091                                         hysteresis = <1000>;
1092                                         type = "passive";
1093                                 };
1094                         };
1095                 };
1096         };
1097
1098         timer {
1099                 compatible = "arm,armv8-timer";
1100                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1101                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1102                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1103                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1104         };
1105 };