arch/arm64/boot/dts/renesas/r9a07g044.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/r9a07g044-cpg.h>
  10
  11 / {
  12         compatible = "renesas,r9a07g044";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         audio_clk1: audio1-clk {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 /* This value must be overridden by boards that provide it */
  20                 clock-frequency = <0>;
  21         };
  22
  23         audio_clk2: audio2-clk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 /* This value must be overridden by boards that provide it */
  27                 clock-frequency = <0>;
  28         };
  29
  30         /* External CAN clock - to be overridden by boards that provide it */
  31         can_clk: can-clk {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <0>;
  35         };
  36
  37         /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
  38         extal_clk: extal-clk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 /* This value must be overridden by the board */
  42                 clock-frequency = <0>;
  43         };
  44
  45         cluster0_opp: opp-table-0 {
  46                 compatible = "operating-points-v2";
  47                 opp-shared;
  48
  49                 opp-150000000 {
  50                         opp-hz = /bits/ 64 <150000000>;
  51                         opp-microvolt = <1100000>;
  52                         clock-latency-ns = <300000>;
  53                 };
  54                 opp-300000000 {
  55                         opp-hz = /bits/ 64 <300000000>;
  56                         opp-microvolt = <1100000>;
  57                         clock-latency-ns = <300000>;
  58                 };
  59                 opp-600000000 {
  60                         opp-hz = /bits/ 64 <600000000>;
  61                         opp-microvolt = <1100000>;
  62                         clock-latency-ns = <300000>;
  63                 };
  64                 opp-1200000000 {
  65                         opp-hz = /bits/ 64 <1200000000>;
  66                         opp-microvolt = <1100000>;
  67                         clock-latency-ns = <300000>;
  68                         opp-suspend;
  69                 };
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 cpu-map {
  77                         cluster0 {
  78                                 core0 {
  79                                         cpu = <&cpu0>;
  80                                 };
  81                                 core1 {
  82                                         cpu = <&cpu1>;
  83                                 };
  84                         };
  85                 };
  86
  87                 cpu0: cpu@0 {
  88                         compatible = "arm,cortex-a55";
  89                         reg = <0>;
  90                         device_type = "cpu";
  91                         #cooling-cells = <2>;
  92                         next-level-cache = <&L3_CA55>;
  93                         enable-method = "psci";
  94                         clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
  95                         operating-points-v2 = <&cluster0_opp>;
  96                 };
  97
  98                 cpu1: cpu@100 {
  99                         compatible = "arm,cortex-a55";
 100                         reg = <0x100>;
 101                         device_type = "cpu";
 102                         next-level-cache = <&L3_CA55>;
 103                         enable-method = "psci";
 104                         clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
 105                         operating-points-v2 = <&cluster0_opp>;
 106                 };
 107
 108                 L3_CA55: cache-controller-0 {
 109                         compatible = "cache";
 110                         cache-unified;
 111                         cache-size = <0x40000>;
 112                 };
 113         };
 114
 115         gpu_opp_table: opp-table-1 {
 116                 compatible = "operating-points-v2";
 117
 118                 opp-500000000 {
 119                         opp-hz = /bits/ 64 <500000000>;
 120                         opp-microvolt = <1100000>;
 121                 };
 122
 123                 opp-400000000 {
 124                         opp-hz = /bits/ 64 <400000000>;
 125                         opp-microvolt = <1100000>;
 126                 };
 127
 128                 opp-250000000 {
 129                         opp-hz = /bits/ 64 <250000000>;
 130                         opp-microvolt = <1100000>;
 131                 };
 132
 133                 opp-200000000 {
 134                         opp-hz = /bits/ 64 <200000000>;
 135                         opp-microvolt = <1100000>;
 136                 };
 137
 138                 opp-125000000 {
 139                         opp-hz = /bits/ 64 <125000000>;
 140                         opp-microvolt = <1100000>;
 141                 };
 142
 143                 opp-100000000 {
 144                         opp-hz = /bits/ 64 <100000000>;
 145                         opp-microvolt = <1100000>;
 146                 };
 147
 148                 opp-62500000 {
 149                         opp-hz = /bits/ 64 <62500000>;
 150                         opp-microvolt = <1100000>;
 151                 };
 152
 153                 opp-50000000 {
 154                         opp-hz = /bits/ 64 <50000000>;
 155                         opp-microvolt = <1100000>;
 156                 };
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         soc: soc {
 165                 compatible = "simple-bus";
 166                 interrupt-parent = <&gic>;
 167                 #address-cells = <2>;
 168                 #size-cells = <2>;
 169                 ranges;
 170
 171                 ssi0: ssi@10049c00 {
 172                         compatible = "renesas,r9a07g044-ssi",
 173                                      "renesas,rz-ssi";
 174                         reg = <0 0x10049c00 0 0x400>;
 175                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
 177                                      <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
 178                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 179                         clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
 180                                  <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
 181                                  <&audio_clk1>, <&audio_clk2>;
 182                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 183                         resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
 184                         dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 185                         dma-names = "tx", "rx";
 186                         power-domains = <&cpg>;
 187                         #sound-dai-cells = <0>;
 188                         status = "disabled";
 189                 };
 190
 191                 ssi1: ssi@1004a000 {
 192                         compatible = "renesas,r9a07g044-ssi",
 193                                      "renesas,rz-ssi";
 194                         reg = <0 0x1004a000 0 0x400>;
 195                         interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
 197                                      <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
 198                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 199                         clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
 200                                  <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
 201                                  <&audio_clk1>, <&audio_clk2>;
 202                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 203                         resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
 204                         dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 205                         dma-names = "tx", "rx";
 206                         power-domains = <&cpg>;
 207                         #sound-dai-cells = <0>;
 208                         status = "disabled";
 209                 };
 210
 211                 ssi2: ssi@1004a400 {
 212                         compatible = "renesas,r9a07g044-ssi",
 213                                      "renesas,rz-ssi";
 214                         reg = <0 0x1004a400 0 0x400>;
 215                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
 217                         interrupt-names = "int_req", "dma_rt";
 218                         clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
 219                                  <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
 220                                  <&audio_clk1>, <&audio_clk2>;
 221                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 222                         resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
 223                         dmas = <&dmac 0x265f>;
 224                         dma-names = "rt";
 225                         power-domains = <&cpg>;
 226                         #sound-dai-cells = <0>;
 227                         status = "disabled";
 228                 };
 229
 230                 ssi3: ssi@1004a800 {
 231                         compatible = "renesas,r9a07g044-ssi",
 232                                      "renesas,rz-ssi";
 233                         reg = <0 0x1004a800 0 0x400>;
 234                         interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
 236                                      <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 237                         interrupt-names = "int_req", "dma_rx", "dma_tx";
 238                         clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
 239                                  <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
 240                                  <&audio_clk1>, <&audio_clk2>;
 241                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 242                         resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
 243                         dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 244                         dma-names = "tx", "rx";
 245                         power-domains = <&cpg>;
 246                         #sound-dai-cells = <0>;
 247                         status = "disabled";
 248                 };
 249
 250                 spi0: spi@1004ac00 {
 251                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 252                         reg = <0 0x1004ac00 0 0x400>;
 253                         interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 256                         interrupt-names = "error", "rx", "tx";
 257                         clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
 258                         resets = <&cpg R9A07G044_RSPI0_RST>;
 259                         dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 260                         dma-names = "tx", "rx";
 261                         power-domains = <&cpg>;
 262                         num-cs = <1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266                 };
 267
 268                 spi1: spi@1004b000 {
 269                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 270                         reg = <0 0x1004b000 0 0x400>;
 271                         interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
 274                         interrupt-names = "error", "rx", "tx";
 275                         clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
 276                         resets = <&cpg R9A07G044_RSPI1_RST>;
 277                         dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 278                         dma-names = "tx", "rx";
 279                         power-domains = <&cpg>;
 280                         num-cs = <1>;
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         status = "disabled";
 284                 };
 285
 286                 spi2: spi@1004b400 {
 287                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 288                         reg = <0 0x1004b400 0 0x400>;
 289                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 292                         interrupt-names = "error", "rx", "tx";
 293                         clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
 294                         resets = <&cpg R9A07G044_RSPI2_RST>;
 295                         dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 296                         dma-names = "tx", "rx";
 297                         power-domains = <&cpg>;
 298                         num-cs = <1>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         status = "disabled";
 302                 };
 303
 304                 scif0: serial@1004b800 {
 305                         compatible = "renesas,scif-r9a07g044";
 306                         reg = <0 0x1004b800 0 0x400>;
 307                         interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 313                         interrupt-names = "eri", "rxi", "txi",
 314                                           "bri", "dri", "tei";
 315                         clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
 316                         clock-names = "fck";
 317                         power-domains = <&cpg>;
 318                         resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
 319                         status = "disabled";
 320                 };
 321
 322                 scif1: serial@1004bc00 {
 323                         compatible = "renesas,scif-r9a07g044";
 324                         reg = <0 0x1004bc00 0 0x400>;
 325                         interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 326                                      <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 327                                      <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
 328                                      <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
 331                         interrupt-names = "eri", "rxi", "txi",
 332                                           "bri", "dri", "tei";
 333                         clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
 334                         clock-names = "fck";
 335                         power-domains = <&cpg>;
 336                         resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
 337                         status = "disabled";
 338                 };
 339
 340                 scif2: serial@1004c000 {
 341                         compatible = "renesas,scif-r9a07g044";
 342                         reg = <0 0x1004c000 0 0x400>;
 343                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
 349                         interrupt-names = "eri", "rxi", "txi",
 350                                           "bri", "dri", "tei";
 351                         clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
 352                         clock-names = "fck";
 353                         power-domains = <&cpg>;
 354                         resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
 355                         status = "disabled";
 356                 };
 357
 358                 scif3: serial@1004c400 {
 359                         compatible = "renesas,scif-r9a07g044";
 360                         reg = <0 0x1004c400 0 0x400>;
 361                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 367                         interrupt-names = "eri", "rxi", "txi",
 368                                           "bri", "dri", "tei";
 369                         clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
 370                         clock-names = "fck";
 371                         power-domains = <&cpg>;
 372                         resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
 373                         status = "disabled";
 374                 };
 375
 376                 scif4: serial@1004c800 {
 377                         compatible = "renesas,scif-r9a07g044";
 378                         reg = <0 0x1004c800 0 0x400>;
 379                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 380                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 381                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 382                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 383                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 384                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 385                         interrupt-names = "eri", "rxi", "txi",
 386                                           "bri", "dri", "tei";
 387                         clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
 388                         clock-names = "fck";
 389                         power-domains = <&cpg>;
 390                         resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
 391                         status = "disabled";
 392                 };
 393
 394                 sci0: serial@1004d000 {
 395                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 396                         reg = <0 0x1004d000 0 0x400>;
 397                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 398                                      <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
 399                                      <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 400                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 401                         interrupt-names = "eri", "rxi", "txi", "tei";
 402                         clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
 403                         clock-names = "fck";
 404                         power-domains = <&cpg>;
 405                         resets = <&cpg R9A07G044_SCI0_RST>;
 406                         status = "disabled";
 407                 };
 408
 409                 sci1: serial@1004d400 {
 410                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 411                         reg = <0 0x1004d400 0 0x400>;
 412                         interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 413                                      <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
 414                                      <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 415                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 416                         interrupt-names = "eri", "rxi", "txi", "tei";
 417                         clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
 418                         clock-names = "fck";
 419                         power-domains = <&cpg>;
 420                         resets = <&cpg R9A07G044_SCI1_RST>;
 421                         status = "disabled";
 422                 };
 423
 424                 canfd: can@10050000 {
 425                         compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
 426                         reg = <0 0x10050000 0 0x8000>;
 427                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 428                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 429                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 430                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 431                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 434                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 435                         interrupt-names = "g_err", "g_recc",
 436                                           "ch0_err", "ch0_rec", "ch0_trx",
 437                                           "ch1_err", "ch1_rec", "ch1_trx";
 438                         clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
 439                                  <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
 440                                  <&can_clk>;
 441                         clock-names = "fck", "canfd", "can_clk";
 442                         assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
 443                         assigned-clock-rates = <50000000>;
 444                         resets = <&cpg R9A07G044_CANFD_RSTP_N>,
 445                                  <&cpg R9A07G044_CANFD_RSTC_N>;
 446                         reset-names = "rstp_n", "rstc_n";
 447                         power-domains = <&cpg>;
 448                         status = "disabled";
 449
 450                         channel0 {
 451                                 status = "disabled";
 452                         };
 453                         channel1 {
 454                                 status = "disabled";
 455                         };
 456                 };
 457
 458                 i2c0: i2c@10058000 {
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 462                         reg = <0 0x10058000 0 0x400>;
 463                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 464                                      <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
 465                                      <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
 466                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 467                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 468                                      <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 469                                      <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 470                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 471                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 472                                           "naki", "ali", "tmoi";
 473                         clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
 474                         clock-frequency = <100000>;
 475                         resets = <&cpg R9A07G044_I2C0_MRST>;
 476                         power-domains = <&cpg>;
 477                         status = "disabled";
 478                 };
 479
 480                 i2c1: i2c@10058400 {
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 484                         reg = <0 0x10058400 0 0x400>;
 485                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 486                                      <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
 487                                      <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
 488                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
 493                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 494                                           "naki", "ali", "tmoi";
 495                         clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
 496                         clock-frequency = <100000>;
 497                         resets = <&cpg R9A07G044_I2C1_MRST>;
 498                         power-domains = <&cpg>;
 499                         status = "disabled";
 500                 };
 501
 502                 i2c2: i2c@10058800 {
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 506                         reg = <0 0x10058800 0 0x400>;
 507                         interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
 508                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 509                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 510                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 511                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 512                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
 513                                      <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 515                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 516                                           "naki", "ali", "tmoi";
 517                         clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
 518                         clock-frequency = <100000>;
 519                         resets = <&cpg R9A07G044_I2C2_MRST>;
 520                         power-domains = <&cpg>;
 521                         status = "disabled";
 522                 };
 523
 524                 i2c3: i2c@10058c00 {
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 528                         reg = <0 0x10058c00 0 0x400>;
 529                         interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 530                                      <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
 531                                      <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 532                                      <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 537                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 538                                           "naki", "ali", "tmoi";
 539                         clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
 540                         clock-frequency = <100000>;
 541                         resets = <&cpg R9A07G044_I2C3_MRST>;
 542                         power-domains = <&cpg>;
 543                         status = "disabled";
 544                 };
 545
 546                 adc: adc@10059000 {
 547                         compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
 548                         reg = <0 0x10059000 0 0x400>;
 549                         interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
 550                         clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
 551                                  <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
 552                         clock-names = "adclk", "pclk";
 553                         resets = <&cpg R9A07G044_ADC_PRESETN>,
 554                                  <&cpg R9A07G044_ADC_ADRST_N>;
 555                         reset-names = "presetn", "adrst-n";
 556                         power-domains = <&cpg>;
 557                         status = "disabled";
 558
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561
 562                         channel@0 {
 563                                 reg = <0>;
 564                         };
 565                         channel@1 {
 566                                 reg = <1>;
 567                         };
 568                         channel@2 {
 569                                 reg = <2>;
 570                         };
 571                         channel@3 {
 572                                 reg = <3>;
 573                         };
 574                         channel@4 {
 575                                 reg = <4>;
 576                         };
 577                         channel@5 {
 578                                 reg = <5>;
 579                         };
 580                         channel@6 {
 581                                 reg = <6>;
 582                         };
 583                         channel@7 {
 584                                 reg = <7>;
 585                         };
 586                 };
 587
 588                 tsu: thermal@10059400 {
 589                         compatible = "renesas,r9a07g044-tsu",
 590                                      "renesas,rzg2l-tsu";
 591                         reg = <0 0x10059400 0 0x400>;
 592                         clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
 593                         resets = <&cpg R9A07G044_TSU_PRESETN>;
 594                         power-domains = <&cpg>;
 595                         #thermal-sensor-cells = <1>;
 596                 };
 597
 598                 sbc: spi@10060000 {
 599                         compatible = "renesas,r9a07g044-rpc-if",
 600                                      "renesas,rzg2l-rpc-if";
 601                         reg = <0 0x10060000 0 0x10000>,
 602                               <0 0x20000000 0 0x10000000>,
 603                               <0 0x10070000 0 0x10000>;
 604                         reg-names = "regs", "dirmap", "wbuf";
 605                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
 607                                  <&cpg CPG_MOD R9A07G044_SPI_CLK>;
 608                         resets = <&cpg R9A07G044_SPI_RST>;
 609                         power-domains = <&cpg>;
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         status = "disabled";
 613                 };
 614
 615                 cpg: clock-controller@11010000 {
 616                         compatible = "renesas,r9a07g044-cpg";
 617                         reg = <0 0x11010000 0 0x10000>;
 618                         clocks = <&extal_clk>;
 619                         clock-names = "extal";
 620                         #clock-cells = <2>;
 621                         #reset-cells = <1>;
 622                         #power-domain-cells = <0>;
 623                 };
 624
 625                 sysc: system-controller@11020000 {
 626                         compatible = "renesas,r9a07g044-sysc";
 627                         reg = <0 0x11020000 0 0x10000>;
 628                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 632                         interrupt-names = "lpm_int", "ca55stbydone_int",
 633                                           "cm33stbyr_int", "ca55_deny";
 634                         status = "disabled";
 635                 };
 636
 637                 pinctrl: pinctrl@11030000 {
 638                         compatible = "renesas,r9a07g044-pinctrl";
 639                         reg = <0 0x11030000 0 0x10000>;
 640                         gpio-controller;
 641                         #gpio-cells = <2>;
 642                         #address-cells = <2>;
 643                         #interrupt-cells = <2>;
 644                         interrupt-parent = <&irqc>;
 645                         interrupt-controller;
 646                         gpio-ranges = <&pinctrl 0 0 392>;
 647                         clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
 648                         power-domains = <&cpg>;
 649                         resets = <&cpg R9A07G044_GPIO_RSTN>,
 650                                  <&cpg R9A07G044_GPIO_PORT_RESETN>,
 651                                  <&cpg R9A07G044_GPIO_SPARE_RESETN>;
 652                 };
 653
 654                 irqc: interrupt-controller@110a0000 {
 655                         compatible = "renesas,r9a07g044-irqc",
 656                                      "renesas,rzg2l-irqc";
 657                         #interrupt-cells = <2>;
 658                         #address-cells = <0>;
 659                         interrupt-controller;
 660                         reg = <0 0x110a0000 0 0x10000>;
 661                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 665                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 666                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 675                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
 703                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 704                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 705                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 706                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 707                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 708                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
 709                         interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
 710                                           "irq4", "irq5", "irq6", "irq7",
 711                                           "tint0", "tint1", "tint2", "tint3",
 712                                           "tint4", "tint5", "tint6", "tint7",
 713                                           "tint8", "tint9", "tint10", "tint11",
 714                                           "tint12", "tint13", "tint14", "tint15",
 715                                           "tint16", "tint17", "tint18", "tint19",
 716                                           "tint20", "tint21", "tint22", "tint23",
 717                                           "tint24", "tint25", "tint26", "tint27",
 718                                           "tint28", "tint29", "tint30", "tint31",
 719                                           "bus-err", "ec7tie1-0", "ec7tie2-0",
 720                                           "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
 721                                           "ec7tiovf-1";
 722                         clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
 723                                  <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
 724                         clock-names = "clk", "pclk";
 725                         power-domains = <&cpg>;
 726                         resets = <&cpg R9A07G044_IA55_RESETN>;
 727                 };
 728
 729                 dmac: dma-controller@11820000 {
 730                         compatible = "renesas,r9a07g044-dmac",
 731                                      "renesas,rz-dmac";
 732                         reg = <0 0x11820000 0 0x10000>,
 733                               <0 0x11830000 0 0x10000>;
 734                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 735                                      <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 736                                      <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 737                                      <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 738                                      <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 739                                      <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 740                                      <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 741                                      <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 742                                      <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 743                                      <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 744                                      <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 745                                      <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 746                                      <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 747                                      <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 748                                      <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 749                                      <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 750                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 751                         interrupt-names = "error",
 752                                           "ch0", "ch1", "ch2", "ch3",
 753                                           "ch4", "ch5", "ch6", "ch7",
 754                                           "ch8", "ch9", "ch10", "ch11",
 755                                           "ch12", "ch13", "ch14", "ch15";
 756                         clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
 757                                  <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
 758                         power-domains = <&cpg>;
 759                         resets = <&cpg R9A07G044_DMAC_ARESETN>,
 760                                  <&cpg R9A07G044_DMAC_RST_ASYNC>;
 761                         #dma-cells = <1>;
 762                         dma-channels = <16>;
 763                 };
 764
 765                 gpu: gpu@11840000 {
 766                         compatible = "renesas,r9a07g044-mali",
 767                                      "arm,mali-bifrost";
 768                         reg = <0x0 0x11840000 0x0 0x10000>;
 769                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 770                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 771                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 772                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 773                         interrupt-names = "job", "mmu", "gpu", "event";
 774                         clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
 775                                  <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
 776                                  <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
 777                         clock-names = "gpu", "bus", "bus_ace";
 778                         power-domains = <&cpg>;
 779                         resets = <&cpg R9A07G044_GPU_RESETN>,
 780                                  <&cpg R9A07G044_GPU_AXI_RESETN>,
 781                                  <&cpg R9A07G044_GPU_ACE_RESETN>;
 782                         reset-names = "rst", "axi_rst", "ace_rst";
 783                         operating-points-v2 = <&gpu_opp_table>;
 784                 };
 785
 786                 gic: interrupt-controller@11900000 {
 787                         compatible = "arm,gic-v3";
 788                         #interrupt-cells = <3>;
 789                         #address-cells = <0>;
 790                         interrupt-controller;
 791                         reg = <0x0 0x11900000 0 0x40000>,
 792                               <0x0 0x11940000 0 0x60000>;
 793                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 794                 };
 795
 796                 sdhi0: mmc@11c00000 {
 797                         compatible = "renesas,sdhi-r9a07g044",
 798                                      "renesas,rcar-gen3-sdhi";
 799                         reg = <0x0 0x11c00000 0 0x10000>;
 800                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 802                         clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
 803                                  <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
 804                                  <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 805                                  <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
 806                         clock-names = "core", "clkh", "cd", "aclk";
 807                         resets = <&cpg R9A07G044_SDHI0_IXRST>;
 808                         power-domains = <&cpg>;
 809                         status = "disabled";
 810                 };
 811
 812                 sdhi1: mmc@11c10000 {
 813                         compatible = "renesas,sdhi-r9a07g044",
 814                                      "renesas,rcar-gen3-sdhi";
 815                         reg = <0x0 0x11c10000 0 0x10000>;
 816                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 818                         clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
 819                                  <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
 820                                  <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 821                                  <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
 822                         clock-names = "core", "clkh", "cd", "aclk";
 823                         resets = <&cpg R9A07G044_SDHI1_IXRST>;
 824                         power-domains = <&cpg>;
 825                         status = "disabled";
 826                 };
 827
 828                 eth0: ethernet@11c20000 {
 829                         compatible = "renesas,r9a07g044-gbeth",
 830                                      "renesas,rzg2l-gbeth";
 831                         reg = <0 0x11c20000 0 0x10000>;
 832                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 833                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 834                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 835                         interrupt-names = "mux", "fil", "arp_ns";
 836                         phy-mode = "rgmii";
 837                         clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
 838                                  <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
 839                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 840                         clock-names = "axi", "chi", "refclk";
 841                         resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
 842                         power-domains = <&cpg>;
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                         status = "disabled";
 846                 };
 847
 848                 eth1: ethernet@11c30000 {
 849                         compatible = "renesas,r9a07g044-gbeth",
 850                                      "renesas,rzg2l-gbeth";
 851                         reg = <0 0x11c30000 0 0x10000>;
 852                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 853                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 854                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 855                         interrupt-names = "mux", "fil", "arp_ns";
 856                         phy-mode = "rgmii";
 857                         clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
 858                                  <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
 859                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 860                         clock-names = "axi", "chi", "refclk";
 861                         resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
 862                         power-domains = <&cpg>;
 863                         #address-cells = <1>;
 864                         #size-cells = <0>;
 865                         status = "disabled";
 866                 };
 867
 868                 phyrst: usbphy-ctrl@11c40000 {
 869                         compatible = "renesas,r9a07g044-usbphy-ctrl",
 870                                      "renesas,rzg2l-usbphy-ctrl";
 871                         reg = <0 0x11c40000 0 0x10000>;
 872                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
 873                         resets = <&cpg R9A07G044_USB_PRESETN>;
 874                         power-domains = <&cpg>;
 875                         #reset-cells = <1>;
 876                         status = "disabled";
 877                 };
 878
 879                 ohci0: usb@11c50000 {
 880                         compatible = "generic-ohci";
 881                         reg = <0 0x11c50000 0 0x100>;
 882                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 883                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 884                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 885                         resets = <&phyrst 0>,
 886                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 887                         phys = <&usb2_phy0 1>;
 888                         phy-names = "usb";
 889                         power-domains = <&cpg>;
 890                         status = "disabled";
 891                 };
 892
 893                 ohci1: usb@11c70000 {
 894                         compatible = "generic-ohci";
 895                         reg = <0 0x11c70000 0 0x100>;
 896                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 898                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 899                         resets = <&phyrst 1>,
 900                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 901                         phys = <&usb2_phy1 1>;
 902                         phy-names = "usb";
 903                         power-domains = <&cpg>;
 904                         status = "disabled";
 905                 };
 906
 907                 ehci0: usb@11c50100 {
 908                         compatible = "generic-ehci";
 909                         reg = <0 0x11c50100 0 0x100>;
 910                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 912                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 913                         resets = <&phyrst 0>,
 914                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 915                         phys = <&usb2_phy0 2>;
 916                         phy-names = "usb";
 917                         companion = <&ohci0>;
 918                         power-domains = <&cpg>;
 919                         status = "disabled";
 920                 };
 921
 922                 ehci1: usb@11c70100 {
 923                         compatible = "generic-ehci";
 924                         reg = <0 0x11c70100 0 0x100>;
 925                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 926                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 927                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 928                         resets = <&phyrst 1>,
 929                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 930                         phys = <&usb2_phy1 2>;
 931                         phy-names = "usb";
 932                         companion = <&ohci1>;
 933                         power-domains = <&cpg>;
 934                         status = "disabled";
 935                 };
 936
 937                 usb2_phy0: usb-phy@11c50200 {
 938                         compatible = "renesas,usb2-phy-r9a07g044",
 939                                      "renesas,rzg2l-usb2-phy";
 940                         reg = <0 0x11c50200 0 0x700>;
 941                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 942                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 943                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 944                         resets = <&phyrst 0>;
 945                         #phy-cells = <1>;
 946                         power-domains = <&cpg>;
 947                         status = "disabled";
 948                 };
 949
 950                 usb2_phy1: usb-phy@11c70200 {
 951                         compatible = "renesas,usb2-phy-r9a07g044",
 952                                      "renesas,rzg2l-usb2-phy";
 953                         reg = <0 0x11c70200 0 0x700>;
 954                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 955                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 956                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 957                         resets = <&phyrst 1>;
 958                         #phy-cells = <1>;
 959                         power-domains = <&cpg>;
 960                         status = "disabled";
 961                 };
 962
 963                 hsusb: usb@11c60000 {
 964                         compatible = "renesas,usbhs-r9a07g044",
 965                                      "renesas,rza2-usbhs";
 966                         reg = <0 0x11c60000 0 0x10000>;
 967                         interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
 968                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 969                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 970                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 971                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 972                                  <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
 973                         resets = <&phyrst 0>,
 974                                  <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
 975                         renesas,buswait = <7>;
 976                         phys = <&usb2_phy0 3>;
 977                         phy-names = "usb";
 978                         power-domains = <&cpg>;
 979                         status = "disabled";
 980                 };
 981
 982                 wdt0: watchdog@12800800 {
 983                         compatible = "renesas,r9a07g044-wdt",
 984                                      "renesas,rzg2l-wdt";
 985                         reg = <0 0x12800800 0 0x400>;
 986                         clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
 987                                  <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
 988                         clock-names = "pclk", "oscclk";
 989                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 991                         interrupt-names = "wdt", "perrout";
 992                         resets = <&cpg R9A07G044_WDT0_PRESETN>;
 993                         power-domains = <&cpg>;
 994                         status = "disabled";
 995                 };
 996
 997                 wdt1: watchdog@12800c00 {
 998                         compatible = "renesas,r9a07g044-wdt",
 999                                      "renesas,rzg2l-wdt";
1000                         reg = <0 0x12800C00 0 0x400>;
1001                         clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1002                                  <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1003                         clock-names = "pclk", "oscclk";
1004                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1005                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1006                         interrupt-names = "wdt", "perrout";
1007                         resets = <&cpg R9A07G044_WDT1_PRESETN>;
1008                         power-domains = <&cpg>;
1009                         status = "disabled";
1010                 };
1011
1012                 wdt2: watchdog@12800400 {
1013                         compatible = "renesas,r9a07g044-wdt",
1014                                      "renesas,rzg2l-wdt";
1015                         reg = <0 0x12800400 0 0x400>;
1016                         clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
1017                                  <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
1018                         clock-names = "pclk", "oscclk";
1019                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1020                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1021                         interrupt-names = "wdt", "perrout";
1022                         resets = <&cpg R9A07G044_WDT2_PRESETN>;
1023                         power-domains = <&cpg>;
1024                         status = "disabled";
1025                 };
1026
1027                 ostm0: timer@12801000 {
1028                         compatible = "renesas,r9a07g044-ostm",
1029                                      "renesas,ostm";
1030                         reg = <0x0 0x12801000 0x0 0x400>;
1031                         interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1032                         clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1033                         resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1034                         power-domains = <&cpg>;
1035                         status = "disabled";
1036                 };
1037
1038                 ostm1: timer@12801400 {
1039                         compatible = "renesas,r9a07g044-ostm",
1040                                      "renesas,ostm";
1041                         reg = <0x0 0x12801400 0x0 0x400>;
1042                         interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1043                         clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1044                         resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1045                         power-domains = <&cpg>;
1046                         status = "disabled";
1047                 };
1048
1049                 ostm2: timer@12801800 {
1050                         compatible = "renesas,r9a07g044-ostm",
1051                                      "renesas,ostm";
1052                         reg = <0x0 0x12801800 0x0 0x400>;
1053                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1054                         clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1055                         resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1056                         power-domains = <&cpg>;
1057                         status = "disabled";
1058                 };
1059         };
1060
1061         thermal-zones {
1062                 cpu-thermal {
1063                         polling-delay-passive = <250>;
1064                         polling-delay = <1000>;
1065                         thermal-sensors = <&tsu 0>;
1066                         sustainable-power = <717>;
1067
1068                         cooling-maps {
1069                                 map0 {
1070                                         trip = <&target>;
1071                                         cooling-device = <&cpu0 0 2>;
1072                                         contribution = <1024>;
1073                                 };
1074                         };
1075
1076                         trips {
1077                                 sensor_crit: sensor-crit {
1078                                         temperature = <125000>;
1079                                         hysteresis = <1000>;
1080                                         type = "critical";
1081                                 };
1082
1083                                 target: trip-point {
1084                                         temperature = <100000>;
1085                                         hysteresis = <1000>;
1086                                         type = "passive";
1087                                 };
1088                         };
1089                 };
1090         };
1091
1092         timer {
1093                 compatible = "arm,armv8-timer";
1094                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1095                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1096                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1097                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1098         };
1099 };