arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2UL SoC
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 #define SOC_PERIPHERAL_IRQ(nr)          GIC_SPI nr
  11
  12 #include "r9a07g043.dtsi"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a55";
  21                         reg = <0>;
  22                         device_type = "cpu";
  23                         #cooling-cells = <2>;
  24                         next-level-cache = <&L3_CA55>;
  25                         enable-method = "psci";
  26                         clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
  27                         operating-points-v2 = <&cluster0_opp>;
  28                 };
  29
  30                 L3_CA55: cache-controller-0 {
  31                         compatible = "cache";
  32                         cache-unified;
  33                         cache-size = <0x40000>;
  34                         cache-level = <3>;
  35                 };
  36         };
  37
  38         pmu {
  39                 compatible = "arm,cortex-a55-pmu";
  40                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  41         };
  42
  43         psci {
  44                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  45                 method = "smc";
  46         };
  47
  48         timer {
  49                 compatible = "arm,armv8-timer";
  50                 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  51                                       <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  52                                       <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  53                                       <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  54         };
  55 };
  56
  57 &pinctrl {
  58         interrupt-parent = <&irqc>;
  59 };
  60
  61 &soc {
  62         interrupt-parent = <&gic>;
  63
  64         irqc: interrupt-controller@110a0000 {
  65                 compatible = "renesas,r9a07g043u-irqc",
  66                              "renesas,rzg2l-irqc";
  67                 reg = <0 0x110a0000 0 0x10000>;
  68                 #interrupt-cells = <2>;
  69                 #address-cells = <0>;
  70                 interrupt-controller;
  71                 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
  72                              <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
  73                              <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
  74                              <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
  75                              <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
  76                              <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
  77                              <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
  78                              <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
  79                              <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
  80                              <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
  81                              <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
  82                              <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
  83                              <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
  84                              <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
  85                              <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
  86                              <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
  87                              <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
  88                              <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
  89                              <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
  90                              <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
  91                              <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
  92                              <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
  93                              <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
  94                              <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
  95                              <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
  96                              <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
  97                              <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
  98                              <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
  99                              <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
 100                              <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
 101                              <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
 102                              <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
 103                              <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
 104                              <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
 105                              <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
 106                              <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
 107                              <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
 108                              <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
 109                              <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
 110                              <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
 111                              <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
 112                              <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
 113                 interrupt-names = "nmi",
 114                                   "irq0", "irq1", "irq2", "irq3",
 115                                   "irq4", "irq5", "irq6", "irq7",
 116                                   "tint0", "tint1", "tint2", "tint3",
 117                                   "tint4", "tint5", "tint6", "tint7",
 118                                   "tint8", "tint9", "tint10", "tint11",
 119                                   "tint12", "tint13", "tint14", "tint15",
 120                                   "tint16", "tint17", "tint18", "tint19",
 121                                   "tint20", "tint21", "tint22", "tint23",
 122                                   "tint24", "tint25", "tint26", "tint27",
 123                                   "tint28", "tint29", "tint30", "tint31",
 124                                   "bus-err";
 125                 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
 126                         <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
 127                 clock-names = "clk", "pclk";
 128                 power-domains = <&cpg>;
 129                 resets = <&cpg R9A07G043_IA55_RESETN>;
 130         };
 131
 132         gic: interrupt-controller@11900000 {
 133                 compatible = "arm,gic-v3";
 134                 #interrupt-cells = <3>;
 135                 #address-cells = <0>;
 136                 interrupt-controller;
 137                 reg = <0x0 0x11900000 0 0x40000>,
 138                       <0x0 0x11940000 0 0x60000>;
 139                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 140         };
 141 };
 142
 143 &sysc {
 144         interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
 145                      <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
 146                      <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
 147                      <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
 148         interrupt-names = "lpm_int", "ca55stbydone_int",
 149                           "cm33stbyr_int", "ca55_deny";
 150 };