1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL SoC
5 * Copyright (C) 2022 Renesas Electronics Corp.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
12 #include "r9a07g043.dtsi"
20 compatible = "arm,cortex-a55";
24 next-level-cache = <&L3_CA55>;
25 enable-method = "psci";
26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
27 operating-points-v2 = <&cluster0_opp>;
30 L3_CA55: cache-controller-0 {
33 cache-size = <0x40000>;
38 compatible = "arm,psci-1.0", "arm,psci-0.2";
43 compatible = "arm,armv8-timer";
44 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
45 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
46 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
47 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
54 irqc: interrupt-controller@110a0000 {
55 compatible = "renesas,r9a07g043u-irqc",
57 reg = <0 0x110a0000 0 0x10000>;
58 #interrupt-cells = <2>;
61 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
62 <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
63 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
64 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
65 <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
66 <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
67 <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
68 <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
69 <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
70 <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
71 <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
72 <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
73 <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
74 <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
75 <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
76 <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
77 <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
78 <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
79 <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
80 <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
81 <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
82 <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
83 <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
84 <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
85 <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
86 <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
87 <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
88 <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
89 <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
90 <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
91 <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
92 <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
93 <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
94 <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
95 <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
96 <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
97 <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
98 <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
99 <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
100 <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
101 <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
102 <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
103 <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
104 <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
105 <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
106 <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
107 <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
108 <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
109 interrupt-names = "nmi",
110 "irq0", "irq1", "irq2", "irq3",
111 "irq4", "irq5", "irq6", "irq7",
112 "tint0", "tint1", "tint2", "tint3",
113 "tint4", "tint5", "tint6", "tint7",
114 "tint8", "tint9", "tint10", "tint11",
115 "tint12", "tint13", "tint14", "tint15",
116 "tint16", "tint17", "tint18", "tint19",
117 "tint20", "tint21", "tint22", "tint23",
118 "tint24", "tint25", "tint26", "tint27",
119 "tint28", "tint29", "tint30", "tint31",
120 "bus-err", "ec7tie1-0", "ec7tie2-0",
121 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
123 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
124 <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
125 clock-names = "clk", "pclk";
126 power-domains = <&cpg>;
127 resets = <&cpg R9A07G043_IA55_RESETN>;
130 gic: interrupt-controller@11900000 {
131 compatible = "arm,gic-v3";
132 #interrupt-cells = <3>;
133 #address-cells = <0>;
134 interrupt-controller;
135 reg = <0x0 0x11900000 0 0x40000>,
136 <0x0 0x11940000 0 0x60000>;
137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
142 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
143 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
144 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
145 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "lpm_int", "ca55stbydone_int",
147 "cm33stbyr_int", "ca55_deny";